1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved. 7 */ 8 9 #ifndef __ADRENO_GPU_H__ 10 #define __ADRENO_GPU_H__ 11 12 #include <linux/firmware.h> 13 #include <linux/iopoll.h> 14 15 #include "msm_gpu.h" 16 17 #include "adreno_common.xml.h" 18 #include "adreno_pm4.xml.h" 19 20 extern bool snapshot_debugbus; 21 extern bool allow_vram_carveout; 22 23 enum { 24 ADRENO_FW_PM4 = 0, 25 ADRENO_FW_SQE = 0, /* a6xx */ 26 ADRENO_FW_PFP = 1, 27 ADRENO_FW_GMU = 1, /* a6xx */ 28 ADRENO_FW_GPMU = 2, 29 ADRENO_FW_MAX, 30 }; 31 32 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) 33 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) 34 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) 35 36 struct adreno_rev { 37 uint8_t core; 38 uint8_t major; 39 uint8_t minor; 40 uint8_t patchid; 41 }; 42 43 #define ANY_ID 0xff 44 45 #define ADRENO_REV(core, major, minor, patchid) \ 46 ((struct adreno_rev){ core, major, minor, patchid }) 47 48 struct adreno_gpu_funcs { 49 struct msm_gpu_funcs base; 50 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 51 }; 52 53 struct adreno_reglist { 54 u32 offset; 55 u32 value; 56 }; 57 58 extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; 59 60 struct adreno_info { 61 struct adreno_rev rev; 62 uint32_t revn; 63 const char *name; 64 const char *fw[ADRENO_FW_MAX]; 65 uint32_t gmem; 66 u64 quirks; 67 struct msm_gpu *(*init)(struct drm_device *dev); 68 const char *zapfw; 69 u32 inactive_period; 70 const struct adreno_reglist *hwcg; 71 u64 address_space_size; 72 }; 73 74 const struct adreno_info *adreno_info(struct adreno_rev rev); 75 76 struct adreno_gpu { 77 struct msm_gpu base; 78 struct adreno_rev rev; 79 const struct adreno_info *info; 80 uint32_t gmem; /* actual gmem size */ 81 uint32_t revn; /* numeric revision name */ 82 uint16_t speedbin; 83 const struct adreno_gpu_funcs *funcs; 84 85 /* interesting register offsets to dump: */ 86 const unsigned int *registers; 87 88 /* 89 * Are we loading fw from legacy path? Prior to addition 90 * of gpu firmware to linux-firmware, the fw files were 91 * placed in toplevel firmware directory, following qcom's 92 * android kernel. But linux-firmware preferred they be 93 * placed in a 'qcom' subdirectory. 94 * 95 * For backwards compatibility, we try first to load from 96 * the new path, using request_firmware_direct() to avoid 97 * any potential timeout waiting for usermode helper, then 98 * fall back to the old path (with direct load). And 99 * finally fall back to request_firmware() with the new 100 * path to allow the usermode helper. 101 */ 102 enum { 103 FW_LOCATION_UNKNOWN = 0, 104 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 105 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 106 FW_LOCATION_HELPER, 107 } fwloc; 108 109 /* firmware: */ 110 const struct firmware *fw[ADRENO_FW_MAX]; 111 112 /* 113 * Register offsets are different between some GPUs. 114 * GPU specific offsets will be exported by GPU specific 115 * code (a3xx_gpu.c) and stored in this common location. 116 */ 117 const unsigned int *reg_offsets; 118 }; 119 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 120 121 struct adreno_ocmem { 122 struct ocmem *ocmem; 123 unsigned long base; 124 void *hdl; 125 }; 126 127 /* platform config data (ie. from DT, or pdata) */ 128 struct adreno_platform_config { 129 struct adreno_rev rev; 130 }; 131 132 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 133 134 #define spin_until(X) ({ \ 135 int __ret = -ETIMEDOUT; \ 136 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 137 do { \ 138 if (X) { \ 139 __ret = 0; \ 140 break; \ 141 } \ 142 } while (time_before(jiffies, __t)); \ 143 __ret; \ 144 }) 145 146 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); 147 148 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) 149 { 150 return (gpu->revn < 300); 151 } 152 153 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) 154 { 155 return (gpu->revn < 210); 156 } 157 158 static inline bool adreno_is_a225(struct adreno_gpu *gpu) 159 { 160 return gpu->revn == 225; 161 } 162 163 static inline bool adreno_is_a305(struct adreno_gpu *gpu) 164 { 165 return gpu->revn == 305; 166 } 167 168 static inline bool adreno_is_a306(struct adreno_gpu *gpu) 169 { 170 /* yes, 307, because a305c is 306 */ 171 return gpu->revn == 307; 172 } 173 174 static inline bool adreno_is_a320(struct adreno_gpu *gpu) 175 { 176 return gpu->revn == 320; 177 } 178 179 static inline bool adreno_is_a330(struct adreno_gpu *gpu) 180 { 181 return gpu->revn == 330; 182 } 183 184 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu) 185 { 186 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 187 } 188 189 static inline int adreno_is_a405(struct adreno_gpu *gpu) 190 { 191 return gpu->revn == 405; 192 } 193 194 static inline int adreno_is_a420(struct adreno_gpu *gpu) 195 { 196 return gpu->revn == 420; 197 } 198 199 static inline int adreno_is_a430(struct adreno_gpu *gpu) 200 { 201 return gpu->revn == 430; 202 } 203 204 static inline int adreno_is_a506(struct adreno_gpu *gpu) 205 { 206 return gpu->revn == 506; 207 } 208 209 static inline int adreno_is_a508(struct adreno_gpu *gpu) 210 { 211 return gpu->revn == 508; 212 } 213 214 static inline int adreno_is_a509(struct adreno_gpu *gpu) 215 { 216 return gpu->revn == 509; 217 } 218 219 static inline int adreno_is_a510(struct adreno_gpu *gpu) 220 { 221 return gpu->revn == 510; 222 } 223 224 static inline int adreno_is_a512(struct adreno_gpu *gpu) 225 { 226 return gpu->revn == 512; 227 } 228 229 static inline int adreno_is_a530(struct adreno_gpu *gpu) 230 { 231 return gpu->revn == 530; 232 } 233 234 static inline int adreno_is_a540(struct adreno_gpu *gpu) 235 { 236 return gpu->revn == 540; 237 } 238 239 static inline int adreno_is_a618(struct adreno_gpu *gpu) 240 { 241 return gpu->revn == 618; 242 } 243 244 static inline int adreno_is_a619(struct adreno_gpu *gpu) 245 { 246 return gpu->revn == 619; 247 } 248 249 static inline int adreno_is_a630(struct adreno_gpu *gpu) 250 { 251 return gpu->revn == 630; 252 } 253 254 static inline int adreno_is_a640_family(struct adreno_gpu *gpu) 255 { 256 return (gpu->revn == 640) || (gpu->revn == 680); 257 } 258 259 static inline int adreno_is_a650(struct adreno_gpu *gpu) 260 { 261 return gpu->revn == 650; 262 } 263 264 static inline int adreno_is_7c3(struct adreno_gpu *gpu) 265 { 266 /* The order of args is important here to handle ANY_ID correctly */ 267 return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev); 268 } 269 270 static inline int adreno_is_a660(struct adreno_gpu *gpu) 271 { 272 return gpu->revn == 660; 273 } 274 275 /* check for a615, a616, a618, a619 or any derivatives */ 276 static inline int adreno_is_a615_family(struct adreno_gpu *gpu) 277 { 278 return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619; 279 } 280 281 static inline int adreno_is_a660_family(struct adreno_gpu *gpu) 282 { 283 return adreno_is_a660(gpu) || adreno_is_7c3(gpu); 284 } 285 286 /* check for a650, a660, or any derivatives */ 287 static inline int adreno_is_a650_family(struct adreno_gpu *gpu) 288 { 289 return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu); 290 } 291 292 u64 adreno_private_address_space_size(struct msm_gpu *gpu); 293 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 294 uint32_t param, uint64_t *value, uint32_t *len); 295 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 296 uint32_t param, uint64_t value, uint32_t len); 297 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 298 const char *fwname); 299 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 300 const struct firmware *fw, u64 *iova); 301 int adreno_hw_init(struct msm_gpu *gpu); 302 void adreno_recover(struct msm_gpu *gpu); 303 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg); 304 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 305 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 306 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 307 struct drm_printer *p); 308 #endif 309 void adreno_dump_info(struct msm_gpu *gpu); 310 void adreno_dump(struct msm_gpu *gpu); 311 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 312 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 313 314 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 315 struct adreno_ocmem *ocmem); 316 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem); 317 318 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 319 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 320 int nr_rings); 321 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 322 int adreno_load_fw(struct adreno_gpu *adreno_gpu); 323 324 void adreno_gpu_state_destroy(struct msm_gpu_state *state); 325 326 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); 327 int adreno_gpu_state_put(struct msm_gpu_state *state); 328 void adreno_show_object(struct drm_printer *p, void **ptr, int len, 329 bool *encoded); 330 331 /* 332 * Common helper function to initialize the default address space for arm-smmu 333 * attached targets 334 */ 335 struct msm_gem_address_space * 336 adreno_create_address_space(struct msm_gpu *gpu, 337 struct platform_device *pdev); 338 339 struct msm_gem_address_space * 340 adreno_iommu_create_address_space(struct msm_gpu *gpu, 341 struct platform_device *pdev, 342 unsigned long quirks); 343 344 int adreno_read_speedbin(struct device *dev, u32 *speedbin); 345 346 /* 347 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU 348 * out of secure mode 349 */ 350 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); 351 352 /* ringbuffer helpers (the parts that are adreno specific) */ 353 354 static inline void 355 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 356 { 357 adreno_wait_ring(ring, cnt+1); 358 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 359 } 360 361 /* no-op packet: */ 362 static inline void 363 OUT_PKT2(struct msm_ringbuffer *ring) 364 { 365 adreno_wait_ring(ring, 1); 366 OUT_RING(ring, CP_TYPE2_PKT); 367 } 368 369 static inline void 370 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 371 { 372 adreno_wait_ring(ring, cnt+1); 373 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 374 } 375 376 static inline u32 PM4_PARITY(u32 val) 377 { 378 return (0x9669 >> (0xF & (val ^ 379 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 380 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 381 (val >> 28)))) & 1; 382 } 383 384 /* Maximum number of values that can be executed for one opcode */ 385 #define TYPE4_MAX_PAYLOAD 127 386 387 #define PKT4(_reg, _cnt) \ 388 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 389 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 390 391 static inline void 392 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 393 { 394 adreno_wait_ring(ring, cnt + 1); 395 OUT_RING(ring, PKT4(regindx, cnt)); 396 } 397 398 static inline void 399 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 400 { 401 adreno_wait_ring(ring, cnt + 1); 402 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 403 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 404 } 405 406 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); 407 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 408 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 409 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 410 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); 411 412 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 413 { 414 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 415 } 416 417 /* 418 * Given a register and a count, return a value to program into 419 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 420 * registers starting at _reg. 421 * 422 * The register base needs to be a multiple of the length. If it is not, the 423 * hardware will quietly mask off the bits for you and shift the size. For 424 * example, if you intend the protection to start at 0x07 for a length of 4 425 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 426 * expose registers you intended to protect! 427 */ 428 #define ADRENO_PROTECT_RW(_reg, _len) \ 429 ((1 << 30) | (1 << 29) | \ 430 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 431 432 /* 433 * Same as above, but allow reads over the range. For areas of mixed use (such 434 * as performance counters) this allows us to protect a much larger range with a 435 * single register 436 */ 437 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 438 ((1 << 29) \ 439 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 440 441 442 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ 443 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ 444 interval, timeout) 445 446 #endif /* __ADRENO_GPU_H__ */ 447