1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 #include "msm_gem.h" 22 #include "msm_mmu.h" 23 24 #define RB_SIZE SZ_32K 25 #define RB_BLKSIZE 32 26 27 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 28 { 29 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 30 31 switch (param) { 32 case MSM_PARAM_GPU_ID: 33 *value = adreno_gpu->info->revn; 34 return 0; 35 case MSM_PARAM_GMEM_SIZE: 36 *value = adreno_gpu->gmem; 37 return 0; 38 case MSM_PARAM_CHIP_ID: 39 *value = adreno_gpu->rev.patchid | 40 (adreno_gpu->rev.minor << 8) | 41 (adreno_gpu->rev.major << 16) | 42 (adreno_gpu->rev.core << 24); 43 return 0; 44 case MSM_PARAM_MAX_FREQ: 45 *value = adreno_gpu->base.fast_rate; 46 return 0; 47 case MSM_PARAM_TIMESTAMP: 48 if (adreno_gpu->funcs->get_timestamp) 49 return adreno_gpu->funcs->get_timestamp(gpu, value); 50 return -EINVAL; 51 default: 52 DBG("%s: invalid param: %u", gpu->name, param); 53 return -EINVAL; 54 } 55 } 56 57 int adreno_hw_init(struct msm_gpu *gpu) 58 { 59 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 60 int ret; 61 62 DBG("%s", gpu->name); 63 64 ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova); 65 if (ret) { 66 gpu->rb_iova = 0; 67 dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret); 68 return ret; 69 } 70 71 /* Setup REG_CP_RB_CNTL: */ 72 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, 73 /* size is log2(quad-words): */ 74 AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | 75 AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) | 76 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); 77 78 /* Setup ringbuffer address: */ 79 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, 80 REG_ADRENO_CP_RB_BASE_HI, gpu->rb_iova); 81 82 if (!adreno_is_a430(adreno_gpu)) { 83 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, 84 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 85 rbmemptr(adreno_gpu, rptr)); 86 } 87 88 return 0; 89 } 90 91 static uint32_t get_wptr(struct msm_ringbuffer *ring) 92 { 93 return ring->cur - ring->start; 94 } 95 96 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 97 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu) 98 { 99 if (adreno_is_a430(adreno_gpu)) 100 return adreno_gpu->memptrs->rptr = adreno_gpu_read( 101 adreno_gpu, REG_ADRENO_CP_RB_RPTR); 102 else 103 return adreno_gpu->memptrs->rptr; 104 } 105 106 uint32_t adreno_last_fence(struct msm_gpu *gpu) 107 { 108 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 109 return adreno_gpu->memptrs->fence; 110 } 111 112 void adreno_recover(struct msm_gpu *gpu) 113 { 114 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 115 struct drm_device *dev = gpu->dev; 116 int ret; 117 118 gpu->funcs->pm_suspend(gpu); 119 120 /* reset ringbuffer: */ 121 gpu->rb->cur = gpu->rb->start; 122 123 /* reset completed fence seqno: */ 124 adreno_gpu->memptrs->fence = gpu->fctx->completed_fence; 125 adreno_gpu->memptrs->rptr = 0; 126 adreno_gpu->memptrs->wptr = 0; 127 128 gpu->funcs->pm_resume(gpu); 129 130 disable_irq(gpu->irq); 131 ret = gpu->funcs->hw_init(gpu); 132 if (ret) { 133 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 134 /* hmm, oh well? */ 135 } 136 enable_irq(gpu->irq); 137 } 138 139 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 140 struct msm_file_private *ctx) 141 { 142 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 143 struct msm_drm_private *priv = gpu->dev->dev_private; 144 struct msm_ringbuffer *ring = gpu->rb; 145 unsigned i; 146 147 for (i = 0; i < submit->nr_cmds; i++) { 148 switch (submit->cmd[i].type) { 149 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 150 /* ignore IB-targets */ 151 break; 152 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 153 /* ignore if there has not been a ctx switch: */ 154 if (priv->lastctx == ctx) 155 break; 156 case MSM_SUBMIT_CMD_BUF: 157 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? 158 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); 159 OUT_RING(ring, submit->cmd[i].iova); 160 OUT_RING(ring, submit->cmd[i].size); 161 OUT_PKT2(ring); 162 break; 163 } 164 } 165 166 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); 167 OUT_RING(ring, submit->fence->seqno); 168 169 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) { 170 /* Flush HLSQ lazy updates to make sure there is nothing 171 * pending for indirect loads after the timestamp has 172 * passed: 173 */ 174 OUT_PKT3(ring, CP_EVENT_WRITE, 1); 175 OUT_RING(ring, HLSQ_FLUSH); 176 177 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 178 OUT_RING(ring, 0x00000000); 179 } 180 181 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 182 OUT_RING(ring, CACHE_FLUSH_TS); 183 OUT_RING(ring, rbmemptr(adreno_gpu, fence)); 184 OUT_RING(ring, submit->fence->seqno); 185 186 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */ 187 OUT_PKT3(ring, CP_INTERRUPT, 1); 188 OUT_RING(ring, 0x80000000); 189 190 /* Workaround for missing irq issue on 8x16/a306. Unsure if the 191 * root cause is a platform issue or some a306 quirk, but this 192 * keeps things humming along: 193 */ 194 if (adreno_is_a306(adreno_gpu)) { 195 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 196 OUT_RING(ring, 0x00000000); 197 OUT_PKT3(ring, CP_INTERRUPT, 1); 198 OUT_RING(ring, 0x80000000); 199 } 200 201 #if 0 202 if (adreno_is_a3xx(adreno_gpu)) { 203 /* Dummy set-constant to trigger context rollover */ 204 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 205 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); 206 OUT_RING(ring, 0x00000000); 207 } 208 #endif 209 210 gpu->funcs->flush(gpu); 211 } 212 213 void adreno_flush(struct msm_gpu *gpu) 214 { 215 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 216 uint32_t wptr = get_wptr(gpu->rb); 217 218 /* ensure writes to ringbuffer have hit system memory: */ 219 mb(); 220 221 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); 222 } 223 224 bool adreno_idle(struct msm_gpu *gpu) 225 { 226 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 227 uint32_t wptr = get_wptr(gpu->rb); 228 229 /* wait for CP to drain ringbuffer: */ 230 if (!spin_until(get_rptr(adreno_gpu) == wptr)) 231 return true; 232 233 /* TODO maybe we need to reset GPU here to recover from hang? */ 234 DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); 235 return false; 236 } 237 238 #ifdef CONFIG_DEBUG_FS 239 void adreno_show(struct msm_gpu *gpu, struct seq_file *m) 240 { 241 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 242 int i; 243 244 seq_printf(m, "revision: %d (%d.%d.%d.%d)\n", 245 adreno_gpu->info->revn, adreno_gpu->rev.core, 246 adreno_gpu->rev.major, adreno_gpu->rev.minor, 247 adreno_gpu->rev.patchid); 248 249 seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, 250 gpu->fctx->last_fence); 251 seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu)); 252 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); 253 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); 254 255 gpu->funcs->pm_resume(gpu); 256 257 /* dump these out in a form that can be parsed by demsm: */ 258 seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name); 259 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 260 uint32_t start = adreno_gpu->registers[i]; 261 uint32_t end = adreno_gpu->registers[i+1]; 262 uint32_t addr; 263 264 for (addr = start; addr <= end; addr++) { 265 uint32_t val = gpu_read(gpu, addr); 266 seq_printf(m, "IO:R %08x %08x\n", addr<<2, val); 267 } 268 } 269 270 gpu->funcs->pm_suspend(gpu); 271 } 272 #endif 273 274 /* Dump common gpu status and scratch registers on any hang, to make 275 * the hangcheck logs more useful. The scratch registers seem always 276 * safe to read when GPU has hung (unlike some other regs, depending 277 * on how the GPU hung), and they are useful to match up to cmdstream 278 * dumps when debugging hangs: 279 */ 280 void adreno_dump_info(struct msm_gpu *gpu) 281 { 282 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 283 284 printk("revision: %d (%d.%d.%d.%d)\n", 285 adreno_gpu->info->revn, adreno_gpu->rev.core, 286 adreno_gpu->rev.major, adreno_gpu->rev.minor, 287 adreno_gpu->rev.patchid); 288 289 printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, 290 gpu->fctx->last_fence); 291 printk("rptr: %d\n", get_rptr(adreno_gpu)); 292 printk("wptr: %d\n", adreno_gpu->memptrs->wptr); 293 printk("rb wptr: %d\n", get_wptr(gpu->rb)); 294 } 295 296 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 297 void adreno_dump(struct msm_gpu *gpu) 298 { 299 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 300 int i; 301 302 /* dump these out in a form that can be parsed by demsm: */ 303 printk("IO:region %s 00000000 00020000\n", gpu->name); 304 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 305 uint32_t start = adreno_gpu->registers[i]; 306 uint32_t end = adreno_gpu->registers[i+1]; 307 uint32_t addr; 308 309 for (addr = start; addr <= end; addr++) { 310 uint32_t val = gpu_read(gpu, addr); 311 printk("IO:R %08x %08x\n", addr<<2, val); 312 } 313 } 314 } 315 316 static uint32_t ring_freewords(struct msm_gpu *gpu) 317 { 318 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 319 uint32_t size = gpu->rb->size / 4; 320 uint32_t wptr = get_wptr(gpu->rb); 321 uint32_t rptr = get_rptr(adreno_gpu); 322 return (rptr + (size - 1) - wptr) % size; 323 } 324 325 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) 326 { 327 if (spin_until(ring_freewords(gpu) >= ndwords)) 328 DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); 329 } 330 331 static const char *iommu_ports[] = { 332 "gfx3d_user", "gfx3d_priv", 333 "gfx3d1_user", "gfx3d1_priv", 334 }; 335 336 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 337 struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs) 338 { 339 struct adreno_platform_config *config = pdev->dev.platform_data; 340 struct msm_gpu *gpu = &adreno_gpu->base; 341 struct msm_mmu *mmu; 342 int ret; 343 344 adreno_gpu->funcs = funcs; 345 adreno_gpu->info = adreno_info(config->rev); 346 adreno_gpu->gmem = adreno_gpu->info->gmem; 347 adreno_gpu->revn = adreno_gpu->info->revn; 348 adreno_gpu->rev = config->rev; 349 adreno_gpu->quirks = config->quirks; 350 351 gpu->fast_rate = config->fast_rate; 352 gpu->slow_rate = config->slow_rate; 353 gpu->bus_freq = config->bus_freq; 354 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 355 gpu->bus_scale_table = config->bus_scale_table; 356 #endif 357 358 DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u", 359 gpu->fast_rate, gpu->slow_rate, gpu->bus_freq); 360 361 ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 362 adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq", 363 RB_SIZE); 364 if (ret) 365 return ret; 366 367 ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev); 368 if (ret) { 369 dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", 370 adreno_gpu->info->pm4fw, ret); 371 return ret; 372 } 373 374 ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev); 375 if (ret) { 376 dev_err(drm->dev, "failed to load %s PFP firmware: %d\n", 377 adreno_gpu->info->pfpfw, ret); 378 return ret; 379 } 380 381 mmu = gpu->aspace->mmu; 382 if (mmu) { 383 ret = mmu->funcs->attach(mmu, iommu_ports, 384 ARRAY_SIZE(iommu_ports)); 385 if (ret) 386 return ret; 387 } 388 389 mutex_lock(&drm->struct_mutex); 390 adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), 391 MSM_BO_UNCACHED); 392 mutex_unlock(&drm->struct_mutex); 393 if (IS_ERR(adreno_gpu->memptrs_bo)) { 394 ret = PTR_ERR(adreno_gpu->memptrs_bo); 395 adreno_gpu->memptrs_bo = NULL; 396 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); 397 return ret; 398 } 399 400 adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo); 401 if (IS_ERR(adreno_gpu->memptrs)) { 402 dev_err(drm->dev, "could not vmap memptrs\n"); 403 return -ENOMEM; 404 } 405 406 ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id, 407 &adreno_gpu->memptrs_iova); 408 if (ret) { 409 dev_err(drm->dev, "could not map memptrs: %d\n", ret); 410 return ret; 411 } 412 413 return 0; 414 } 415 416 void adreno_gpu_cleanup(struct adreno_gpu *gpu) 417 { 418 if (gpu->memptrs_bo) { 419 if (gpu->memptrs) 420 msm_gem_put_vaddr(gpu->memptrs_bo); 421 422 if (gpu->memptrs_iova) 423 msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id); 424 425 drm_gem_object_unreference_unlocked(gpu->memptrs_bo); 426 } 427 release_firmware(gpu->pm4); 428 release_firmware(gpu->pfp); 429 msm_gpu_cleanup(&gpu->base); 430 } 431