1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 22 #define ANY_ID 0xff 23 24 bool hang_debug = false; 25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 26 module_param_named(hang_debug, hang_debug, bool, 0600); 27 28 static const struct adreno_info gpulist[] = { 29 { 30 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 31 .revn = 305, 32 .name = "A305", 33 .pm4fw = "a300_pm4.fw", 34 .pfpfw = "a300_pfp.fw", 35 .gmem = SZ_256K, 36 .init = a3xx_gpu_init, 37 }, { 38 .rev = ADRENO_REV(3, 0, 6, 0), 39 .revn = 307, /* because a305c is revn==306 */ 40 .name = "A306", 41 .pm4fw = "a300_pm4.fw", 42 .pfpfw = "a300_pfp.fw", 43 .gmem = SZ_128K, 44 .init = a3xx_gpu_init, 45 }, { 46 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 47 .revn = 320, 48 .name = "A320", 49 .pm4fw = "a300_pm4.fw", 50 .pfpfw = "a300_pfp.fw", 51 .gmem = SZ_512K, 52 .init = a3xx_gpu_init, 53 }, { 54 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 55 .revn = 330, 56 .name = "A330", 57 .pm4fw = "a330_pm4.fw", 58 .pfpfw = "a330_pfp.fw", 59 .gmem = SZ_1M, 60 .init = a3xx_gpu_init, 61 }, { 62 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 63 .revn = 420, 64 .name = "A420", 65 .pm4fw = "a420_pm4.fw", 66 .pfpfw = "a420_pfp.fw", 67 .gmem = (SZ_1M + SZ_512K), 68 .init = a4xx_gpu_init, 69 }, { 70 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 71 .revn = 430, 72 .name = "A430", 73 .pm4fw = "a420_pm4.fw", 74 .pfpfw = "a420_pfp.fw", 75 .gmem = (SZ_1M + SZ_512K), 76 .init = a4xx_gpu_init, 77 }, { 78 .rev = ADRENO_REV(5, 3, 0, ANY_ID), 79 .revn = 530, 80 .name = "A530", 81 .pm4fw = "a530_pm4.fw", 82 .pfpfw = "a530_pfp.fw", 83 .gmem = SZ_1M, 84 .init = a5xx_gpu_init, 85 .gpmufw = "a530v3_gpmu.fw2", 86 }, 87 }; 88 89 MODULE_FIRMWARE("a300_pm4.fw"); 90 MODULE_FIRMWARE("a300_pfp.fw"); 91 MODULE_FIRMWARE("a330_pm4.fw"); 92 MODULE_FIRMWARE("a330_pfp.fw"); 93 MODULE_FIRMWARE("a420_pm4.fw"); 94 MODULE_FIRMWARE("a420_pfp.fw"); 95 MODULE_FIRMWARE("a530_fm4.fw"); 96 MODULE_FIRMWARE("a530_pfp.fw"); 97 98 static inline bool _rev_match(uint8_t entry, uint8_t id) 99 { 100 return (entry == ANY_ID) || (entry == id); 101 } 102 103 const struct adreno_info *adreno_info(struct adreno_rev rev) 104 { 105 int i; 106 107 /* identify gpu: */ 108 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 109 const struct adreno_info *info = &gpulist[i]; 110 if (_rev_match(info->rev.core, rev.core) && 111 _rev_match(info->rev.major, rev.major) && 112 _rev_match(info->rev.minor, rev.minor) && 113 _rev_match(info->rev.patchid, rev.patchid)) 114 return info; 115 } 116 117 return NULL; 118 } 119 120 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 121 { 122 struct msm_drm_private *priv = dev->dev_private; 123 struct platform_device *pdev = priv->gpu_pdev; 124 struct adreno_platform_config *config; 125 struct adreno_rev rev; 126 const struct adreno_info *info; 127 struct msm_gpu *gpu = NULL; 128 129 if (!pdev) { 130 dev_err(dev->dev, "no adreno device\n"); 131 return NULL; 132 } 133 134 config = pdev->dev.platform_data; 135 rev = config->rev; 136 info = adreno_info(config->rev); 137 138 if (!info) { 139 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 140 rev.core, rev.major, rev.minor, rev.patchid); 141 return NULL; 142 } 143 144 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major, 145 rev.minor, rev.patchid); 146 147 gpu = info->init(dev); 148 if (IS_ERR(gpu)) { 149 dev_warn(dev->dev, "failed to load adreno gpu\n"); 150 gpu = NULL; 151 /* not fatal */ 152 } 153 154 if (gpu) { 155 int ret; 156 mutex_lock(&dev->struct_mutex); 157 gpu->funcs->pm_resume(gpu); 158 mutex_unlock(&dev->struct_mutex); 159 160 disable_irq(gpu->irq); 161 162 ret = gpu->funcs->hw_init(gpu); 163 if (ret) { 164 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 165 gpu->funcs->destroy(gpu); 166 gpu = NULL; 167 } else { 168 enable_irq(gpu->irq); 169 /* give inactive pm a chance to kick in: */ 170 msm_gpu_retire(gpu); 171 } 172 } 173 174 return gpu; 175 } 176 177 static void set_gpu_pdev(struct drm_device *dev, 178 struct platform_device *pdev) 179 { 180 struct msm_drm_private *priv = dev->dev_private; 181 priv->gpu_pdev = pdev; 182 } 183 184 static const struct { 185 const char *str; 186 uint32_t flag; 187 } quirks[] = { 188 { "qcom,gpu-quirk-two-pass-use-wfi", ADRENO_QUIRK_TWO_PASS_USE_WFI }, 189 { "qcom,gpu-quirk-fault-detect-mask", ADRENO_QUIRK_FAULT_DETECT_MASK }, 190 }; 191 192 static int adreno_bind(struct device *dev, struct device *master, void *data) 193 { 194 static struct adreno_platform_config config = {}; 195 struct device_node *child, *node = dev->of_node; 196 u32 val; 197 int ret, i; 198 199 ret = of_property_read_u32(node, "qcom,chipid", &val); 200 if (ret) { 201 dev_err(dev, "could not find chipid: %d\n", ret); 202 return ret; 203 } 204 205 config.rev = ADRENO_REV((val >> 24) & 0xff, 206 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); 207 208 /* find clock rates: */ 209 config.fast_rate = 0; 210 config.slow_rate = ~0; 211 for_each_child_of_node(node, child) { 212 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) { 213 struct device_node *pwrlvl; 214 for_each_child_of_node(child, pwrlvl) { 215 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val); 216 if (ret) { 217 dev_err(dev, "could not find gpu-freq: %d\n", ret); 218 return ret; 219 } 220 config.fast_rate = max(config.fast_rate, val); 221 config.slow_rate = min(config.slow_rate, val); 222 } 223 } 224 } 225 226 if (!config.fast_rate) { 227 dev_err(dev, "could not find clk rates\n"); 228 return -ENXIO; 229 } 230 231 for (i = 0; i < ARRAY_SIZE(quirks); i++) 232 if (of_property_read_bool(node, quirks[i].str)) 233 config.quirks |= quirks[i].flag; 234 235 dev->platform_data = &config; 236 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev)); 237 return 0; 238 } 239 240 static void adreno_unbind(struct device *dev, struct device *master, 241 void *data) 242 { 243 set_gpu_pdev(dev_get_drvdata(master), NULL); 244 } 245 246 static const struct component_ops a3xx_ops = { 247 .bind = adreno_bind, 248 .unbind = adreno_unbind, 249 }; 250 251 static int adreno_probe(struct platform_device *pdev) 252 { 253 return component_add(&pdev->dev, &a3xx_ops); 254 } 255 256 static int adreno_remove(struct platform_device *pdev) 257 { 258 component_del(&pdev->dev, &a3xx_ops); 259 return 0; 260 } 261 262 static const struct of_device_id dt_match[] = { 263 { .compatible = "qcom,adreno-3xx" }, 264 /* for backwards compat w/ downstream kgsl DT files: */ 265 { .compatible = "qcom,kgsl-3d0" }, 266 {} 267 }; 268 269 static struct platform_driver adreno_driver = { 270 .probe = adreno_probe, 271 .remove = adreno_remove, 272 .driver = { 273 .name = "adreno", 274 .of_match_table = dt_match, 275 }, 276 }; 277 278 void __init adreno_register(void) 279 { 280 platform_driver_register(&adreno_driver); 281 } 282 283 void __exit adreno_unregister(void) 284 { 285 platform_driver_unregister(&adreno_driver); 286 } 287