1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 11 bool hang_debug = false; 12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 13 module_param_named(hang_debug, hang_debug, bool, 0600); 14 15 bool snapshot_debugbus = false; 16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)"); 17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600); 18 19 bool allow_vram_carveout = false; 20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); 21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); 22 23 static const struct adreno_info gpulist[] = { 24 { 25 .chip_ids = ADRENO_CHIP_IDS(0x02000000), 26 .family = ADRENO_2XX_GEN1, 27 .revn = 200, 28 .fw = { 29 [ADRENO_FW_PM4] = "yamato_pm4.fw", 30 [ADRENO_FW_PFP] = "yamato_pfp.fw", 31 }, 32 .gmem = SZ_256K, 33 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 34 .init = a2xx_gpu_init, 35 }, { /* a200 on i.mx51 has only 128kib gmem */ 36 .chip_ids = ADRENO_CHIP_IDS(0x02000001), 37 .family = ADRENO_2XX_GEN1, 38 .revn = 201, 39 .fw = { 40 [ADRENO_FW_PM4] = "yamato_pm4.fw", 41 [ADRENO_FW_PFP] = "yamato_pfp.fw", 42 }, 43 .gmem = SZ_128K, 44 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 45 .init = a2xx_gpu_init, 46 }, { 47 .chip_ids = ADRENO_CHIP_IDS(0x02020000), 48 .family = ADRENO_2XX_GEN2, 49 .revn = 220, 50 .fw = { 51 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 52 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 53 }, 54 .gmem = SZ_512K, 55 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 56 .init = a2xx_gpu_init, 57 }, { 58 .chip_ids = ADRENO_CHIP_IDS( 59 0x03000512, 60 0x03000520 61 ), 62 .family = ADRENO_3XX, 63 .revn = 305, 64 .fw = { 65 [ADRENO_FW_PM4] = "a300_pm4.fw", 66 [ADRENO_FW_PFP] = "a300_pfp.fw", 67 }, 68 .gmem = SZ_256K, 69 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 70 .init = a3xx_gpu_init, 71 }, { 72 .chip_ids = ADRENO_CHIP_IDS(0x03000600), 73 .family = ADRENO_3XX, 74 .revn = 307, /* because a305c is revn==306 */ 75 .fw = { 76 [ADRENO_FW_PM4] = "a300_pm4.fw", 77 [ADRENO_FW_PFP] = "a300_pfp.fw", 78 }, 79 .gmem = SZ_128K, 80 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 81 .init = a3xx_gpu_init, 82 }, { 83 .chip_ids = ADRENO_CHIP_IDS( 84 0x03020000, 85 0x03020001, 86 0x03020002 87 ), 88 .family = ADRENO_3XX, 89 .revn = 320, 90 .fw = { 91 [ADRENO_FW_PM4] = "a300_pm4.fw", 92 [ADRENO_FW_PFP] = "a300_pfp.fw", 93 }, 94 .gmem = SZ_512K, 95 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 96 .init = a3xx_gpu_init, 97 }, { 98 .chip_ids = ADRENO_CHIP_IDS( 99 0x03030000, 100 0x03030001, 101 0x03030002 102 ), 103 .family = ADRENO_3XX, 104 .revn = 330, 105 .fw = { 106 [ADRENO_FW_PM4] = "a330_pm4.fw", 107 [ADRENO_FW_PFP] = "a330_pfp.fw", 108 }, 109 .gmem = SZ_1M, 110 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 111 .init = a3xx_gpu_init, 112 }, { 113 .chip_ids = ADRENO_CHIP_IDS(0x04000500), 114 .family = ADRENO_4XX, 115 .revn = 405, 116 .fw = { 117 [ADRENO_FW_PM4] = "a420_pm4.fw", 118 [ADRENO_FW_PFP] = "a420_pfp.fw", 119 }, 120 .gmem = SZ_256K, 121 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 122 .init = a4xx_gpu_init, 123 }, { 124 .chip_ids = ADRENO_CHIP_IDS(0x04020000), 125 .family = ADRENO_4XX, 126 .revn = 420, 127 .fw = { 128 [ADRENO_FW_PM4] = "a420_pm4.fw", 129 [ADRENO_FW_PFP] = "a420_pfp.fw", 130 }, 131 .gmem = (SZ_1M + SZ_512K), 132 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 133 .init = a4xx_gpu_init, 134 }, { 135 .chip_ids = ADRENO_CHIP_IDS(0x04030002), 136 .family = ADRENO_4XX, 137 .revn = 430, 138 .fw = { 139 [ADRENO_FW_PM4] = "a420_pm4.fw", 140 [ADRENO_FW_PFP] = "a420_pfp.fw", 141 }, 142 .gmem = (SZ_1M + SZ_512K), 143 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 144 .init = a4xx_gpu_init, 145 }, { 146 .chip_ids = ADRENO_CHIP_IDS(0x05000600), 147 .family = ADRENO_5XX, 148 .revn = 506, 149 .fw = { 150 [ADRENO_FW_PM4] = "a530_pm4.fw", 151 [ADRENO_FW_PFP] = "a530_pfp.fw", 152 }, 153 .gmem = (SZ_128K + SZ_8K), 154 /* 155 * Increase inactive period to 250 to avoid bouncing 156 * the GDSC which appears to make it grumpy 157 */ 158 .inactive_period = 250, 159 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 160 ADRENO_QUIRK_LMLOADKILL_DISABLE, 161 .init = a5xx_gpu_init, 162 .zapfw = "a506_zap.mdt", 163 }, { 164 .chip_ids = ADRENO_CHIP_IDS(0x05000800), 165 .family = ADRENO_5XX, 166 .revn = 508, 167 .fw = { 168 [ADRENO_FW_PM4] = "a530_pm4.fw", 169 [ADRENO_FW_PFP] = "a530_pfp.fw", 170 }, 171 .gmem = (SZ_128K + SZ_8K), 172 /* 173 * Increase inactive period to 250 to avoid bouncing 174 * the GDSC which appears to make it grumpy 175 */ 176 .inactive_period = 250, 177 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 178 .init = a5xx_gpu_init, 179 .zapfw = "a508_zap.mdt", 180 }, { 181 .chip_ids = ADRENO_CHIP_IDS(0x05000900), 182 .family = ADRENO_5XX, 183 .revn = 509, 184 .fw = { 185 [ADRENO_FW_PM4] = "a530_pm4.fw", 186 [ADRENO_FW_PFP] = "a530_pfp.fw", 187 }, 188 .gmem = (SZ_256K + SZ_16K), 189 /* 190 * Increase inactive period to 250 to avoid bouncing 191 * the GDSC which appears to make it grumpy 192 */ 193 .inactive_period = 250, 194 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 195 .init = a5xx_gpu_init, 196 /* Adreno 509 uses the same ZAP as 512 */ 197 .zapfw = "a512_zap.mdt", 198 }, { 199 .chip_ids = ADRENO_CHIP_IDS(0x05010000), 200 .family = ADRENO_5XX, 201 .revn = 510, 202 .fw = { 203 [ADRENO_FW_PM4] = "a530_pm4.fw", 204 [ADRENO_FW_PFP] = "a530_pfp.fw", 205 }, 206 .gmem = SZ_256K, 207 /* 208 * Increase inactive period to 250 to avoid bouncing 209 * the GDSC which appears to make it grumpy 210 */ 211 .inactive_period = 250, 212 .init = a5xx_gpu_init, 213 }, { 214 .chip_ids = ADRENO_CHIP_IDS(0x05010200), 215 .family = ADRENO_5XX, 216 .revn = 512, 217 .fw = { 218 [ADRENO_FW_PM4] = "a530_pm4.fw", 219 [ADRENO_FW_PFP] = "a530_pfp.fw", 220 }, 221 .gmem = (SZ_256K + SZ_16K), 222 /* 223 * Increase inactive period to 250 to avoid bouncing 224 * the GDSC which appears to make it grumpy 225 */ 226 .inactive_period = 250, 227 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 228 .init = a5xx_gpu_init, 229 .zapfw = "a512_zap.mdt", 230 }, { 231 .chip_ids = ADRENO_CHIP_IDS( 232 0x05030002, 233 0x05030004 234 ), 235 .family = ADRENO_5XX, 236 .revn = 530, 237 .fw = { 238 [ADRENO_FW_PM4] = "a530_pm4.fw", 239 [ADRENO_FW_PFP] = "a530_pfp.fw", 240 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 241 }, 242 .gmem = SZ_1M, 243 /* 244 * Increase inactive period to 250 to avoid bouncing 245 * the GDSC which appears to make it grumpy 246 */ 247 .inactive_period = 250, 248 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 249 ADRENO_QUIRK_FAULT_DETECT_MASK, 250 .init = a5xx_gpu_init, 251 .zapfw = "a530_zap.mdt", 252 }, { 253 .chip_ids = ADRENO_CHIP_IDS(0x05040001), 254 .family = ADRENO_5XX, 255 .revn = 540, 256 .fw = { 257 [ADRENO_FW_PM4] = "a530_pm4.fw", 258 [ADRENO_FW_PFP] = "a530_pfp.fw", 259 [ADRENO_FW_GPMU] = "a540_gpmu.fw2", 260 }, 261 .gmem = SZ_1M, 262 /* 263 * Increase inactive period to 250 to avoid bouncing 264 * the GDSC which appears to make it grumpy 265 */ 266 .inactive_period = 250, 267 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 268 .init = a5xx_gpu_init, 269 .zapfw = "a540_zap.mdt", 270 }, { 271 .chip_ids = ADRENO_CHIP_IDS(0x06010000), 272 .family = ADRENO_6XX_GEN1, 273 .revn = 610, 274 .fw = { 275 [ADRENO_FW_SQE] = "a630_sqe.fw", 276 }, 277 .gmem = (SZ_128K + SZ_4K), 278 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 279 .init = a6xx_gpu_init, 280 .zapfw = "a610_zap.mdt", 281 .hwcg = a612_hwcg, 282 /* 283 * There are (at least) three SoCs implementing A610: SM6125 284 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does 285 * not have speedbinning, as only a single SKU exists and we 286 * don't support khaje upstream yet. Hence, this matching 287 * table is only valid for bengal. 288 */ 289 .speedbins = ADRENO_SPEEDBINS( 290 { 0, 0 }, 291 { 206, 1 }, 292 { 200, 2 }, 293 { 157, 3 }, 294 { 127, 4 }, 295 ), 296 }, { 297 .chip_ids = ADRENO_CHIP_IDS(0x06010800), 298 .family = ADRENO_6XX_GEN1, 299 .revn = 618, 300 .fw = { 301 [ADRENO_FW_SQE] = "a630_sqe.fw", 302 [ADRENO_FW_GMU] = "a630_gmu.bin", 303 }, 304 .gmem = SZ_512K, 305 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 306 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 307 .init = a6xx_gpu_init, 308 .speedbins = ADRENO_SPEEDBINS( 309 { 0, 0 }, 310 { 169, 1 }, 311 { 174, 2 }, 312 ), 313 }, { 314 .machine = "qcom,sm4350", 315 .chip_ids = ADRENO_CHIP_IDS(0x06010900), 316 .family = ADRENO_6XX_GEN1, 317 .revn = 619, 318 .fw = { 319 [ADRENO_FW_SQE] = "a630_sqe.fw", 320 [ADRENO_FW_GMU] = "a619_gmu.bin", 321 }, 322 .gmem = SZ_512K, 323 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 324 .init = a6xx_gpu_init, 325 .zapfw = "a615_zap.mdt", 326 .hwcg = a615_hwcg, 327 .speedbins = ADRENO_SPEEDBINS( 328 { 0, 0 }, 329 { 138, 1 }, 330 { 92, 2 }, 331 ), 332 }, { 333 .machine = "qcom,sm6375", 334 .chip_ids = ADRENO_CHIP_IDS(0x06010901), 335 .family = ADRENO_6XX_GEN1, 336 .revn = 619, 337 .fw = { 338 [ADRENO_FW_SQE] = "a630_sqe.fw", 339 [ADRENO_FW_GMU] = "a619_gmu.bin", 340 }, 341 .gmem = SZ_512K, 342 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 343 .init = a6xx_gpu_init, 344 .zapfw = "a615_zap.mdt", 345 .hwcg = a615_hwcg, 346 .speedbins = ADRENO_SPEEDBINS( 347 { 0, 0 }, 348 { 190, 1 }, 349 { 177, 2 }, 350 ), 351 }, { 352 .chip_ids = ADRENO_CHIP_IDS(0x06010900), 353 .family = ADRENO_6XX_GEN1, 354 .revn = 619, 355 .fw = { 356 [ADRENO_FW_SQE] = "a630_sqe.fw", 357 [ADRENO_FW_GMU] = "a619_gmu.bin", 358 }, 359 .gmem = SZ_512K, 360 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 361 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 362 .init = a6xx_gpu_init, 363 .zapfw = "a615_zap.mdt", 364 .hwcg = a615_hwcg, 365 .speedbins = ADRENO_SPEEDBINS( 366 { 0, 0 }, 367 { 120, 4 }, 368 { 138, 3 }, 369 { 169, 2 }, 370 { 180, 1 }, 371 ), 372 }, { 373 .chip_ids = ADRENO_CHIP_IDS( 374 0x06030001, 375 0x06030002 376 ), 377 .family = ADRENO_6XX_GEN1, 378 .revn = 630, 379 .fw = { 380 [ADRENO_FW_SQE] = "a630_sqe.fw", 381 [ADRENO_FW_GMU] = "a630_gmu.bin", 382 }, 383 .gmem = SZ_1M, 384 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 385 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 386 .init = a6xx_gpu_init, 387 .zapfw = "a630_zap.mdt", 388 .hwcg = a630_hwcg, 389 }, { 390 .chip_ids = ADRENO_CHIP_IDS(0x06040001), 391 .family = ADRENO_6XX_GEN2, 392 .revn = 640, 393 .fw = { 394 [ADRENO_FW_SQE] = "a630_sqe.fw", 395 [ADRENO_FW_GMU] = "a640_gmu.bin", 396 }, 397 .gmem = SZ_1M, 398 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 399 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 400 .init = a6xx_gpu_init, 401 .zapfw = "a640_zap.mdt", 402 .hwcg = a640_hwcg, 403 .speedbins = ADRENO_SPEEDBINS( 404 { 0, 0 }, 405 { 1, 1 }, 406 ), 407 }, { 408 .chip_ids = ADRENO_CHIP_IDS(0x06050002), 409 .family = ADRENO_6XX_GEN3, 410 .revn = 650, 411 .fw = { 412 [ADRENO_FW_SQE] = "a650_sqe.fw", 413 [ADRENO_FW_GMU] = "a650_gmu.bin", 414 }, 415 .gmem = SZ_1M + SZ_128K, 416 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 417 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 418 ADRENO_QUIRK_HAS_HW_APRIV, 419 .init = a6xx_gpu_init, 420 .zapfw = "a650_zap.mdt", 421 .hwcg = a650_hwcg, 422 .address_space_size = SZ_16G, 423 .speedbins = ADRENO_SPEEDBINS( 424 { 0, 0 }, 425 { 1, 1 }, 426 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ 427 { 3, 2 }, 428 ), 429 }, { 430 .chip_ids = ADRENO_CHIP_IDS(0x06060001), 431 .family = ADRENO_6XX_GEN4, 432 .revn = 660, 433 .fw = { 434 [ADRENO_FW_SQE] = "a660_sqe.fw", 435 [ADRENO_FW_GMU] = "a660_gmu.bin", 436 }, 437 .gmem = SZ_1M + SZ_512K, 438 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 439 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 440 ADRENO_QUIRK_HAS_HW_APRIV, 441 .init = a6xx_gpu_init, 442 .zapfw = "a660_zap.mdt", 443 .hwcg = a660_hwcg, 444 .address_space_size = SZ_16G, 445 }, { 446 .chip_ids = ADRENO_CHIP_IDS(0x06030500), 447 .family = ADRENO_6XX_GEN4, 448 .fw = { 449 [ADRENO_FW_SQE] = "a660_sqe.fw", 450 [ADRENO_FW_GMU] = "a660_gmu.bin", 451 }, 452 .gmem = SZ_512K, 453 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 454 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 455 ADRENO_QUIRK_HAS_HW_APRIV, 456 .init = a6xx_gpu_init, 457 .zapfw = "a660_zap.mbn", 458 .hwcg = a660_hwcg, 459 .address_space_size = SZ_16G, 460 .speedbins = ADRENO_SPEEDBINS( 461 { 0, 0 }, 462 { 117, 0 }, 463 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ 464 { 190, 1 }, 465 ), 466 }, { 467 .chip_ids = ADRENO_CHIP_IDS(0x06080001), 468 .family = ADRENO_6XX_GEN2, 469 .revn = 680, 470 .fw = { 471 [ADRENO_FW_SQE] = "a630_sqe.fw", 472 [ADRENO_FW_GMU] = "a640_gmu.bin", 473 }, 474 .gmem = SZ_2M, 475 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 476 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 477 .init = a6xx_gpu_init, 478 .zapfw = "a640_zap.mdt", 479 .hwcg = a640_hwcg, 480 }, { 481 .chip_ids = ADRENO_CHIP_IDS(0x06090000), 482 .family = ADRENO_6XX_GEN4, 483 .fw = { 484 [ADRENO_FW_SQE] = "a660_sqe.fw", 485 [ADRENO_FW_GMU] = "a660_gmu.bin", 486 }, 487 .gmem = SZ_4M, 488 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 489 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 490 ADRENO_QUIRK_HAS_HW_APRIV, 491 .init = a6xx_gpu_init, 492 .zapfw = "a690_zap.mdt", 493 .hwcg = a690_hwcg, 494 .address_space_size = SZ_16G, 495 }, { 496 .chip_ids = ADRENO_CHIP_IDS(0x07030001), 497 .family = ADRENO_7XX_GEN1, 498 .fw = { 499 [ADRENO_FW_SQE] = "a730_sqe.fw", 500 [ADRENO_FW_GMU] = "gmu_gen70000.bin", 501 }, 502 .gmem = SZ_2M, 503 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 504 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 505 ADRENO_QUIRK_HAS_HW_APRIV, 506 .init = a6xx_gpu_init, 507 .zapfw = "a730_zap.mdt", 508 .hwcg = a730_hwcg, 509 .address_space_size = SZ_16G, 510 }, { 511 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ 512 .family = ADRENO_7XX_GEN2, 513 .fw = { 514 [ADRENO_FW_SQE] = "a740_sqe.fw", 515 [ADRENO_FW_GMU] = "gmu_gen70200.bin", 516 }, 517 .gmem = 3 * SZ_1M, 518 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 519 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 520 ADRENO_QUIRK_HAS_HW_APRIV, 521 .init = a6xx_gpu_init, 522 .zapfw = "a740_zap.mdt", 523 .hwcg = a740_hwcg, 524 .address_space_size = SZ_16G, 525 }, 526 }; 527 528 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 529 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 530 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 531 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 532 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 533 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 534 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 535 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 536 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 537 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 538 MODULE_FIRMWARE("qcom/a530_zap.b00"); 539 MODULE_FIRMWARE("qcom/a530_zap.b01"); 540 MODULE_FIRMWARE("qcom/a530_zap.b02"); 541 MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); 542 MODULE_FIRMWARE("qcom/a619_gmu.bin"); 543 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 544 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 545 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 546 MODULE_FIRMWARE("qcom/a640_gmu.bin"); 547 MODULE_FIRMWARE("qcom/a650_gmu.bin"); 548 MODULE_FIRMWARE("qcom/a650_sqe.fw"); 549 MODULE_FIRMWARE("qcom/a660_gmu.bin"); 550 MODULE_FIRMWARE("qcom/a660_sqe.fw"); 551 MODULE_FIRMWARE("qcom/leia_pfp_470.fw"); 552 MODULE_FIRMWARE("qcom/leia_pm4_470.fw"); 553 MODULE_FIRMWARE("qcom/yamato_pfp.fw"); 554 MODULE_FIRMWARE("qcom/yamato_pm4.fw"); 555 556 static const struct adreno_info *adreno_info(uint32_t chip_id) 557 { 558 /* identify gpu: */ 559 for (int i = 0; i < ARRAY_SIZE(gpulist); i++) { 560 const struct adreno_info *info = &gpulist[i]; 561 if (info->machine && !of_machine_is_compatible(info->machine)) 562 continue; 563 for (int j = 0; info->chip_ids[j]; j++) 564 if (info->chip_ids[j] == chip_id) 565 return info; 566 } 567 568 return NULL; 569 } 570 571 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 572 { 573 struct msm_drm_private *priv = dev->dev_private; 574 struct platform_device *pdev = priv->gpu_pdev; 575 struct msm_gpu *gpu = NULL; 576 struct adreno_gpu *adreno_gpu; 577 int ret; 578 579 if (pdev) 580 gpu = dev_to_gpu(&pdev->dev); 581 582 if (!gpu) { 583 dev_err_once(dev->dev, "no GPU device was found\n"); 584 return NULL; 585 } 586 587 adreno_gpu = to_adreno_gpu(gpu); 588 589 /* 590 * The number one reason for HW init to fail is if the firmware isn't 591 * loaded yet. Try that first and don't bother continuing on 592 * otherwise 593 */ 594 595 ret = adreno_load_fw(adreno_gpu); 596 if (ret) 597 return NULL; 598 599 if (gpu->funcs->ucode_load) { 600 ret = gpu->funcs->ucode_load(gpu); 601 if (ret) 602 return NULL; 603 } 604 605 /* 606 * Now that we have firmware loaded, and are ready to begin 607 * booting the gpu, go ahead and enable runpm: 608 */ 609 pm_runtime_enable(&pdev->dev); 610 611 ret = pm_runtime_get_sync(&pdev->dev); 612 if (ret < 0) { 613 pm_runtime_put_noidle(&pdev->dev); 614 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 615 goto err_disable_rpm; 616 } 617 618 mutex_lock(&gpu->lock); 619 ret = msm_gpu_hw_init(gpu); 620 mutex_unlock(&gpu->lock); 621 if (ret) { 622 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 623 goto err_put_rpm; 624 } 625 626 pm_runtime_put_autosuspend(&pdev->dev); 627 628 #ifdef CONFIG_DEBUG_FS 629 if (gpu->funcs->debugfs_init) { 630 gpu->funcs->debugfs_init(gpu, dev->primary); 631 gpu->funcs->debugfs_init(gpu, dev->render); 632 } 633 #endif 634 635 return gpu; 636 637 err_put_rpm: 638 pm_runtime_put_sync_suspend(&pdev->dev); 639 err_disable_rpm: 640 pm_runtime_disable(&pdev->dev); 641 642 return NULL; 643 } 644 645 static int find_chipid(struct device *dev, uint32_t *chipid) 646 { 647 struct device_node *node = dev->of_node; 648 const char *compat; 649 int ret; 650 651 /* first search the compat strings for qcom,adreno-XYZ.W: */ 652 ret = of_property_read_string_index(node, "compatible", 0, &compat); 653 if (ret == 0) { 654 unsigned int r, patch; 655 656 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 657 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 658 uint32_t core, major, minor; 659 660 core = r / 100; 661 r %= 100; 662 major = r / 10; 663 r %= 10; 664 minor = r; 665 666 *chipid = (core << 24) | 667 (major << 16) | 668 (minor << 8) | 669 patch; 670 671 return 0; 672 } 673 674 if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1) 675 return 0; 676 } 677 678 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 679 ret = of_property_read_u32(node, "qcom,chipid", chipid); 680 if (ret) { 681 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 682 return ret; 683 } 684 685 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 686 687 return 0; 688 } 689 690 static int adreno_bind(struct device *dev, struct device *master, void *data) 691 { 692 static struct adreno_platform_config config = {}; 693 const struct adreno_info *info; 694 struct msm_drm_private *priv = dev_get_drvdata(master); 695 struct drm_device *drm = priv->dev; 696 struct msm_gpu *gpu; 697 int ret; 698 699 ret = find_chipid(dev, &config.chip_id); 700 if (ret) 701 return ret; 702 703 dev->platform_data = &config; 704 priv->gpu_pdev = to_platform_device(dev); 705 706 info = adreno_info(config.chip_id); 707 if (!info) { 708 dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", 709 ADRENO_CHIPID_ARGS(config.chip_id)); 710 return -ENXIO; 711 } 712 713 config.info = info; 714 715 DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id)); 716 717 priv->is_a2xx = info->family < ADRENO_3XX; 718 priv->has_cached_coherent = 719 !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); 720 721 gpu = info->init(drm); 722 if (IS_ERR(gpu)) { 723 dev_warn(drm->dev, "failed to load adreno gpu\n"); 724 return PTR_ERR(gpu); 725 } 726 727 ret = dev_pm_opp_of_find_icc_paths(dev, NULL); 728 if (ret) 729 return ret; 730 731 return 0; 732 } 733 734 static int adreno_system_suspend(struct device *dev); 735 static void adreno_unbind(struct device *dev, struct device *master, 736 void *data) 737 { 738 struct msm_drm_private *priv = dev_get_drvdata(master); 739 struct msm_gpu *gpu = dev_to_gpu(dev); 740 741 if (pm_runtime_enabled(dev)) 742 WARN_ON_ONCE(adreno_system_suspend(dev)); 743 gpu->funcs->destroy(gpu); 744 745 priv->gpu_pdev = NULL; 746 } 747 748 static const struct component_ops a3xx_ops = { 749 .bind = adreno_bind, 750 .unbind = adreno_unbind, 751 }; 752 753 static void adreno_device_register_headless(void) 754 { 755 /* on imx5, we don't have a top-level mdp/dpu node 756 * this creates a dummy node for the driver for that case 757 */ 758 struct platform_device_info dummy_info = { 759 .parent = NULL, 760 .name = "msm", 761 .id = -1, 762 .res = NULL, 763 .num_res = 0, 764 .data = NULL, 765 .size_data = 0, 766 .dma_mask = ~0, 767 }; 768 platform_device_register_full(&dummy_info); 769 } 770 771 static int adreno_probe(struct platform_device *pdev) 772 { 773 774 int ret; 775 776 ret = component_add(&pdev->dev, &a3xx_ops); 777 if (ret) 778 return ret; 779 780 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 781 adreno_device_register_headless(); 782 783 return 0; 784 } 785 786 static void adreno_remove(struct platform_device *pdev) 787 { 788 component_del(&pdev->dev, &a3xx_ops); 789 } 790 791 static void adreno_shutdown(struct platform_device *pdev) 792 { 793 WARN_ON_ONCE(adreno_system_suspend(&pdev->dev)); 794 } 795 796 static const struct of_device_id dt_match[] = { 797 { .compatible = "qcom,adreno" }, 798 { .compatible = "qcom,adreno-3xx" }, 799 /* for compatibility with imx5 gpu: */ 800 { .compatible = "amd,imageon" }, 801 /* for backwards compat w/ downstream kgsl DT files: */ 802 { .compatible = "qcom,kgsl-3d0" }, 803 {} 804 }; 805 806 static int adreno_runtime_resume(struct device *dev) 807 { 808 struct msm_gpu *gpu = dev_to_gpu(dev); 809 810 return gpu->funcs->pm_resume(gpu); 811 } 812 813 static int adreno_runtime_suspend(struct device *dev) 814 { 815 struct msm_gpu *gpu = dev_to_gpu(dev); 816 817 /* 818 * We should be holding a runpm ref, which will prevent 819 * runtime suspend. In the system suspend path, we've 820 * already waited for active jobs to complete. 821 */ 822 WARN_ON_ONCE(gpu->active_submits); 823 824 return gpu->funcs->pm_suspend(gpu); 825 } 826 827 static void suspend_scheduler(struct msm_gpu *gpu) 828 { 829 int i; 830 831 /* 832 * Shut down the scheduler before we force suspend, so that 833 * suspend isn't racing with scheduler kthread feeding us 834 * more work. 835 * 836 * Note, we just want to park the thread, and let any jobs 837 * that are already on the hw queue complete normally, as 838 * opposed to the drm_sched_stop() path used for handling 839 * faulting/timed-out jobs. We can't really cancel any jobs 840 * already on the hw queue without racing with the GPU. 841 */ 842 for (i = 0; i < gpu->nr_rings; i++) { 843 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 844 845 drm_sched_wqueue_stop(sched); 846 } 847 } 848 849 static void resume_scheduler(struct msm_gpu *gpu) 850 { 851 int i; 852 853 for (i = 0; i < gpu->nr_rings; i++) { 854 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 855 856 drm_sched_wqueue_start(sched); 857 } 858 } 859 860 static int adreno_system_suspend(struct device *dev) 861 { 862 struct msm_gpu *gpu = dev_to_gpu(dev); 863 int remaining, ret; 864 865 if (!gpu) 866 return 0; 867 868 suspend_scheduler(gpu); 869 870 remaining = wait_event_timeout(gpu->retire_event, 871 gpu->active_submits == 0, 872 msecs_to_jiffies(1000)); 873 if (remaining == 0) { 874 dev_err(dev, "Timeout waiting for GPU to suspend\n"); 875 ret = -EBUSY; 876 goto out; 877 } 878 879 ret = pm_runtime_force_suspend(dev); 880 out: 881 if (ret) 882 resume_scheduler(gpu); 883 884 return ret; 885 } 886 887 static int adreno_system_resume(struct device *dev) 888 { 889 struct msm_gpu *gpu = dev_to_gpu(dev); 890 891 if (!gpu) 892 return 0; 893 894 resume_scheduler(gpu); 895 return pm_runtime_force_resume(dev); 896 } 897 898 static const struct dev_pm_ops adreno_pm_ops = { 899 SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume) 900 RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL) 901 }; 902 903 static struct platform_driver adreno_driver = { 904 .probe = adreno_probe, 905 .remove_new = adreno_remove, 906 .shutdown = adreno_shutdown, 907 .driver = { 908 .name = "adreno", 909 .of_match_table = dt_match, 910 .pm = &adreno_pm_ops, 911 }, 912 }; 913 914 void __init adreno_register(void) 915 { 916 platform_driver_register(&adreno_driver); 917 } 918 919 void __exit adreno_unregister(void) 920 { 921 platform_driver_unregister(&adreno_driver); 922 } 923