1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 3 4 #ifndef __A6XX_GPU_H__ 5 #define __A6XX_GPU_H__ 6 7 8 #include "adreno_gpu.h" 9 #include "a6xx.xml.h" 10 11 #include "a6xx_gmu.h" 12 13 extern bool hang_debug; 14 15 /** 16 * struct a6xx_info - a6xx specific information from device table 17 * 18 * @hwcg: hw clock gating register sequence 19 * @protect: CP_PROTECT settings 20 */ 21 struct a6xx_info { 22 const struct adreno_reglist *hwcg; 23 const struct adreno_protect *protect; 24 u32 gmu_chipid; 25 }; 26 27 struct a6xx_gpu { 28 struct adreno_gpu base; 29 30 struct drm_gem_object *sqe_bo; 31 uint64_t sqe_iova; 32 33 struct msm_ringbuffer *cur_ring; 34 35 struct a6xx_gmu gmu; 36 37 struct drm_gem_object *shadow_bo; 38 uint64_t shadow_iova; 39 uint32_t *shadow; 40 41 bool has_whereami; 42 43 void __iomem *llc_mmio; 44 void *llc_slice; 45 void *htw_llc_slice; 46 bool have_mmu500; 47 bool hung; 48 }; 49 50 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 51 52 /* 53 * Given a register and a count, return a value to program into 54 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for 55 * _len + 1 registers starting at _reg. 56 */ 57 #define A6XX_PROTECT_NORDWR(_reg, _len) \ 58 ((1 << 31) | \ 59 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 60 61 /* 62 * Same as above, but allow reads over the range. For areas of mixed use (such 63 * as performance counters) this allows us to protect a much larger range with a 64 * single register 65 */ 66 #define A6XX_PROTECT_RDONLY(_reg, _len) \ 67 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 68 69 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 70 { 71 if(adreno_is_a630(gpu)) 72 return false; 73 74 return true; 75 } 76 77 static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 78 { 79 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 80 } 81 82 static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) 83 { 84 return readl(a6xx_gpu->llc_mmio + (reg << 2)); 85 } 86 87 static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 88 { 89 writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 90 } 91 92 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ 93 ((_ring)->id * sizeof(uint32_t))) 94 95 int a6xx_gmu_resume(struct a6xx_gpu *gpu); 96 int a6xx_gmu_stop(struct a6xx_gpu *gpu); 97 98 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 99 100 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 101 102 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 103 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 104 105 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 106 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 107 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 108 109 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 110 bool suspended); 111 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 112 113 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 114 struct drm_printer *p); 115 116 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 117 int a6xx_gpu_state_put(struct msm_gpu_state *state); 118 119 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off); 120 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); 121 122 #endif /* __A6XX_GPU_H__ */ 123