1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 3 4 #ifndef __A6XX_GPU_H__ 5 #define __A6XX_GPU_H__ 6 7 8 #include "adreno_gpu.h" 9 #include "a6xx.xml.h" 10 11 #include "a6xx_gmu.h" 12 13 extern bool hang_debug; 14 15 struct cpu_gpu_lock { 16 uint32_t gpu_req; 17 uint32_t cpu_req; 18 uint32_t turn; 19 union { 20 struct { 21 uint16_t list_length; 22 uint16_t list_offset; 23 }; 24 struct { 25 uint8_t ifpc_list_len; 26 uint8_t preemption_list_len; 27 uint16_t dynamic_list_len; 28 }; 29 }; 30 uint64_t regs[62]; 31 }; 32 33 /** 34 * struct a6xx_info - a6xx specific information from device table 35 * 36 * @hwcg: hw clock gating register sequence 37 * @protect: CP_PROTECT settings 38 * @pwrup_reglist pwrup reglist for preemption 39 */ 40 struct a6xx_info { 41 const struct adreno_reglist *hwcg; 42 const struct adreno_protect *protect; 43 const struct adreno_reglist_list *pwrup_reglist; 44 u32 gmu_chipid; 45 u32 gmu_cgc_mode; 46 u32 prim_fifo_threshold; 47 }; 48 49 struct a6xx_gpu { 50 struct adreno_gpu base; 51 52 struct drm_gem_object *sqe_bo; 53 uint64_t sqe_iova; 54 55 struct msm_ringbuffer *cur_ring; 56 struct msm_ringbuffer *next_ring; 57 58 struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; 59 void *preempt[MSM_GPU_MAX_RINGS]; 60 uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; 61 struct drm_gem_object *preempt_smmu_bo[MSM_GPU_MAX_RINGS]; 62 void *preempt_smmu[MSM_GPU_MAX_RINGS]; 63 uint64_t preempt_smmu_iova[MSM_GPU_MAX_RINGS]; 64 uint32_t last_seqno[MSM_GPU_MAX_RINGS]; 65 66 atomic_t preempt_state; 67 spinlock_t eval_lock; 68 struct timer_list preempt_timer; 69 70 unsigned int preempt_level; 71 bool uses_gmem; 72 bool skip_save_restore; 73 74 struct drm_gem_object *preempt_postamble_bo; 75 void *preempt_postamble_ptr; 76 uint64_t preempt_postamble_iova; 77 uint64_t preempt_postamble_len; 78 bool postamble_enabled; 79 80 struct a6xx_gmu gmu; 81 82 struct drm_gem_object *shadow_bo; 83 uint64_t shadow_iova; 84 uint32_t *shadow; 85 86 struct drm_gem_object *pwrup_reglist_bo; 87 void *pwrup_reglist_ptr; 88 uint64_t pwrup_reglist_iova; 89 bool pwrup_reglist_emitted; 90 91 bool has_whereami; 92 93 void __iomem *llc_mmio; 94 void *llc_slice; 95 void *htw_llc_slice; 96 bool have_mmu500; 97 bool hung; 98 }; 99 100 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 101 102 /* 103 * In order to do lockless preemption we use a simple state machine to progress 104 * through the process. 105 * 106 * PREEMPT_NONE - no preemption in progress. Next state START. 107 * PREEMPT_START - The trigger is evaluating if preemption is possible. Next 108 * states: TRIGGERED, NONE 109 * PREEMPT_FINISH - An intermediate state before moving back to NONE. Next 110 * state: NONE. 111 * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next 112 * states: FAULTED, PENDING 113 * PREEMPT_FAULTED: A preemption timed out (never completed). This will trigger 114 * recovery. Next state: N/A 115 * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is 116 * checking the success of the operation. Next state: FAULTED, NONE. 117 */ 118 119 enum a6xx_preempt_state { 120 PREEMPT_NONE = 0, 121 PREEMPT_START, 122 PREEMPT_FINISH, 123 PREEMPT_TRIGGERED, 124 PREEMPT_FAULTED, 125 PREEMPT_PENDING, 126 }; 127 128 /* 129 * struct a6xx_preempt_record is a shared buffer between the microcode and the 130 * CPU to store the state for preemption. The record itself is much larger 131 * (2112k) but most of that is used by the CP for storage. 132 * 133 * There is a preemption record assigned per ringbuffer. When the CPU triggers a 134 * preemption, it fills out the record with the useful information (wptr, ring 135 * base, etc) and the microcode uses that information to set up the CP following 136 * the preemption. When a ring is switched out, the CP will save the ringbuffer 137 * state back to the record. In this way, once the records are properly set up 138 * the CPU can quickly switch back and forth between ringbuffers by only 139 * updating a few registers (often only the wptr). 140 * 141 * These are the CPU aware registers in the record: 142 * @magic: Must always be 0xAE399D6EUL 143 * @info: Type of the record - written 0 by the CPU, updated by the CP 144 * @errno: preemption error record 145 * @data: Data field in YIELD and SET_MARKER packets, Written and used by CP 146 * @cntl: Value of RB_CNTL written by CPU, save/restored by CP 147 * @rptr: Value of RB_RPTR written by CPU, save/restored by CP 148 * @wptr: Value of RB_WPTR written by CPU, save/restored by CP 149 * @_pad: Reserved/padding 150 * @rptr_addr: Value of RB_RPTR_ADDR_LO|HI written by CPU, save/restored by CP 151 * @rbase: Value of RB_BASE written by CPU, save/restored by CP 152 * @counter: GPU address of the storage area for the preemption counters 153 * @bv_rptr_addr: Value of BV_RB_RPTR_ADDR_LO|HI written by CPU, save/restored by CP 154 */ 155 struct a6xx_preempt_record { 156 u32 magic; 157 u32 info; 158 u32 errno; 159 u32 data; 160 u32 cntl; 161 u32 rptr; 162 u32 wptr; 163 u32 _pad; 164 u64 rptr_addr; 165 u64 rbase; 166 u64 counter; 167 u64 bv_rptr_addr; 168 }; 169 170 #define A6XX_PREEMPT_RECORD_MAGIC 0xAE399D6EUL 171 172 #define PREEMPT_SMMU_INFO_SIZE 4096 173 174 #define PREEMPT_RECORD_SIZE(adreno_gpu) \ 175 ((adreno_gpu->info->preempt_record_size) == 0 ? \ 176 4192 * SZ_1K : (adreno_gpu->info->preempt_record_size)) 177 178 /* 179 * The preemption counter block is a storage area for the value of the 180 * preemption counters that are saved immediately before context switch. We 181 * append it on to the end of the allocation for the preemption record. 182 */ 183 #define A6XX_PREEMPT_COUNTER_SIZE (16 * 4) 184 185 struct a7xx_cp_smmu_info { 186 u32 magic; 187 u32 _pad4; 188 u64 ttbr0; 189 u32 asid; 190 u32 context_idr; 191 u32 context_bank; 192 }; 193 194 #define GEN7_CP_SMMU_INFO_MAGIC 0x241350d5UL 195 196 /* 197 * Given a register and a count, return a value to program into 198 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for 199 * _len + 1 registers starting at _reg. 200 */ 201 #define A6XX_PROTECT_NORDWR(_reg, _len) \ 202 ((1 << 31) | \ 203 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 204 205 /* 206 * Same as above, but allow reads over the range. For areas of mixed use (such 207 * as performance counters) this allows us to protect a much larger range with a 208 * single register 209 */ 210 #define A6XX_PROTECT_RDONLY(_reg, _len) \ 211 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 212 213 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 214 { 215 if(adreno_is_a630(gpu)) 216 return false; 217 218 return true; 219 } 220 221 static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 222 { 223 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 224 } 225 226 static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) 227 { 228 return readl(a6xx_gpu->llc_mmio + (reg << 2)); 229 } 230 231 static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 232 { 233 writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 234 } 235 236 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ 237 ((_ring)->id * sizeof(uint32_t))) 238 239 int a6xx_gmu_resume(struct a6xx_gpu *gpu); 240 int a6xx_gmu_stop(struct a6xx_gpu *gpu); 241 242 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 243 244 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 245 246 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 247 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 248 249 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 250 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 251 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 252 253 void a6xx_preempt_init(struct msm_gpu *gpu); 254 void a6xx_preempt_hw_init(struct msm_gpu *gpu); 255 void a6xx_preempt_trigger(struct msm_gpu *gpu); 256 void a6xx_preempt_irq(struct msm_gpu *gpu); 257 void a6xx_preempt_fini(struct msm_gpu *gpu); 258 int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu, 259 struct msm_gpu_submitqueue *queue); 260 void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu, 261 struct msm_gpu_submitqueue *queue); 262 263 /* Return true if we are in a preempt state */ 264 static inline bool a6xx_in_preempt(struct a6xx_gpu *a6xx_gpu) 265 { 266 /* 267 * Make sure the read to preempt_state is ordered with respect to reads 268 * of other variables before ... 269 */ 270 smp_rmb(); 271 272 int preempt_state = atomic_read(&a6xx_gpu->preempt_state); 273 274 /* ... and after. */ 275 smp_rmb(); 276 277 return !(preempt_state == PREEMPT_NONE || 278 preempt_state == PREEMPT_FINISH); 279 } 280 281 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 282 bool suspended); 283 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 284 285 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 286 struct drm_printer *p); 287 288 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 289 int a6xx_gpu_state_put(struct msm_gpu_state *state); 290 291 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off); 292 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); 293 294 #endif /* __A6XX_GPU_H__ */ 295