1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 3 4 #ifndef __A6XX_GPU_H__ 5 #define __A6XX_GPU_H__ 6 7 8 #include "adreno_gpu.h" 9 #include "a6xx.xml.h" 10 11 #include "a6xx_gmu.h" 12 13 extern bool hang_debug; 14 15 /** 16 * struct a6xx_info - a6xx specific information from device table 17 * 18 * @hwcg: hw clock gating register sequence 19 * @protect: CP_PROTECT settings 20 */ 21 struct a6xx_info { 22 const struct adreno_reglist *hwcg; 23 const struct adreno_protect *protect; 24 }; 25 26 struct a6xx_gpu { 27 struct adreno_gpu base; 28 29 struct drm_gem_object *sqe_bo; 30 uint64_t sqe_iova; 31 32 struct msm_ringbuffer *cur_ring; 33 34 struct a6xx_gmu gmu; 35 36 struct drm_gem_object *shadow_bo; 37 uint64_t shadow_iova; 38 uint32_t *shadow; 39 40 bool has_whereami; 41 42 void __iomem *llc_mmio; 43 void *llc_slice; 44 void *htw_llc_slice; 45 bool have_mmu500; 46 bool hung; 47 }; 48 49 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 50 51 /* 52 * Given a register and a count, return a value to program into 53 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for 54 * _len + 1 registers starting at _reg. 55 */ 56 #define A6XX_PROTECT_NORDWR(_reg, _len) \ 57 ((1 << 31) | \ 58 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 59 60 /* 61 * Same as above, but allow reads over the range. For areas of mixed use (such 62 * as performance counters) this allows us to protect a much larger range with a 63 * single register 64 */ 65 #define A6XX_PROTECT_RDONLY(_reg, _len) \ 66 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 67 68 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 69 { 70 if(adreno_is_a630(gpu)) 71 return false; 72 73 return true; 74 } 75 76 static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 77 { 78 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 79 } 80 81 static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) 82 { 83 return readl(a6xx_gpu->llc_mmio + (reg << 2)); 84 } 85 86 static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 87 { 88 writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 89 } 90 91 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ 92 ((_ring)->id * sizeof(uint32_t))) 93 94 int a6xx_gmu_resume(struct a6xx_gpu *gpu); 95 int a6xx_gmu_stop(struct a6xx_gpu *gpu); 96 97 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 98 99 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 100 101 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 102 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 103 104 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 105 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 106 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 107 108 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 109 bool suspended); 110 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 111 112 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 113 struct drm_printer *p); 114 115 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 116 int a6xx_gpu_state_put(struct msm_gpu_state *state); 117 118 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off); 119 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); 120 121 #endif /* __A6XX_GPU_H__ */ 122