1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/firmware/qcom/qcom_scm.h> 14 #include <linux/pm_domain.h> 15 #include <linux/soc/qcom/llcc-qcom.h> 16 17 #define GPU_PAS_ID 13 18 19 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 20 { 21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 23 24 /* Check that the GMU is idle */ 25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 26 return false; 27 28 /* Check tha the CX master is idle */ 29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 30 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 31 return false; 32 33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 34 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 35 } 36 37 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 38 { 39 /* wait for CP to drain ringbuffer: */ 40 if (!adreno_idle(gpu, ring)) 41 return false; 42 43 if (spin_until(_a6xx_check_idle(gpu))) { 44 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 45 gpu->name, __builtin_return_address(0), 46 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 48 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 49 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 50 return false; 51 } 52 53 return true; 54 } 55 56 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 57 { 58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 59 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 60 61 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 63 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 66 } 67 } 68 69 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 70 { 71 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 72 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 73 uint32_t wptr; 74 unsigned long flags; 75 76 update_shadow_rptr(gpu, ring); 77 78 spin_lock_irqsave(&ring->preempt_lock, flags); 79 80 /* Copy the shadow to the actual register */ 81 ring->cur = ring->next; 82 83 /* Make sure to wrap wptr if we need to */ 84 wptr = get_wptr(ring); 85 86 /* Update HW if this is the current ring and we are not in preempt*/ 87 if (!a6xx_in_preempt(a6xx_gpu)) { 88 if (a6xx_gpu->cur_ring == ring) 89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 90 else 91 ring->restore_wptr = true; 92 } else { 93 ring->restore_wptr = true; 94 } 95 96 spin_unlock_irqrestore(&ring->preempt_lock, flags); 97 } 98 99 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 100 u64 iova) 101 { 102 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 103 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 104 CP_REG_TO_MEM_0_CNT(2) | 105 CP_REG_TO_MEM_0_64B); 106 OUT_RING(ring, lower_32_bits(iova)); 107 OUT_RING(ring, upper_32_bits(iova)); 108 } 109 110 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 111 struct msm_ringbuffer *ring, struct msm_gem_submit *submit) 112 { 113 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; 114 struct msm_file_private *ctx = submit->queue->ctx; 115 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 116 phys_addr_t ttbr; 117 u32 asid; 118 u64 memptr = rbmemptr(ring, ttbr0); 119 120 if (ctx->seqno == ring->cur_ctx_seqno) 121 return; 122 123 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 124 return; 125 126 if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { 127 /* Wait for previous submit to complete before continuing: */ 128 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 129 OUT_RING(ring, 0); 130 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 131 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 132 OUT_RING(ring, submit->seqno - 1); 133 } 134 135 if (!sysprof) { 136 if (!adreno_is_a7xx(adreno_gpu)) { 137 /* Turn off protected mode to write to special registers */ 138 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 139 OUT_RING(ring, 0); 140 } 141 142 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 143 OUT_RING(ring, 1); 144 } 145 146 /* Execute the table update */ 147 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 148 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 149 150 OUT_RING(ring, 151 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 152 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 153 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 154 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 155 156 /* 157 * Write the new TTBR0 to the memstore. This is good for debugging. 158 * Needed for preemption 159 */ 160 OUT_PKT7(ring, CP_MEM_WRITE, 5); 161 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 162 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 163 OUT_RING(ring, lower_32_bits(ttbr)); 164 OUT_RING(ring, upper_32_bits(ttbr)); 165 OUT_RING(ring, ctx->seqno); 166 167 /* 168 * Sync both threads after switching pagetables and enable BR only 169 * to make sure BV doesn't race ahead while BR is still switching 170 * pagetables. 171 */ 172 if (adreno_is_a7xx(&a6xx_gpu->base)) { 173 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 174 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 175 } 176 177 /* 178 * And finally, trigger a uche flush to be sure there isn't anything 179 * lingering in that part of the GPU 180 */ 181 182 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 183 OUT_RING(ring, CACHE_INVALIDATE); 184 185 if (!sysprof) { 186 /* 187 * Wait for SRAM clear after the pgtable update, so the 188 * two can happen in parallel: 189 */ 190 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 191 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 192 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 193 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 194 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 195 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 196 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 197 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 198 199 if (!adreno_is_a7xx(adreno_gpu)) { 200 /* Re-enable protected mode: */ 201 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 202 OUT_RING(ring, 1); 203 } 204 } 205 } 206 207 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 208 { 209 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 210 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 211 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 212 struct msm_ringbuffer *ring = submit->ring; 213 unsigned int i, ibs = 0; 214 215 a6xx_set_pagetable(a6xx_gpu, ring, submit); 216 217 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 218 rbmemptr_stats(ring, index, cpcycles_start)); 219 220 /* 221 * For PM4 the GMU register offsets are calculated from the base of the 222 * GPU registers so we need to add 0x1a800 to the register value on A630 223 * to get the right value from PM4. 224 */ 225 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 226 rbmemptr_stats(ring, index, alwayson_start)); 227 228 /* Invalidate CCU depth and color */ 229 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 230 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 231 232 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 233 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 234 235 /* Submit the commands */ 236 for (i = 0; i < submit->nr_cmds; i++) { 237 switch (submit->cmd[i].type) { 238 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 239 break; 240 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 241 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 242 break; 243 fallthrough; 244 case MSM_SUBMIT_CMD_BUF: 245 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 246 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 247 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 248 OUT_RING(ring, submit->cmd[i].size); 249 ibs++; 250 break; 251 } 252 253 /* 254 * Periodically update shadow-wptr if needed, so that we 255 * can see partial progress of submits with large # of 256 * cmds.. otherwise we could needlessly stall waiting for 257 * ringbuffer state, simply due to looking at a shadow 258 * rptr value that has not been updated 259 */ 260 if ((ibs % 32) == 0) 261 update_shadow_rptr(gpu, ring); 262 } 263 264 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 265 rbmemptr_stats(ring, index, cpcycles_end)); 266 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 267 rbmemptr_stats(ring, index, alwayson_end)); 268 269 /* Write the fence to the scratch register */ 270 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 271 OUT_RING(ring, submit->seqno); 272 273 /* 274 * Execute a CACHE_FLUSH_TS event. This will ensure that the 275 * timestamp is written to the memory and then triggers the interrupt 276 */ 277 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 278 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 279 CP_EVENT_WRITE_0_IRQ); 280 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 281 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 282 OUT_RING(ring, submit->seqno); 283 284 trace_msm_gpu_submit_flush(submit, 285 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 286 287 a6xx_flush(gpu, ring); 288 } 289 290 static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, 291 struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) 292 { 293 u64 preempt_postamble; 294 295 OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); 296 297 OUT_RING(ring, SMMU_INFO); 298 /* don't save SMMU, we write the record from the kernel instead */ 299 OUT_RING(ring, 0); 300 OUT_RING(ring, 0); 301 302 /* privileged and non secure buffer save */ 303 OUT_RING(ring, NON_SECURE_SAVE_ADDR); 304 OUT_RING(ring, lower_32_bits( 305 a6xx_gpu->preempt_iova[ring->id])); 306 OUT_RING(ring, upper_32_bits( 307 a6xx_gpu->preempt_iova[ring->id])); 308 309 /* user context buffer save, seems to be unnused by fw */ 310 OUT_RING(ring, NON_PRIV_SAVE_ADDR); 311 OUT_RING(ring, 0); 312 OUT_RING(ring, 0); 313 314 OUT_RING(ring, COUNTER); 315 /* seems OK to set to 0 to disable it */ 316 OUT_RING(ring, 0); 317 OUT_RING(ring, 0); 318 319 /* Emit postamble to clear perfcounters */ 320 preempt_postamble = a6xx_gpu->preempt_postamble_iova; 321 322 OUT_PKT7(ring, CP_SET_AMBLE, 3); 323 OUT_RING(ring, lower_32_bits(preempt_postamble)); 324 OUT_RING(ring, upper_32_bits(preempt_postamble)); 325 OUT_RING(ring, CP_SET_AMBLE_2_DWORDS( 326 a6xx_gpu->preempt_postamble_len) | 327 CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE)); 328 } 329 330 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 331 { 332 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 333 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 334 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 335 struct msm_ringbuffer *ring = submit->ring; 336 unsigned int i, ibs = 0; 337 338 /* 339 * Toggle concurrent binning for pagetable switch and set the thread to 340 * BR since only it can execute the pagetable switch packets. 341 */ 342 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 343 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 344 345 a6xx_set_pagetable(a6xx_gpu, ring, submit); 346 347 /* 348 * If preemption is enabled, then set the pseudo register for the save 349 * sequence 350 */ 351 if (gpu->nr_rings > 1) 352 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); 353 354 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 355 rbmemptr_stats(ring, index, cpcycles_start)); 356 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 357 rbmemptr_stats(ring, index, alwayson_start)); 358 359 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 360 OUT_RING(ring, CP_SET_THREAD_BOTH); 361 362 OUT_PKT7(ring, CP_SET_MARKER, 1); 363 OUT_RING(ring, 0x101); /* IFPC disable */ 364 365 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 366 OUT_PKT7(ring, CP_SET_MARKER, 1); 367 OUT_RING(ring, 0x00d); /* IB1LIST start */ 368 } 369 370 /* Submit the commands */ 371 for (i = 0; i < submit->nr_cmds; i++) { 372 switch (submit->cmd[i].type) { 373 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 374 break; 375 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 376 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 377 break; 378 fallthrough; 379 case MSM_SUBMIT_CMD_BUF: 380 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 381 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 382 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 383 OUT_RING(ring, submit->cmd[i].size); 384 ibs++; 385 break; 386 } 387 388 /* 389 * Periodically update shadow-wptr if needed, so that we 390 * can see partial progress of submits with large # of 391 * cmds.. otherwise we could needlessly stall waiting for 392 * ringbuffer state, simply due to looking at a shadow 393 * rptr value that has not been updated 394 */ 395 if ((ibs % 32) == 0) 396 update_shadow_rptr(gpu, ring); 397 } 398 399 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 400 OUT_PKT7(ring, CP_SET_MARKER, 1); 401 OUT_RING(ring, 0x00e); /* IB1LIST end */ 402 } 403 404 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 405 rbmemptr_stats(ring, index, cpcycles_end)); 406 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 407 rbmemptr_stats(ring, index, alwayson_end)); 408 409 /* Write the fence to the scratch register */ 410 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 411 OUT_RING(ring, submit->seqno); 412 413 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 414 OUT_RING(ring, CP_SET_THREAD_BR); 415 416 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 417 OUT_RING(ring, CCU_INVALIDATE_DEPTH); 418 419 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 420 OUT_RING(ring, CCU_INVALIDATE_COLOR); 421 422 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 423 OUT_RING(ring, CP_SET_THREAD_BV); 424 425 /* 426 * Make sure the timestamp is committed once BV pipe is 427 * completely done with this submission. 428 */ 429 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 430 OUT_RING(ring, CACHE_CLEAN | BIT(27)); 431 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 432 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 433 OUT_RING(ring, submit->seqno); 434 435 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 436 OUT_RING(ring, CP_SET_THREAD_BR); 437 438 /* 439 * This makes sure that BR doesn't race ahead and commit 440 * timestamp to memstore while BV is still processing 441 * this submission. 442 */ 443 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 444 OUT_RING(ring, 0); 445 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 446 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 447 OUT_RING(ring, submit->seqno); 448 449 a6xx_gpu->last_seqno[ring->id] = submit->seqno; 450 451 /* write the ringbuffer timestamp */ 452 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 453 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); 454 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 455 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 456 OUT_RING(ring, submit->seqno); 457 458 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 459 OUT_RING(ring, CP_SET_THREAD_BOTH); 460 461 OUT_PKT7(ring, CP_SET_MARKER, 1); 462 OUT_RING(ring, 0x100); /* IFPC enable */ 463 464 /* If preemption is enabled */ 465 if (gpu->nr_rings > 1) { 466 /* Yield the floor on command completion */ 467 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 468 469 /* 470 * If dword[2:1] are non zero, they specify an address for 471 * the CP to write the value of dword[3] to on preemption 472 * complete. Write 0 to skip the write 473 */ 474 OUT_RING(ring, 0x00); 475 OUT_RING(ring, 0x00); 476 /* Data value - not used if the address above is 0 */ 477 OUT_RING(ring, 0x01); 478 /* generate interrupt on preemption completion */ 479 OUT_RING(ring, 0x00); 480 } 481 482 483 trace_msm_gpu_submit_flush(submit, 484 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 485 486 a6xx_flush(gpu, ring); 487 488 /* Check to see if we need to start preemption */ 489 a6xx_preempt_trigger(gpu); 490 } 491 492 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 493 { 494 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 495 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 496 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 497 const struct adreno_reglist *reg; 498 unsigned int i; 499 u32 cgc_delay, cgc_hyst; 500 u32 val, clock_cntl_on; 501 502 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 503 return; 504 505 if (adreno_is_a630(adreno_gpu)) 506 clock_cntl_on = 0x8aa8aa02; 507 else if (adreno_is_a610(adreno_gpu)) 508 clock_cntl_on = 0xaaa8aa82; 509 else if (adreno_is_a702(adreno_gpu)) 510 clock_cntl_on = 0xaaaaaa82; 511 else 512 clock_cntl_on = 0x8aa8aa82; 513 514 cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; 515 cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; 516 517 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 518 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 519 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 520 state ? cgc_delay : 0); 521 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 522 state ? cgc_hyst : 0); 523 524 if (!adreno_gpu->info->a6xx->hwcg) { 525 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 526 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); 527 528 if (state) { 529 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); 530 531 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, 532 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 533 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 534 return; 535 } 536 537 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 538 } 539 540 return; 541 } 542 543 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 544 545 /* Don't re-program the registers if they are already correct */ 546 if ((!state && !val) || (state && (val == clock_cntl_on))) 547 return; 548 549 /* Disable SP clock before programming HWCG registers */ 550 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 551 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 552 553 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) 554 gpu_write(gpu, reg->offset, state ? reg->value : 0); 555 556 /* Enable SP clock */ 557 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 558 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 559 560 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 561 } 562 563 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 564 { 565 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 566 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 567 unsigned i; 568 569 /* 570 * Enable access protection to privileged registers, fault on an access 571 * protect violation and select the last span to protect from the start 572 * address all the way to the end of the register address space 573 */ 574 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 575 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | 576 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | 577 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); 578 579 for (i = 0; i < protect->count - 1; i++) { 580 /* Intentionally skip writing to some registers */ 581 if (protect->regs[i]) 582 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); 583 } 584 /* last CP_PROTECT to have "infinite" length on the last entry */ 585 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); 586 } 587 588 static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 589 { 590 gpu->ubwc_config.rgb565_predicator = 0; 591 gpu->ubwc_config.uavflagprd_inv = 0; 592 gpu->ubwc_config.min_acc_len = 0; 593 gpu->ubwc_config.ubwc_swizzle = 0x6; 594 gpu->ubwc_config.macrotile_mode = 0; 595 gpu->ubwc_config.highest_bank_bit = 15; 596 597 if (adreno_is_a610(gpu)) { 598 gpu->ubwc_config.highest_bank_bit = 13; 599 gpu->ubwc_config.min_acc_len = 1; 600 gpu->ubwc_config.ubwc_swizzle = 0x7; 601 } 602 603 if (adreno_is_a618(gpu)) 604 gpu->ubwc_config.highest_bank_bit = 14; 605 606 if (adreno_is_a619(gpu)) 607 /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ 608 gpu->ubwc_config.highest_bank_bit = 13; 609 610 if (adreno_is_a619_holi(gpu)) 611 gpu->ubwc_config.highest_bank_bit = 13; 612 613 if (adreno_is_a621(gpu)) { 614 gpu->ubwc_config.highest_bank_bit = 13; 615 gpu->ubwc_config.amsbc = 1; 616 gpu->ubwc_config.uavflagprd_inv = 2; 617 } 618 619 if (adreno_is_a640_family(gpu)) 620 gpu->ubwc_config.amsbc = 1; 621 622 if (adreno_is_a680(gpu)) 623 gpu->ubwc_config.macrotile_mode = 1; 624 625 if (adreno_is_a650(gpu) || 626 adreno_is_a660(gpu) || 627 adreno_is_a690(gpu) || 628 adreno_is_a730(gpu) || 629 adreno_is_a740_family(gpu)) { 630 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 631 gpu->ubwc_config.highest_bank_bit = 16; 632 gpu->ubwc_config.amsbc = 1; 633 gpu->ubwc_config.rgb565_predicator = 1; 634 gpu->ubwc_config.uavflagprd_inv = 2; 635 gpu->ubwc_config.macrotile_mode = 1; 636 } 637 638 if (adreno_is_7c3(gpu)) { 639 gpu->ubwc_config.highest_bank_bit = 14; 640 gpu->ubwc_config.amsbc = 1; 641 gpu->ubwc_config.rgb565_predicator = 1; 642 gpu->ubwc_config.uavflagprd_inv = 2; 643 gpu->ubwc_config.macrotile_mode = 1; 644 } 645 646 if (adreno_is_a702(gpu)) { 647 gpu->ubwc_config.highest_bank_bit = 14; 648 gpu->ubwc_config.min_acc_len = 1; 649 } 650 } 651 652 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 653 { 654 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 655 /* 656 * We subtract 13 from the highest bank bit (13 is the minimum value 657 * allowed by hw) and write the lowest two bits of the remaining value 658 * as hbb_lo and the one above it as hbb_hi to the hardware. 659 */ 660 BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); 661 u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; 662 u32 hbb_hi = hbb >> 2; 663 u32 hbb_lo = hbb & 3; 664 u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; 665 u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); 666 667 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 668 level2_swizzling_dis << 12 | 669 adreno_gpu->ubwc_config.rgb565_predicator << 11 | 670 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | 671 adreno_gpu->ubwc_config.min_acc_len << 3 | 672 hbb_lo << 1 | ubwc_mode); 673 674 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 675 level2_swizzling_dis << 6 | hbb_hi << 4 | 676 adreno_gpu->ubwc_config.min_acc_len << 3 | 677 hbb_lo << 1 | ubwc_mode); 678 679 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 680 level2_swizzling_dis << 12 | hbb_hi << 10 | 681 adreno_gpu->ubwc_config.uavflagprd_inv << 4 | 682 adreno_gpu->ubwc_config.min_acc_len << 3 | 683 hbb_lo << 1 | ubwc_mode); 684 685 if (adreno_is_a7xx(adreno_gpu)) 686 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 687 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 688 689 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 690 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); 691 692 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 693 adreno_gpu->ubwc_config.macrotile_mode); 694 } 695 696 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 697 { 698 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 699 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 700 const struct adreno_reglist_list *reglist; 701 void *ptr = a6xx_gpu->pwrup_reglist_ptr; 702 struct cpu_gpu_lock *lock = ptr; 703 u32 *dest = (u32 *)&lock->regs[0]; 704 int i; 705 706 reglist = adreno_gpu->info->a6xx->pwrup_reglist; 707 708 lock->gpu_req = lock->cpu_req = lock->turn = 0; 709 lock->ifpc_list_len = 0; 710 lock->preemption_list_len = reglist->count; 711 712 /* 713 * For each entry in each of the lists, write the offset and the current 714 * register value into the GPU buffer 715 */ 716 for (i = 0; i < reglist->count; i++) { 717 *dest++ = reglist->regs[i]; 718 *dest++ = gpu_read(gpu, reglist->regs[i]); 719 } 720 721 /* 722 * The overall register list is composed of 723 * 1. Static IFPC-only registers 724 * 2. Static IFPC + preemption registers 725 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) 726 * 727 * The first two lists are static. Size of these lists are stored as 728 * number of pairs in ifpc_list_len and preemption_list_len 729 * respectively. With concurrent binning, Some of the perfcounter 730 * registers being virtualized, CP needs to know the pipe id to program 731 * the aperture inorder to restore the same. Thus, third list is a 732 * dynamic list with triplets as 733 * (<aperture, shifted 12 bits> <address> <data>), and the length is 734 * stored as number for triplets in dynamic_list_len. 735 */ 736 lock->dynamic_list_len = 0; 737 } 738 739 static int a7xx_preempt_start(struct msm_gpu *gpu) 740 { 741 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 742 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 743 struct msm_ringbuffer *ring = gpu->rb[0]; 744 745 if (gpu->nr_rings <= 1) 746 return 0; 747 748 /* Turn CP protection off */ 749 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 750 OUT_RING(ring, 0); 751 752 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); 753 754 /* Yield the floor on command completion */ 755 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 756 OUT_RING(ring, 0x00); 757 OUT_RING(ring, 0x00); 758 OUT_RING(ring, 0x00); 759 /* Generate interrupt on preemption completion */ 760 OUT_RING(ring, 0x00); 761 762 a6xx_flush(gpu, ring); 763 764 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 765 } 766 767 static int a6xx_cp_init(struct msm_gpu *gpu) 768 { 769 struct msm_ringbuffer *ring = gpu->rb[0]; 770 771 OUT_PKT7(ring, CP_ME_INIT, 8); 772 773 OUT_RING(ring, 0x0000002f); 774 775 /* Enable multiple hardware contexts */ 776 OUT_RING(ring, 0x00000003); 777 778 /* Enable error detection */ 779 OUT_RING(ring, 0x20000000); 780 781 /* Don't enable header dump */ 782 OUT_RING(ring, 0x00000000); 783 OUT_RING(ring, 0x00000000); 784 785 /* No workarounds enabled */ 786 OUT_RING(ring, 0x00000000); 787 788 /* Pad rest of the cmds with 0's */ 789 OUT_RING(ring, 0x00000000); 790 OUT_RING(ring, 0x00000000); 791 792 a6xx_flush(gpu, ring); 793 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 794 } 795 796 static int a7xx_cp_init(struct msm_gpu *gpu) 797 { 798 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 799 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 800 struct msm_ringbuffer *ring = gpu->rb[0]; 801 u32 mask; 802 803 /* Disable concurrent binning before sending CP init */ 804 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 805 OUT_RING(ring, BIT(27)); 806 807 OUT_PKT7(ring, CP_ME_INIT, 7); 808 809 /* Use multiple HW contexts */ 810 mask = BIT(0); 811 812 /* Enable error detection */ 813 mask |= BIT(1); 814 815 /* Set default reset state */ 816 mask |= BIT(3); 817 818 /* Disable save/restore of performance counters across preemption */ 819 mask |= BIT(6); 820 821 /* Enable the register init list with the spinlock */ 822 mask |= BIT(8); 823 824 OUT_RING(ring, mask); 825 826 /* Enable multiple hardware contexts */ 827 OUT_RING(ring, 0x00000003); 828 829 /* Enable error detection */ 830 OUT_RING(ring, 0x20000000); 831 832 /* Operation mode mask */ 833 OUT_RING(ring, 0x00000002); 834 835 /* *Don't* send a power up reg list for concurrent binning (TODO) */ 836 /* Lo address */ 837 OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); 838 /* Hi address */ 839 OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); 840 /* BIT(31) set => read the regs from the list */ 841 OUT_RING(ring, BIT(31)); 842 843 a6xx_flush(gpu, ring); 844 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 845 } 846 847 /* 848 * Check that the microcode version is new enough to include several key 849 * security fixes. Return true if the ucode is safe. 850 */ 851 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 852 struct drm_gem_object *obj) 853 { 854 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 855 struct msm_gpu *gpu = &adreno_gpu->base; 856 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 857 u32 *buf = msm_gem_get_vaddr(obj); 858 bool ret = false; 859 860 if (IS_ERR(buf)) 861 return false; 862 863 /* A7xx is safe! */ 864 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) 865 return true; 866 867 /* 868 * Targets up to a640 (a618, a630 and a640) need to check for a 869 * microcode version that is patched to support the whereami opcode or 870 * one that is new enough to include it by default. 871 * 872 * a650 tier targets don't need whereami but still need to be 873 * equal to or newer than 0.95 for other security fixes 874 * 875 * a660 targets have all the critical security fixes from the start 876 */ 877 if (!strcmp(sqe_name, "a630_sqe.fw")) { 878 /* 879 * If the lowest nibble is 0xa that is an indication that this 880 * microcode has been patched. The actual version is in dword 881 * [3] but we only care about the patchlevel which is the lowest 882 * nibble of dword [3] 883 * 884 * Otherwise check that the firmware is greater than or equal 885 * to 1.90 which was the first version that had this fix built 886 * in 887 */ 888 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 889 (buf[0] & 0xfff) >= 0x190) { 890 a6xx_gpu->has_whereami = true; 891 ret = true; 892 goto out; 893 } 894 895 DRM_DEV_ERROR(&gpu->pdev->dev, 896 "a630 SQE ucode is too old. Have version %x need at least %x\n", 897 buf[0] & 0xfff, 0x190); 898 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 899 if ((buf[0] & 0xfff) >= 0x095) { 900 ret = true; 901 goto out; 902 } 903 904 DRM_DEV_ERROR(&gpu->pdev->dev, 905 "a650 SQE ucode is too old. Have version %x need at least %x\n", 906 buf[0] & 0xfff, 0x095); 907 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 908 ret = true; 909 } else { 910 DRM_DEV_ERROR(&gpu->pdev->dev, 911 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 912 } 913 out: 914 msm_gem_put_vaddr(obj); 915 return ret; 916 } 917 918 static int a6xx_ucode_load(struct msm_gpu *gpu) 919 { 920 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 921 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 922 923 if (!a6xx_gpu->sqe_bo) { 924 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 925 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 926 927 if (IS_ERR(a6xx_gpu->sqe_bo)) { 928 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 929 930 a6xx_gpu->sqe_bo = NULL; 931 DRM_DEV_ERROR(&gpu->pdev->dev, 932 "Could not allocate SQE ucode: %d\n", ret); 933 934 return ret; 935 } 936 937 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 938 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 939 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 940 drm_gem_object_put(a6xx_gpu->sqe_bo); 941 942 a6xx_gpu->sqe_bo = NULL; 943 return -EPERM; 944 } 945 } 946 947 /* 948 * Expanded APRIV and targets that support WHERE_AM_I both need a 949 * privileged buffer to store the RPTR shadow 950 */ 951 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 952 !a6xx_gpu->shadow_bo) { 953 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 954 sizeof(u32) * gpu->nr_rings, 955 MSM_BO_WC | MSM_BO_MAP_PRIV, 956 gpu->aspace, &a6xx_gpu->shadow_bo, 957 &a6xx_gpu->shadow_iova); 958 959 if (IS_ERR(a6xx_gpu->shadow)) 960 return PTR_ERR(a6xx_gpu->shadow); 961 962 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 963 } 964 965 a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, 966 MSM_BO_WC | MSM_BO_MAP_PRIV, 967 gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, 968 &a6xx_gpu->pwrup_reglist_iova); 969 970 if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) 971 return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); 972 973 msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); 974 975 return 0; 976 } 977 978 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 979 { 980 static bool loaded; 981 int ret; 982 983 if (loaded) 984 return 0; 985 986 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 987 988 loaded = !ret; 989 return ret; 990 } 991 992 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 993 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 994 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 995 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 996 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 997 A6XX_RBBM_INT_0_MASK_CP_RB | \ 998 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 999 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1000 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1001 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1002 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 1003 1004 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1005 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1006 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 1007 A6XX_RBBM_INT_0_MASK_CP_SW | \ 1008 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1009 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 1010 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 1011 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1012 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1013 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1014 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1015 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 1016 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 1017 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1018 1019 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ 1020 A6XX_CP_APRIV_CNTL_RBFETCH | \ 1021 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \ 1022 A6XX_CP_APRIV_CNTL_RBRPWB) 1023 1024 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \ 1025 A6XX_CP_APRIV_CNTL_CDREAD | \ 1026 A6XX_CP_APRIV_CNTL_CDWRITE) 1027 1028 static int hw_init(struct msm_gpu *gpu) 1029 { 1030 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1031 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1032 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1033 u64 gmem_range_min; 1034 unsigned int i; 1035 int ret; 1036 1037 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1038 /* Make sure the GMU keeps the GPU on while we set it up */ 1039 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1040 if (ret) 1041 return ret; 1042 } 1043 1044 /* Clear GBIF halt in case GX domain was not collapsed */ 1045 if (adreno_is_a619_holi(adreno_gpu)) { 1046 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1047 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1048 1049 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 1050 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); 1051 } else if (a6xx_has_gbif(adreno_gpu)) { 1052 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1053 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1054 1055 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 1056 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); 1057 } 1058 1059 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 1060 1061 if (adreno_is_a619_holi(adreno_gpu)) 1062 a6xx_sptprac_enable(gmu); 1063 1064 /* 1065 * Disable the trusted memory range - we don't actually supported secure 1066 * memory rendering at this point in time and we don't want to block off 1067 * part of the virtual memory space. 1068 */ 1069 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 1070 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 1071 1072 if (!adreno_is_a7xx(adreno_gpu)) { 1073 /* Turn on 64 bit addressing for all blocks */ 1074 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 1075 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 1076 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 1077 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 1078 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 1079 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 1080 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 1081 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 1082 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 1083 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 1084 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 1085 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 1086 } 1087 1088 /* enable hardware clockgating */ 1089 a6xx_set_hwcg(gpu, true); 1090 1091 /* VBIF/GBIF start*/ 1092 if (adreno_is_a610_family(adreno_gpu) || 1093 adreno_is_a640_family(adreno_gpu) || 1094 adreno_is_a650_family(adreno_gpu) || 1095 adreno_is_a7xx(adreno_gpu)) { 1096 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 1097 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 1098 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 1099 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 1100 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 1101 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); 1102 } else { 1103 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 1104 } 1105 1106 if (adreno_is_a630(adreno_gpu)) 1107 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 1108 1109 if (adreno_is_a7xx(adreno_gpu)) 1110 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); 1111 1112 /* Make all blocks contribute to the GPU BUSY perf counter */ 1113 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 1114 1115 /* Disable L2 bypass in the UCHE */ 1116 if (adreno_is_a7xx(adreno_gpu)) { 1117 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 1118 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 1119 } else { 1120 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); 1121 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 1122 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 1123 } 1124 1125 if (!(adreno_is_a650_family(adreno_gpu) || 1126 adreno_is_a702(adreno_gpu) || 1127 adreno_is_a730(adreno_gpu))) { 1128 gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; 1129 1130 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 1131 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); 1132 1133 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 1134 gmem_range_min + adreno_gpu->info->gmem - 1); 1135 } 1136 1137 if (adreno_is_a7xx(adreno_gpu)) 1138 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); 1139 else { 1140 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 1141 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 1142 } 1143 1144 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 1145 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1146 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1147 } else if (adreno_is_a610_family(adreno_gpu)) { 1148 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 1149 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 1150 } else if (!adreno_is_a7xx(adreno_gpu)) { 1151 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 1152 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1153 } 1154 1155 if (adreno_is_a660_family(adreno_gpu)) 1156 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1157 1158 /* Setting the mem pool size */ 1159 if (adreno_is_a610(adreno_gpu)) { 1160 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 1161 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 1162 } else if (adreno_is_a702(adreno_gpu)) { 1163 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); 1164 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); 1165 } else if (!adreno_is_a7xx(adreno_gpu)) 1166 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 1167 1168 1169 /* Set the default primFifo threshold values */ 1170 if (adreno_gpu->info->a6xx->prim_fifo_threshold) 1171 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 1172 adreno_gpu->info->a6xx->prim_fifo_threshold); 1173 1174 /* Set the AHB default slave response to "ERROR" */ 1175 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1176 1177 /* Turn on performance counters */ 1178 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1179 1180 if (adreno_is_a7xx(adreno_gpu)) { 1181 /* Turn on the IFPC counter (countable 4 on XOCLK4) */ 1182 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1183 FIELD_PREP(GENMASK(7, 0), 0x4)); 1184 } 1185 1186 /* Select CP0 to always count cycles */ 1187 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1188 1189 a6xx_set_ubwc_config(gpu); 1190 1191 /* Enable fault detection */ 1192 if (adreno_is_a730(adreno_gpu) || 1193 adreno_is_a740_family(adreno_gpu)) 1194 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); 1195 else if (adreno_is_a690(adreno_gpu)) 1196 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); 1197 else if (adreno_is_a619(adreno_gpu)) 1198 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1199 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 1200 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1201 else 1202 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1203 1204 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1205 1206 /* Set weights for bicubic filtering */ 1207 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1208 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1209 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1210 0x3fe05ff4); 1211 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1212 0x3fa0ebee); 1213 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1214 0x3f5193ed); 1215 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1216 0x3f0243f0); 1217 } 1218 1219 /* Set up the CX GMU counter 0 to count busy ticks */ 1220 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1221 1222 /* Enable the power counter */ 1223 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1224 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1225 1226 /* Protect registers from the CP */ 1227 a6xx_set_cp_protect(gpu); 1228 1229 if (adreno_is_a660_family(adreno_gpu)) { 1230 if (adreno_is_a690(adreno_gpu)) 1231 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); 1232 else 1233 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1234 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1235 } else if (adreno_is_a702(adreno_gpu)) { 1236 /* Something to do with the HLSQ cluster */ 1237 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); 1238 } 1239 1240 if (adreno_is_a690(adreno_gpu)) 1241 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); 1242 /* Set dualQ + disable afull for A660 GPU */ 1243 else if (adreno_is_a660(adreno_gpu)) 1244 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1245 else if (adreno_is_a7xx(adreno_gpu)) 1246 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 1247 FIELD_PREP(GENMASK(19, 16), 6) | 1248 FIELD_PREP(GENMASK(15, 12), 6) | 1249 FIELD_PREP(GENMASK(11, 8), 9) | 1250 BIT(3) | BIT(2) | 1251 FIELD_PREP(GENMASK(1, 0), 2)); 1252 1253 /* Enable expanded apriv for targets that support it */ 1254 if (gpu->hw_apriv) { 1255 if (adreno_is_a7xx(adreno_gpu)) { 1256 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1257 A7XX_BR_APRIVMASK); 1258 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, 1259 A7XX_APRIV_MASK); 1260 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, 1261 A7XX_APRIV_MASK); 1262 } else 1263 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1264 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); 1265 } 1266 1267 if (adreno_is_a750(adreno_gpu)) { 1268 /* Disable ubwc merged UFC request feature */ 1269 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); 1270 1271 /* Enable TP flaghint and other performance settings */ 1272 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); 1273 } else if (adreno_is_a7xx(adreno_gpu)) { 1274 /* Disable non-ubwc read reqs from passing write reqs */ 1275 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); 1276 } 1277 1278 /* Enable interrupts */ 1279 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 1280 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); 1281 1282 ret = adreno_hw_init(gpu); 1283 if (ret) 1284 goto out; 1285 1286 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1287 1288 /* Set the ringbuffer address */ 1289 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1290 1291 /* Targets that support extended APRIV can use the RPTR shadow from 1292 * hardware but all the other ones need to disable the feature. Targets 1293 * that support the WHERE_AM_I opcode can use that instead 1294 */ 1295 if (adreno_gpu->base.hw_apriv) 1296 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1297 else 1298 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1299 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1300 1301 /* Configure the RPTR shadow if needed: */ 1302 if (a6xx_gpu->shadow_bo) { 1303 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1304 shadowptr(a6xx_gpu, gpu->rb[0])); 1305 for (unsigned int i = 0; i < gpu->nr_rings; i++) 1306 a6xx_gpu->shadow[i] = 0; 1307 } 1308 1309 /* ..which means "always" on A7xx, also for BV shadow */ 1310 if (adreno_is_a7xx(adreno_gpu)) { 1311 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, 1312 rbmemptr(gpu->rb[0], bv_rptr)); 1313 } 1314 1315 a6xx_preempt_hw_init(gpu); 1316 1317 /* Always come up on rb 0 */ 1318 a6xx_gpu->cur_ring = gpu->rb[0]; 1319 1320 for (i = 0; i < gpu->nr_rings; i++) 1321 gpu->rb[i]->cur_ctx_seqno = 0; 1322 1323 /* Enable the SQE_to start the CP engine */ 1324 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1325 1326 if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { 1327 a7xx_patch_pwrup_reglist(gpu); 1328 a6xx_gpu->pwrup_reglist_emitted = true; 1329 } 1330 1331 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); 1332 if (ret) 1333 goto out; 1334 1335 /* 1336 * Try to load a zap shader into the secure world. If successful 1337 * we can use the CP to switch out of secure mode. If not then we 1338 * have no resource but to try to switch ourselves out manually. If we 1339 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1340 * be blocked and a permissions violation will soon follow. 1341 */ 1342 ret = a6xx_zap_shader_init(gpu); 1343 if (!ret) { 1344 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1345 OUT_RING(gpu->rb[0], 0x00000000); 1346 1347 a6xx_flush(gpu, gpu->rb[0]); 1348 if (!a6xx_idle(gpu, gpu->rb[0])) 1349 return -EINVAL; 1350 } else if (ret == -ENODEV) { 1351 /* 1352 * This device does not use zap shader (but print a warning 1353 * just in case someone got their dt wrong.. hopefully they 1354 * have a debug UART to realize the error of their ways... 1355 * if you mess this up you are about to crash horribly) 1356 */ 1357 dev_warn_once(gpu->dev->dev, 1358 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1359 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1360 ret = 0; 1361 } else { 1362 return ret; 1363 } 1364 1365 out: 1366 if (adreno_has_gmu_wrapper(adreno_gpu)) 1367 return ret; 1368 1369 /* Last step - yield the ringbuffer */ 1370 a7xx_preempt_start(gpu); 1371 1372 /* 1373 * Tell the GMU that we are done touching the GPU and it can start power 1374 * management 1375 */ 1376 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1377 1378 if (a6xx_gpu->gmu.legacy) { 1379 /* Take the GMU out of its special boot mode */ 1380 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1381 } 1382 1383 return ret; 1384 } 1385 1386 static int a6xx_hw_init(struct msm_gpu *gpu) 1387 { 1388 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1389 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1390 int ret; 1391 1392 mutex_lock(&a6xx_gpu->gmu.lock); 1393 ret = hw_init(gpu); 1394 mutex_unlock(&a6xx_gpu->gmu.lock); 1395 1396 return ret; 1397 } 1398 1399 static void a6xx_dump(struct msm_gpu *gpu) 1400 { 1401 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1402 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1403 adreno_dump(gpu); 1404 } 1405 1406 static void a6xx_recover(struct msm_gpu *gpu) 1407 { 1408 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1409 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1410 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1411 int i, active_submits; 1412 1413 adreno_dump_info(gpu); 1414 1415 for (i = 0; i < 8; i++) 1416 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1417 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1418 1419 if (hang_debug) 1420 a6xx_dump(gpu); 1421 1422 /* 1423 * To handle recovery specific sequences during the rpm suspend we are 1424 * about to trigger 1425 */ 1426 a6xx_gpu->hung = true; 1427 1428 /* Halt SQE first */ 1429 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1430 1431 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1432 1433 /* active_submit won't change until we make a submission */ 1434 mutex_lock(&gpu->active_lock); 1435 active_submits = gpu->active_submits; 1436 1437 /* 1438 * Temporarily clear active_submits count to silence a WARN() in the 1439 * runtime suspend cb 1440 */ 1441 gpu->active_submits = 0; 1442 1443 if (adreno_has_gmu_wrapper(adreno_gpu)) { 1444 /* Drain the outstanding traffic on memory buses */ 1445 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1446 1447 /* Reset the GPU to a clean state */ 1448 a6xx_gpu_sw_reset(gpu, true); 1449 a6xx_gpu_sw_reset(gpu, false); 1450 } 1451 1452 reinit_completion(&gmu->pd_gate); 1453 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1454 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1455 1456 /* Drop the rpm refcount from active submits */ 1457 if (active_submits) 1458 pm_runtime_put(&gpu->pdev->dev); 1459 1460 /* And the final one from recover worker */ 1461 pm_runtime_put_sync(&gpu->pdev->dev); 1462 1463 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1464 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1465 1466 dev_pm_genpd_remove_notifier(gmu->cxpd); 1467 1468 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1469 1470 if (active_submits) 1471 pm_runtime_get(&gpu->pdev->dev); 1472 1473 pm_runtime_get_sync(&gpu->pdev->dev); 1474 1475 gpu->active_submits = active_submits; 1476 mutex_unlock(&gpu->active_lock); 1477 1478 msm_gpu_hw_init(gpu); 1479 a6xx_gpu->hung = false; 1480 } 1481 1482 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1483 { 1484 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1485 static const char *uche_clients[7] = { 1486 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1487 }; 1488 u32 val; 1489 1490 if (adreno_is_a7xx(adreno_gpu)) { 1491 if (mid != 1 && mid != 2 && mid != 3 && mid != 8) 1492 return "UNKNOWN"; 1493 } else { 1494 if (mid < 1 || mid > 3) 1495 return "UNKNOWN"; 1496 } 1497 1498 /* 1499 * The source of the data depends on the mid ID read from FSYNR1. 1500 * and the client ID read from the UCHE block 1501 */ 1502 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1503 1504 if (adreno_is_a7xx(adreno_gpu)) { 1505 /* Bit 3 for mid=3 indicates BR or BV */ 1506 static const char *uche_clients_a7xx[16] = { 1507 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", 1508 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 1509 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", 1510 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 1511 }; 1512 1513 /* LPAC has the same clients as BR and BV, but because it is 1514 * compute-only some of them do not exist and there are holes 1515 * in the array. 1516 */ 1517 static const char *uche_clients_lpac_a7xx[8] = { 1518 "-", "LPAC_SP", "-", "-", 1519 "LPAC_HLSQ", "-", "-", "LPAC_TP", 1520 }; 1521 1522 val &= GENMASK(6, 0); 1523 1524 /* mid=3 refers to BR or BV */ 1525 if (mid == 3) { 1526 if (val < ARRAY_SIZE(uche_clients_a7xx)) 1527 return uche_clients_a7xx[val]; 1528 else 1529 return "UCHE"; 1530 } 1531 1532 /* mid=8 refers to LPAC */ 1533 if (mid == 8) { 1534 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) 1535 return uche_clients_lpac_a7xx[val]; 1536 else 1537 return "UCHE_LPAC"; 1538 } 1539 1540 /* mid=2 is a catchall for everything else in LPAC */ 1541 if (mid == 2) 1542 return "UCHE_LPAC"; 1543 1544 /* mid=1 is a catchall for everything else in BR/BV */ 1545 return "UCHE"; 1546 } else if (adreno_is_a660_family(adreno_gpu)) { 1547 static const char *uche_clients_a660[8] = { 1548 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", 1549 }; 1550 1551 static const char *uche_clients_a660_not[8] = { 1552 "not VFD", "not SP", "not VSC", "not VPC", 1553 "not HLSQ", "not PC", "not LRZ", "not TP", 1554 }; 1555 1556 val &= GENMASK(6, 0); 1557 1558 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) 1559 return uche_clients_a660[val]; 1560 1561 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) 1562 return uche_clients_a660_not[val]; 1563 1564 return "UCHE"; 1565 } else { 1566 /* mid = 3 is most precise and refers to only one block per client */ 1567 if (mid == 3) 1568 return uche_clients[val & 7]; 1569 1570 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1571 if (mid == 2) 1572 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1573 1574 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1575 return "UCHE"; 1576 } 1577 } 1578 1579 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1580 { 1581 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1582 1583 if (id == 0) 1584 return "CP"; 1585 else if (id == 4) 1586 return "CCU"; 1587 else if (id == 6) 1588 return "CDP Prefetch"; 1589 else if (id == 7) 1590 return "GMU"; 1591 else if (id == 5 && adreno_is_a7xx(adreno_gpu)) 1592 return "Flag cache"; 1593 1594 return a6xx_uche_fault_block(gpu, id); 1595 } 1596 1597 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1598 { 1599 struct msm_gpu *gpu = arg; 1600 struct adreno_smmu_fault_info *info = data; 1601 const char *block = "unknown"; 1602 1603 u32 scratch[] = { 1604 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1605 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1606 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1607 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1608 }; 1609 1610 if (info) 1611 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1612 1613 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1614 } 1615 1616 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1617 { 1618 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1619 1620 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1621 u32 val; 1622 1623 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1624 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1625 dev_err_ratelimited(&gpu->pdev->dev, 1626 "CP | opcode error | possible opcode=0x%8.8X\n", 1627 val); 1628 } 1629 1630 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1631 dev_err_ratelimited(&gpu->pdev->dev, 1632 "CP ucode error interrupt\n"); 1633 1634 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1635 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1636 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1637 1638 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1639 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1640 1641 dev_err_ratelimited(&gpu->pdev->dev, 1642 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1643 val & (1 << 20) ? "READ" : "WRITE", 1644 (val & 0x3ffff), val); 1645 } 1646 1647 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) 1648 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1649 1650 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1651 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1652 1653 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1654 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1655 1656 } 1657 1658 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1659 { 1660 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1661 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1662 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1663 1664 /* 1665 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1666 * but the fault handler will trigger the devcore dump, and we want 1667 * to otherwise resume normally rather than killing the submit, so 1668 * just bail. 1669 */ 1670 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1671 return; 1672 1673 /* 1674 * Force the GPU to stay on until after we finish 1675 * collecting information 1676 */ 1677 if (!adreno_has_gmu_wrapper(adreno_gpu)) 1678 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1679 1680 DRM_DEV_ERROR(&gpu->pdev->dev, 1681 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1682 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1683 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1684 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1685 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1686 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1687 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1688 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1689 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1690 1691 /* Turn off the hangcheck timer to keep it from bothering us */ 1692 del_timer(&gpu->hangcheck_timer); 1693 1694 kthread_queue_work(gpu->worker, &gpu->recover_work); 1695 } 1696 1697 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1698 { 1699 u32 status; 1700 1701 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); 1702 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); 1703 1704 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1705 1706 /* 1707 * Ignore FASTBLEND violations, because the HW will silently fall back 1708 * to legacy blending. 1709 */ 1710 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1711 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1712 del_timer(&gpu->hangcheck_timer); 1713 1714 kthread_queue_work(gpu->worker, &gpu->recover_work); 1715 } 1716 } 1717 1718 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1719 { 1720 struct msm_drm_private *priv = gpu->dev->dev_private; 1721 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1722 1723 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1724 1725 if (priv->disable_err_irq) 1726 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1727 1728 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1729 a6xx_fault_detect_irq(gpu); 1730 1731 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1732 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1733 1734 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1735 a6xx_cp_hw_err_irq(gpu); 1736 1737 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1738 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1739 1740 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1741 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1742 1743 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1744 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1745 1746 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1747 a7xx_sw_fuse_violation_irq(gpu); 1748 1749 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { 1750 msm_gpu_retire(gpu); 1751 a6xx_preempt_trigger(gpu); 1752 } 1753 1754 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1755 a6xx_preempt_irq(gpu); 1756 1757 return IRQ_HANDLED; 1758 } 1759 1760 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1761 { 1762 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1763 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1764 } 1765 1766 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1767 { 1768 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1769 struct msm_gpu *gpu = &adreno_gpu->base; 1770 u32 cntl1_regval = 0; 1771 1772 if (IS_ERR(a6xx_gpu->llc_mmio)) 1773 return; 1774 1775 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1776 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1777 1778 gpu_scid &= 0x1f; 1779 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1780 (gpu_scid << 15) | (gpu_scid << 20); 1781 1782 /* On A660, the SCID programming for UCHE traffic is done in 1783 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1784 */ 1785 if (adreno_is_a660_family(adreno_gpu)) 1786 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1787 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1788 } 1789 1790 /* 1791 * For targets with a MMU500, activate the slice but don't program the 1792 * register. The XBL will take care of that. 1793 */ 1794 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1795 if (!a6xx_gpu->have_mmu500) { 1796 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1797 1798 gpuhtw_scid &= 0x1f; 1799 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1800 } 1801 } 1802 1803 if (!cntl1_regval) 1804 return; 1805 1806 /* 1807 * Program the slice IDs for the various GPU blocks and GPU MMU 1808 * pagetables 1809 */ 1810 if (!a6xx_gpu->have_mmu500) { 1811 a6xx_llc_write(a6xx_gpu, 1812 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1813 1814 /* 1815 * Program cacheability overrides to not allocate cache 1816 * lines on a write miss 1817 */ 1818 a6xx_llc_rmw(a6xx_gpu, 1819 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1820 return; 1821 } 1822 1823 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1824 } 1825 1826 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1827 { 1828 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1829 struct msm_gpu *gpu = &adreno_gpu->base; 1830 1831 if (IS_ERR(a6xx_gpu->llc_mmio)) 1832 return; 1833 1834 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1835 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1836 1837 gpu_scid &= GENMASK(4, 0); 1838 1839 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 1840 FIELD_PREP(GENMASK(29, 25), gpu_scid) | 1841 FIELD_PREP(GENMASK(24, 20), gpu_scid) | 1842 FIELD_PREP(GENMASK(19, 15), gpu_scid) | 1843 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1844 FIELD_PREP(GENMASK(9, 5), gpu_scid) | 1845 FIELD_PREP(GENMASK(4, 0), gpu_scid)); 1846 1847 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 1848 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1849 BIT(8)); 1850 } 1851 1852 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 1853 } 1854 1855 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1856 { 1857 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1858 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1859 return; 1860 1861 llcc_slice_putd(a6xx_gpu->llc_slice); 1862 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1863 } 1864 1865 static void a6xx_llc_slices_init(struct platform_device *pdev, 1866 struct a6xx_gpu *a6xx_gpu, bool is_a7xx) 1867 { 1868 struct device_node *phandle; 1869 1870 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1871 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1872 return; 1873 1874 /* 1875 * There is a different programming path for A6xx targets with an 1876 * mmu500 attached, so detect if that is the case 1877 */ 1878 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1879 a6xx_gpu->have_mmu500 = (phandle && 1880 of_device_is_compatible(phandle, "arm,mmu-500")); 1881 of_node_put(phandle); 1882 1883 if (is_a7xx || !a6xx_gpu->have_mmu500) 1884 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); 1885 else 1886 a6xx_gpu->llc_mmio = NULL; 1887 1888 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1889 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1890 1891 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1892 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1893 } 1894 1895 static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) 1896 { 1897 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1898 struct msm_gpu *gpu = &adreno_gpu->base; 1899 u32 fuse_val; 1900 int ret; 1901 1902 if (adreno_is_a750(adreno_gpu)) { 1903 /* 1904 * Assume that if qcom scm isn't available, that whatever 1905 * replacement allows writing the fuse register ourselves. 1906 * Users of alternative firmware need to make sure this 1907 * register is writeable or indicate that it's not somehow. 1908 * Print a warning because if you mess this up you're about to 1909 * crash horribly. 1910 */ 1911 if (!qcom_scm_is_available()) { 1912 dev_warn_once(gpu->dev->dev, 1913 "SCM is not available, poking fuse register\n"); 1914 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, 1915 A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1916 A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | 1917 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); 1918 adreno_gpu->has_ray_tracing = true; 1919 return 0; 1920 } 1921 1922 ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | 1923 QCOM_SCM_GPU_TSENSE_EN_REQ); 1924 if (ret) 1925 return ret; 1926 1927 /* 1928 * On a750 raytracing may be disabled by the firmware, find out 1929 * whether that's the case. The scm call above sets the fuse 1930 * register. 1931 */ 1932 fuse_val = a6xx_llc_read(a6xx_gpu, 1933 REG_A7XX_CX_MISC_SW_FUSE_VALUE); 1934 adreno_gpu->has_ray_tracing = 1935 !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); 1936 } else if (adreno_is_a740(adreno_gpu)) { 1937 /* Raytracing is always enabled on a740 */ 1938 adreno_gpu->has_ray_tracing = true; 1939 } 1940 1941 return 0; 1942 } 1943 1944 1945 #define GBIF_CLIENT_HALT_MASK BIT(0) 1946 #define GBIF_ARB_HALT_MASK BIT(1) 1947 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 1948 #define VBIF_RESET_ACK_MASK 0xF0 1949 #define GPR0_GBIF_HALT_REQUEST 0x1E0 1950 1951 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 1952 { 1953 struct msm_gpu *gpu = &adreno_gpu->base; 1954 1955 if (adreno_is_a619_holi(adreno_gpu)) { 1956 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 1957 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 1958 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 1959 } else if (!a6xx_has_gbif(adreno_gpu)) { 1960 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 1961 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 1962 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 1963 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 1964 1965 return; 1966 } 1967 1968 if (gx_off) { 1969 /* Halt the gx side of GBIF */ 1970 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 1971 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 1972 } 1973 1974 /* Halt new client requests on GBIF */ 1975 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 1976 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1977 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 1978 1979 /* Halt all AXI requests on GBIF */ 1980 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 1981 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1982 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 1983 1984 /* The GBIF halt needs to be explicitly cleared */ 1985 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 1986 } 1987 1988 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 1989 { 1990 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 1991 if (adreno_is_a610(to_adreno_gpu(gpu))) 1992 return; 1993 1994 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 1995 /* Perform a bogus read and add a brief delay to ensure ordering. */ 1996 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 1997 udelay(1); 1998 1999 /* The reset line needs to be asserted for at least 100 us */ 2000 if (assert) 2001 udelay(100); 2002 } 2003 2004 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 2005 { 2006 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2007 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2008 int ret; 2009 2010 gpu->needs_hw_init = true; 2011 2012 trace_msm_gpu_resume(0); 2013 2014 mutex_lock(&a6xx_gpu->gmu.lock); 2015 ret = a6xx_gmu_resume(a6xx_gpu); 2016 mutex_unlock(&a6xx_gpu->gmu.lock); 2017 if (ret) 2018 return ret; 2019 2020 msm_devfreq_resume(gpu); 2021 2022 adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu); 2023 2024 return ret; 2025 } 2026 2027 static int a6xx_pm_resume(struct msm_gpu *gpu) 2028 { 2029 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2030 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2031 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2032 unsigned long freq = gpu->fast_rate; 2033 struct dev_pm_opp *opp; 2034 int ret; 2035 2036 gpu->needs_hw_init = true; 2037 2038 trace_msm_gpu_resume(0); 2039 2040 mutex_lock(&a6xx_gpu->gmu.lock); 2041 2042 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 2043 if (IS_ERR(opp)) { 2044 ret = PTR_ERR(opp); 2045 goto err_set_opp; 2046 } 2047 dev_pm_opp_put(opp); 2048 2049 /* Set the core clock and bus bw, having VDD scaling in mind */ 2050 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 2051 2052 pm_runtime_resume_and_get(gmu->dev); 2053 pm_runtime_resume_and_get(gmu->gxpd); 2054 2055 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 2056 if (ret) 2057 goto err_bulk_clk; 2058 2059 if (adreno_is_a619_holi(adreno_gpu)) 2060 a6xx_sptprac_enable(gmu); 2061 2062 /* If anything goes south, tear the GPU down piece by piece.. */ 2063 if (ret) { 2064 err_bulk_clk: 2065 pm_runtime_put(gmu->gxpd); 2066 pm_runtime_put(gmu->dev); 2067 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2068 } 2069 err_set_opp: 2070 mutex_unlock(&a6xx_gpu->gmu.lock); 2071 2072 if (!ret) 2073 msm_devfreq_resume(gpu); 2074 2075 return ret; 2076 } 2077 2078 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 2079 { 2080 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2081 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2082 int i, ret; 2083 2084 trace_msm_gpu_suspend(0); 2085 2086 a6xx_llc_deactivate(a6xx_gpu); 2087 2088 msm_devfreq_suspend(gpu); 2089 2090 mutex_lock(&a6xx_gpu->gmu.lock); 2091 ret = a6xx_gmu_stop(a6xx_gpu); 2092 mutex_unlock(&a6xx_gpu->gmu.lock); 2093 if (ret) 2094 return ret; 2095 2096 if (a6xx_gpu->shadow_bo) 2097 for (i = 0; i < gpu->nr_rings; i++) 2098 a6xx_gpu->shadow[i] = 0; 2099 2100 gpu->suspend_count++; 2101 2102 return 0; 2103 } 2104 2105 static int a6xx_pm_suspend(struct msm_gpu *gpu) 2106 { 2107 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2108 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2109 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2110 int i; 2111 2112 trace_msm_gpu_suspend(0); 2113 2114 msm_devfreq_suspend(gpu); 2115 2116 mutex_lock(&a6xx_gpu->gmu.lock); 2117 2118 /* Drain the outstanding traffic on memory buses */ 2119 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 2120 2121 if (adreno_is_a619_holi(adreno_gpu)) 2122 a6xx_sptprac_disable(gmu); 2123 2124 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2125 2126 pm_runtime_put_sync(gmu->gxpd); 2127 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2128 pm_runtime_put_sync(gmu->dev); 2129 2130 mutex_unlock(&a6xx_gpu->gmu.lock); 2131 2132 if (a6xx_gpu->shadow_bo) 2133 for (i = 0; i < gpu->nr_rings; i++) 2134 a6xx_gpu->shadow[i] = 0; 2135 2136 gpu->suspend_count++; 2137 2138 return 0; 2139 } 2140 2141 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2142 { 2143 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2144 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2145 2146 mutex_lock(&a6xx_gpu->gmu.lock); 2147 2148 /* Force the GPU power on so we can read this register */ 2149 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2150 2151 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2152 2153 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2154 2155 mutex_unlock(&a6xx_gpu->gmu.lock); 2156 2157 return 0; 2158 } 2159 2160 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2161 { 2162 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2163 return 0; 2164 } 2165 2166 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 2167 { 2168 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2169 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2170 2171 return a6xx_gpu->cur_ring; 2172 } 2173 2174 static void a6xx_destroy(struct msm_gpu *gpu) 2175 { 2176 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2177 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2178 2179 if (a6xx_gpu->sqe_bo) { 2180 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 2181 drm_gem_object_put(a6xx_gpu->sqe_bo); 2182 } 2183 2184 if (a6xx_gpu->shadow_bo) { 2185 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 2186 drm_gem_object_put(a6xx_gpu->shadow_bo); 2187 } 2188 2189 a6xx_llc_slices_destroy(a6xx_gpu); 2190 2191 a6xx_gmu_remove(a6xx_gpu); 2192 2193 adreno_gpu_cleanup(adreno_gpu); 2194 2195 kfree(a6xx_gpu); 2196 } 2197 2198 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2199 { 2200 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2201 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2202 u64 busy_cycles; 2203 2204 /* 19.2MHz */ 2205 *out_sample_rate = 19200000; 2206 2207 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2208 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2209 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2210 2211 return busy_cycles; 2212 } 2213 2214 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2215 bool suspended) 2216 { 2217 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2218 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2219 2220 mutex_lock(&a6xx_gpu->gmu.lock); 2221 a6xx_gmu_set_freq(gpu, opp, suspended); 2222 mutex_unlock(&a6xx_gpu->gmu.lock); 2223 } 2224 2225 static struct msm_gem_address_space * 2226 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 2227 { 2228 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2229 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2230 unsigned long quirks = 0; 2231 2232 /* 2233 * This allows GPU to set the bus attributes required to use system 2234 * cache on behalf of the iommu page table walker. 2235 */ 2236 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2237 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2238 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2239 2240 return adreno_iommu_create_address_space(gpu, pdev, quirks); 2241 } 2242 2243 static struct msm_gem_address_space * 2244 a6xx_create_private_address_space(struct msm_gpu *gpu) 2245 { 2246 struct msm_mmu *mmu; 2247 2248 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 2249 2250 if (IS_ERR(mmu)) 2251 return ERR_CAST(mmu); 2252 2253 return msm_gem_address_space_create(mmu, 2254 "gpu", 0x100000000ULL, 2255 adreno_private_address_space_size(gpu)); 2256 } 2257 2258 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2259 { 2260 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2261 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2262 2263 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2264 return a6xx_gpu->shadow[ring->id]; 2265 2266 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2267 } 2268 2269 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2270 { 2271 struct msm_cp_state cp_state = { 2272 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2273 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2274 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2275 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2276 }; 2277 bool progress; 2278 2279 /* 2280 * Adjust the remaining data to account for what has already been 2281 * fetched from memory, but not yet consumed by the SQE. 2282 * 2283 * This is not *technically* correct, the amount buffered could 2284 * exceed the IB size due to hw prefetching ahead, but: 2285 * 2286 * (1) We aren't trying to find the exact position, just whether 2287 * progress has been made 2288 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2289 * to prevent prefetching into an unrelated submit. (And 2290 * either way, at some point the ROQ will be full.) 2291 */ 2292 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2293 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2294 2295 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2296 2297 ring->last_cp_state = cp_state; 2298 2299 return progress; 2300 } 2301 2302 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) 2303 { 2304 if (!info->speedbins) 2305 return UINT_MAX; 2306 2307 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) 2308 if (info->speedbins[i].fuse == fuse) 2309 return BIT(info->speedbins[i].speedbin); 2310 2311 return UINT_MAX; 2312 } 2313 2314 static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) 2315 { 2316 u32 supp_hw; 2317 u32 speedbin; 2318 int ret; 2319 2320 ret = adreno_read_speedbin(dev, &speedbin); 2321 /* 2322 * -ENOENT means that the platform doesn't support speedbin which is 2323 * fine 2324 */ 2325 if (ret == -ENOENT) { 2326 return 0; 2327 } else if (ret) { 2328 dev_err_probe(dev, ret, 2329 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2330 return ret; 2331 } 2332 2333 supp_hw = fuse_to_supp_hw(info, speedbin); 2334 2335 if (supp_hw == UINT_MAX) { 2336 DRM_DEV_ERROR(dev, 2337 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2338 speedbin); 2339 supp_hw = BIT(0); /* Default */ 2340 } 2341 2342 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2343 if (ret) 2344 return ret; 2345 2346 return 0; 2347 } 2348 2349 static const struct adreno_gpu_funcs funcs = { 2350 .base = { 2351 .get_param = adreno_get_param, 2352 .set_param = adreno_set_param, 2353 .hw_init = a6xx_hw_init, 2354 .ucode_load = a6xx_ucode_load, 2355 .pm_suspend = a6xx_gmu_pm_suspend, 2356 .pm_resume = a6xx_gmu_pm_resume, 2357 .recover = a6xx_recover, 2358 .submit = a6xx_submit, 2359 .active_ring = a6xx_active_ring, 2360 .irq = a6xx_irq, 2361 .destroy = a6xx_destroy, 2362 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2363 .show = a6xx_show, 2364 #endif 2365 .gpu_busy = a6xx_gpu_busy, 2366 .gpu_get_freq = a6xx_gmu_get_freq, 2367 .gpu_set_freq = a6xx_gpu_set_freq, 2368 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2369 .gpu_state_get = a6xx_gpu_state_get, 2370 .gpu_state_put = a6xx_gpu_state_put, 2371 #endif 2372 .create_address_space = a6xx_create_address_space, 2373 .create_private_address_space = a6xx_create_private_address_space, 2374 .get_rptr = a6xx_get_rptr, 2375 .progress = a6xx_progress, 2376 }, 2377 .get_timestamp = a6xx_gmu_get_timestamp, 2378 }; 2379 2380 static const struct adreno_gpu_funcs funcs_gmuwrapper = { 2381 .base = { 2382 .get_param = adreno_get_param, 2383 .set_param = adreno_set_param, 2384 .hw_init = a6xx_hw_init, 2385 .ucode_load = a6xx_ucode_load, 2386 .pm_suspend = a6xx_pm_suspend, 2387 .pm_resume = a6xx_pm_resume, 2388 .recover = a6xx_recover, 2389 .submit = a6xx_submit, 2390 .active_ring = a6xx_active_ring, 2391 .irq = a6xx_irq, 2392 .destroy = a6xx_destroy, 2393 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2394 .show = a6xx_show, 2395 #endif 2396 .gpu_busy = a6xx_gpu_busy, 2397 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2398 .gpu_state_get = a6xx_gpu_state_get, 2399 .gpu_state_put = a6xx_gpu_state_put, 2400 #endif 2401 .create_address_space = a6xx_create_address_space, 2402 .create_private_address_space = a6xx_create_private_address_space, 2403 .get_rptr = a6xx_get_rptr, 2404 .progress = a6xx_progress, 2405 }, 2406 .get_timestamp = a6xx_get_timestamp, 2407 }; 2408 2409 static const struct adreno_gpu_funcs funcs_a7xx = { 2410 .base = { 2411 .get_param = adreno_get_param, 2412 .set_param = adreno_set_param, 2413 .hw_init = a6xx_hw_init, 2414 .ucode_load = a6xx_ucode_load, 2415 .pm_suspend = a6xx_gmu_pm_suspend, 2416 .pm_resume = a6xx_gmu_pm_resume, 2417 .recover = a6xx_recover, 2418 .submit = a7xx_submit, 2419 .active_ring = a6xx_active_ring, 2420 .irq = a6xx_irq, 2421 .destroy = a6xx_destroy, 2422 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2423 .show = a6xx_show, 2424 #endif 2425 .gpu_busy = a6xx_gpu_busy, 2426 .gpu_get_freq = a6xx_gmu_get_freq, 2427 .gpu_set_freq = a6xx_gpu_set_freq, 2428 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2429 .gpu_state_get = a6xx_gpu_state_get, 2430 .gpu_state_put = a6xx_gpu_state_put, 2431 #endif 2432 .create_address_space = a6xx_create_address_space, 2433 .create_private_address_space = a6xx_create_private_address_space, 2434 .get_rptr = a6xx_get_rptr, 2435 .progress = a6xx_progress, 2436 }, 2437 .get_timestamp = a6xx_gmu_get_timestamp, 2438 }; 2439 2440 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2441 { 2442 struct msm_drm_private *priv = dev->dev_private; 2443 struct platform_device *pdev = priv->gpu_pdev; 2444 struct adreno_platform_config *config = pdev->dev.platform_data; 2445 struct device_node *node; 2446 struct a6xx_gpu *a6xx_gpu; 2447 struct adreno_gpu *adreno_gpu; 2448 struct msm_gpu *gpu; 2449 extern int enable_preemption; 2450 bool is_a7xx; 2451 int ret; 2452 2453 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 2454 if (!a6xx_gpu) 2455 return ERR_PTR(-ENOMEM); 2456 2457 adreno_gpu = &a6xx_gpu->base; 2458 gpu = &adreno_gpu->base; 2459 2460 mutex_init(&a6xx_gpu->gmu.lock); 2461 2462 adreno_gpu->registers = NULL; 2463 2464 /* Check if there is a GMU phandle and set it up */ 2465 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2466 /* FIXME: How do we gracefully handle this? */ 2467 BUG_ON(!node); 2468 2469 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2470 2471 adreno_gpu->base.hw_apriv = 2472 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); 2473 2474 /* gpu->info only gets assigned in adreno_gpu_init() */ 2475 is_a7xx = config->info->family == ADRENO_7XX_GEN1 || 2476 config->info->family == ADRENO_7XX_GEN2 || 2477 config->info->family == ADRENO_7XX_GEN3; 2478 2479 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); 2480 2481 ret = a6xx_set_supported_hw(&pdev->dev, config->info); 2482 if (ret) { 2483 a6xx_llc_slices_destroy(a6xx_gpu); 2484 kfree(a6xx_gpu); 2485 return ERR_PTR(ret); 2486 } 2487 2488 if ((enable_preemption == 1) || (enable_preemption == -1 && 2489 (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) 2490 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); 2491 else if (is_a7xx) 2492 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); 2493 else if (adreno_has_gmu_wrapper(adreno_gpu)) 2494 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); 2495 else 2496 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 2497 if (ret) { 2498 a6xx_destroy(&(a6xx_gpu->base.base)); 2499 return ERR_PTR(ret); 2500 } 2501 2502 /* 2503 * For now only clamp to idle freq for devices where this is known not 2504 * to cause power supply issues: 2505 */ 2506 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2507 priv->gpu_clamp_to_idle = true; 2508 2509 if (adreno_has_gmu_wrapper(adreno_gpu)) 2510 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2511 else 2512 ret = a6xx_gmu_init(a6xx_gpu, node); 2513 of_node_put(node); 2514 if (ret) { 2515 a6xx_destroy(&(a6xx_gpu->base.base)); 2516 return ERR_PTR(ret); 2517 } 2518 2519 if (adreno_is_a7xx(adreno_gpu)) { 2520 ret = a7xx_cx_mem_init(a6xx_gpu); 2521 if (ret) { 2522 a6xx_destroy(&(a6xx_gpu->base.base)); 2523 return ERR_PTR(ret); 2524 } 2525 } 2526 2527 if (gpu->aspace) 2528 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 2529 a6xx_fault_handler); 2530 2531 a6xx_calc_ubwc_config(adreno_gpu); 2532 /* Set up the preemption specific bits and pieces for each ringbuffer */ 2533 a6xx_preempt_init(gpu); 2534 2535 return gpu; 2536 } 2537