1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/firmware/qcom/qcom_scm.h> 14 #include <linux/pm_domain.h> 15 #include <linux/soc/qcom/llcc-qcom.h> 16 17 #define GPU_PAS_ID 13 18 19 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 20 { 21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 23 24 /* Check that the GMU is idle */ 25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 26 return false; 27 28 /* Check tha the CX master is idle */ 29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 30 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 31 return false; 32 33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 34 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 35 } 36 37 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 38 { 39 /* wait for CP to drain ringbuffer: */ 40 if (!adreno_idle(gpu, ring)) 41 return false; 42 43 if (spin_until(_a6xx_check_idle(gpu))) { 44 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 45 gpu->name, __builtin_return_address(0), 46 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 48 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 49 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 50 return false; 51 } 52 53 return true; 54 } 55 56 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 57 { 58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 59 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 60 61 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 63 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 66 } 67 } 68 69 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 70 { 71 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 72 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 73 uint32_t wptr; 74 unsigned long flags; 75 76 update_shadow_rptr(gpu, ring); 77 78 spin_lock_irqsave(&ring->preempt_lock, flags); 79 80 /* Copy the shadow to the actual register */ 81 ring->cur = ring->next; 82 83 /* Make sure to wrap wptr if we need to */ 84 wptr = get_wptr(ring); 85 86 /* Update HW if this is the current ring and we are not in preempt*/ 87 if (!a6xx_in_preempt(a6xx_gpu)) { 88 if (a6xx_gpu->cur_ring == ring) 89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 90 else 91 ring->restore_wptr = true; 92 } else { 93 ring->restore_wptr = true; 94 } 95 96 spin_unlock_irqrestore(&ring->preempt_lock, flags); 97 } 98 99 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 100 u64 iova) 101 { 102 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 103 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 104 CP_REG_TO_MEM_0_CNT(2) | 105 CP_REG_TO_MEM_0_64B); 106 OUT_RING(ring, lower_32_bits(iova)); 107 OUT_RING(ring, upper_32_bits(iova)); 108 } 109 110 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 111 struct msm_ringbuffer *ring, struct msm_gem_submit *submit) 112 { 113 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; 114 struct msm_file_private *ctx = submit->queue->ctx; 115 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 116 phys_addr_t ttbr; 117 u32 asid; 118 u64 memptr = rbmemptr(ring, ttbr0); 119 120 if (ctx->seqno == ring->cur_ctx_seqno) 121 return; 122 123 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 124 return; 125 126 if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { 127 /* Wait for previous submit to complete before continuing: */ 128 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 129 OUT_RING(ring, 0); 130 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 131 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 132 OUT_RING(ring, submit->seqno - 1); 133 } 134 135 if (!sysprof) { 136 if (!adreno_is_a7xx(adreno_gpu)) { 137 /* Turn off protected mode to write to special registers */ 138 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 139 OUT_RING(ring, 0); 140 } 141 142 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 143 OUT_RING(ring, 1); 144 } 145 146 /* Execute the table update */ 147 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 148 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 149 150 OUT_RING(ring, 151 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 152 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 153 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 154 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 155 156 /* 157 * Write the new TTBR0 to the memstore. This is good for debugging. 158 * Needed for preemption 159 */ 160 OUT_PKT7(ring, CP_MEM_WRITE, 5); 161 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 162 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 163 OUT_RING(ring, lower_32_bits(ttbr)); 164 OUT_RING(ring, upper_32_bits(ttbr)); 165 OUT_RING(ring, ctx->seqno); 166 167 /* 168 * Sync both threads after switching pagetables and enable BR only 169 * to make sure BV doesn't race ahead while BR is still switching 170 * pagetables. 171 */ 172 if (adreno_is_a7xx(&a6xx_gpu->base)) { 173 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 174 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 175 } 176 177 /* 178 * And finally, trigger a uche flush to be sure there isn't anything 179 * lingering in that part of the GPU 180 */ 181 182 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 183 OUT_RING(ring, CACHE_INVALIDATE); 184 185 if (!sysprof) { 186 /* 187 * Wait for SRAM clear after the pgtable update, so the 188 * two can happen in parallel: 189 */ 190 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 191 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 192 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 193 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 194 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 195 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 196 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 197 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 198 199 if (!adreno_is_a7xx(adreno_gpu)) { 200 /* Re-enable protected mode: */ 201 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 202 OUT_RING(ring, 1); 203 } 204 } 205 } 206 207 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 208 { 209 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 210 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 211 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 212 struct msm_ringbuffer *ring = submit->ring; 213 unsigned int i, ibs = 0; 214 215 a6xx_set_pagetable(a6xx_gpu, ring, submit); 216 217 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 218 rbmemptr_stats(ring, index, cpcycles_start)); 219 220 /* 221 * For PM4 the GMU register offsets are calculated from the base of the 222 * GPU registers so we need to add 0x1a800 to the register value on A630 223 * to get the right value from PM4. 224 */ 225 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 226 rbmemptr_stats(ring, index, alwayson_start)); 227 228 /* Invalidate CCU depth and color */ 229 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 230 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 231 232 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 233 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 234 235 /* Submit the commands */ 236 for (i = 0; i < submit->nr_cmds; i++) { 237 switch (submit->cmd[i].type) { 238 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 239 break; 240 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 241 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 242 break; 243 fallthrough; 244 case MSM_SUBMIT_CMD_BUF: 245 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3); 246 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 247 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 248 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size)); 249 ibs++; 250 break; 251 } 252 253 /* 254 * Periodically update shadow-wptr if needed, so that we 255 * can see partial progress of submits with large # of 256 * cmds.. otherwise we could needlessly stall waiting for 257 * ringbuffer state, simply due to looking at a shadow 258 * rptr value that has not been updated 259 */ 260 if ((ibs % 32) == 0) 261 update_shadow_rptr(gpu, ring); 262 } 263 264 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 265 rbmemptr_stats(ring, index, cpcycles_end)); 266 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 267 rbmemptr_stats(ring, index, alwayson_end)); 268 269 /* Write the fence to the scratch register */ 270 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 271 OUT_RING(ring, submit->seqno); 272 273 /* 274 * Execute a CACHE_FLUSH_TS event. This will ensure that the 275 * timestamp is written to the memory and then triggers the interrupt 276 */ 277 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 278 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 279 CP_EVENT_WRITE_0_IRQ); 280 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 281 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 282 OUT_RING(ring, submit->seqno); 283 284 trace_msm_gpu_submit_flush(submit, 285 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 286 287 a6xx_flush(gpu, ring); 288 } 289 290 static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, 291 struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) 292 { 293 u64 preempt_postamble; 294 295 OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); 296 297 OUT_RING(ring, SMMU_INFO); 298 /* don't save SMMU, we write the record from the kernel instead */ 299 OUT_RING(ring, 0); 300 OUT_RING(ring, 0); 301 302 /* privileged and non secure buffer save */ 303 OUT_RING(ring, NON_SECURE_SAVE_ADDR); 304 OUT_RING(ring, lower_32_bits( 305 a6xx_gpu->preempt_iova[ring->id])); 306 OUT_RING(ring, upper_32_bits( 307 a6xx_gpu->preempt_iova[ring->id])); 308 309 /* user context buffer save, seems to be unnused by fw */ 310 OUT_RING(ring, NON_PRIV_SAVE_ADDR); 311 OUT_RING(ring, 0); 312 OUT_RING(ring, 0); 313 314 OUT_RING(ring, COUNTER); 315 /* seems OK to set to 0 to disable it */ 316 OUT_RING(ring, 0); 317 OUT_RING(ring, 0); 318 319 /* Emit postamble to clear perfcounters */ 320 preempt_postamble = a6xx_gpu->preempt_postamble_iova; 321 322 OUT_PKT7(ring, CP_SET_AMBLE, 3); 323 OUT_RING(ring, lower_32_bits(preempt_postamble)); 324 OUT_RING(ring, upper_32_bits(preempt_postamble)); 325 OUT_RING(ring, CP_SET_AMBLE_2_DWORDS( 326 a6xx_gpu->preempt_postamble_len) | 327 CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE)); 328 } 329 330 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 331 { 332 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 333 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 334 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 335 struct msm_ringbuffer *ring = submit->ring; 336 unsigned int i, ibs = 0; 337 338 /* 339 * Toggle concurrent binning for pagetable switch and set the thread to 340 * BR since only it can execute the pagetable switch packets. 341 */ 342 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 343 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 344 345 a6xx_set_pagetable(a6xx_gpu, ring, submit); 346 347 /* 348 * If preemption is enabled, then set the pseudo register for the save 349 * sequence 350 */ 351 if (gpu->nr_rings > 1) 352 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); 353 354 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 355 rbmemptr_stats(ring, index, cpcycles_start)); 356 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 357 rbmemptr_stats(ring, index, alwayson_start)); 358 359 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 360 OUT_RING(ring, CP_SET_THREAD_BOTH); 361 362 OUT_PKT7(ring, CP_SET_MARKER, 1); 363 OUT_RING(ring, 0x101); /* IFPC disable */ 364 365 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 366 OUT_PKT7(ring, CP_SET_MARKER, 1); 367 OUT_RING(ring, 0x00d); /* IB1LIST start */ 368 } 369 370 /* Submit the commands */ 371 for (i = 0; i < submit->nr_cmds; i++) { 372 switch (submit->cmd[i].type) { 373 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 374 break; 375 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 376 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 377 break; 378 fallthrough; 379 case MSM_SUBMIT_CMD_BUF: 380 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3); 381 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 382 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 383 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size)); 384 ibs++; 385 break; 386 } 387 388 /* 389 * Periodically update shadow-wptr if needed, so that we 390 * can see partial progress of submits with large # of 391 * cmds.. otherwise we could needlessly stall waiting for 392 * ringbuffer state, simply due to looking at a shadow 393 * rptr value that has not been updated 394 */ 395 if ((ibs % 32) == 0) 396 update_shadow_rptr(gpu, ring); 397 } 398 399 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 400 OUT_PKT7(ring, CP_SET_MARKER, 1); 401 OUT_RING(ring, 0x00e); /* IB1LIST end */ 402 } 403 404 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 405 rbmemptr_stats(ring, index, cpcycles_end)); 406 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 407 rbmemptr_stats(ring, index, alwayson_end)); 408 409 /* Write the fence to the scratch register */ 410 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 411 OUT_RING(ring, submit->seqno); 412 413 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 414 OUT_RING(ring, CP_SET_THREAD_BR); 415 416 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 417 OUT_RING(ring, CCU_INVALIDATE_DEPTH); 418 419 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 420 OUT_RING(ring, CCU_INVALIDATE_COLOR); 421 422 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 423 OUT_RING(ring, CP_SET_THREAD_BV); 424 425 /* 426 * Make sure the timestamp is committed once BV pipe is 427 * completely done with this submission. 428 */ 429 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 430 OUT_RING(ring, CACHE_CLEAN | BIT(27)); 431 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 432 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 433 OUT_RING(ring, submit->seqno); 434 435 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 436 OUT_RING(ring, CP_SET_THREAD_BR); 437 438 /* 439 * This makes sure that BR doesn't race ahead and commit 440 * timestamp to memstore while BV is still processing 441 * this submission. 442 */ 443 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 444 OUT_RING(ring, 0); 445 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 446 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 447 OUT_RING(ring, submit->seqno); 448 449 a6xx_gpu->last_seqno[ring->id] = submit->seqno; 450 451 /* write the ringbuffer timestamp */ 452 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 453 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); 454 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 455 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 456 OUT_RING(ring, submit->seqno); 457 458 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 459 OUT_RING(ring, CP_SET_THREAD_BOTH); 460 461 OUT_PKT7(ring, CP_SET_MARKER, 1); 462 OUT_RING(ring, 0x100); /* IFPC enable */ 463 464 /* If preemption is enabled */ 465 if (gpu->nr_rings > 1) { 466 /* Yield the floor on command completion */ 467 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 468 469 /* 470 * If dword[2:1] are non zero, they specify an address for 471 * the CP to write the value of dword[3] to on preemption 472 * complete. Write 0 to skip the write 473 */ 474 OUT_RING(ring, 0x00); 475 OUT_RING(ring, 0x00); 476 /* Data value - not used if the address above is 0 */ 477 OUT_RING(ring, 0x01); 478 /* generate interrupt on preemption completion */ 479 OUT_RING(ring, 0x00); 480 } 481 482 483 trace_msm_gpu_submit_flush(submit, 484 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 485 486 a6xx_flush(gpu, ring); 487 488 /* Check to see if we need to start preemption */ 489 a6xx_preempt_trigger(gpu); 490 } 491 492 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 493 { 494 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 495 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 496 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 497 const struct adreno_reglist *reg; 498 unsigned int i; 499 u32 cgc_delay, cgc_hyst; 500 u32 val, clock_cntl_on; 501 502 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 503 return; 504 505 if (adreno_is_a630(adreno_gpu)) 506 clock_cntl_on = 0x8aa8aa02; 507 else if (adreno_is_a610(adreno_gpu)) 508 clock_cntl_on = 0xaaa8aa82; 509 else if (adreno_is_a702(adreno_gpu)) 510 clock_cntl_on = 0xaaaaaa82; 511 else 512 clock_cntl_on = 0x8aa8aa82; 513 514 cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; 515 cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; 516 517 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 518 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 519 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 520 state ? cgc_delay : 0); 521 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 522 state ? cgc_hyst : 0); 523 524 if (!adreno_gpu->info->a6xx->hwcg) { 525 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 526 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); 527 528 if (state) { 529 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); 530 531 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, 532 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 533 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 534 return; 535 } 536 537 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 538 } 539 540 return; 541 } 542 543 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 544 545 /* Don't re-program the registers if they are already correct */ 546 if ((!state && !val) || (state && (val == clock_cntl_on))) 547 return; 548 549 /* Disable SP clock before programming HWCG registers */ 550 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 551 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 552 553 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) 554 gpu_write(gpu, reg->offset, state ? reg->value : 0); 555 556 /* Enable SP clock */ 557 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 558 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 559 560 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 561 } 562 563 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 564 { 565 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 566 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 567 unsigned i; 568 569 /* 570 * Enable access protection to privileged registers, fault on an access 571 * protect violation and select the last span to protect from the start 572 * address all the way to the end of the register address space 573 */ 574 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 575 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | 576 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | 577 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); 578 579 for (i = 0; i < protect->count - 1; i++) { 580 /* Intentionally skip writing to some registers */ 581 if (protect->regs[i]) 582 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); 583 } 584 /* last CP_PROTECT to have "infinite" length on the last entry */ 585 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); 586 } 587 588 static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 589 { 590 gpu->ubwc_config.rgb565_predicator = 0; 591 gpu->ubwc_config.uavflagprd_inv = 0; 592 gpu->ubwc_config.min_acc_len = 0; 593 gpu->ubwc_config.ubwc_swizzle = 0x6; 594 gpu->ubwc_config.macrotile_mode = 0; 595 gpu->ubwc_config.highest_bank_bit = 15; 596 597 if (adreno_is_a610(gpu)) { 598 gpu->ubwc_config.highest_bank_bit = 13; 599 gpu->ubwc_config.min_acc_len = 1; 600 gpu->ubwc_config.ubwc_swizzle = 0x7; 601 } 602 603 if (adreno_is_a618(gpu)) 604 gpu->ubwc_config.highest_bank_bit = 14; 605 606 if (adreno_is_a619(gpu)) 607 /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ 608 gpu->ubwc_config.highest_bank_bit = 13; 609 610 if (adreno_is_a619_holi(gpu)) 611 gpu->ubwc_config.highest_bank_bit = 13; 612 613 if (adreno_is_a621(gpu)) { 614 gpu->ubwc_config.highest_bank_bit = 13; 615 gpu->ubwc_config.amsbc = 1; 616 gpu->ubwc_config.uavflagprd_inv = 2; 617 } 618 619 if (adreno_is_a623(gpu)) { 620 gpu->ubwc_config.highest_bank_bit = 16; 621 gpu->ubwc_config.amsbc = 1; 622 gpu->ubwc_config.rgb565_predicator = 1; 623 gpu->ubwc_config.uavflagprd_inv = 2; 624 gpu->ubwc_config.macrotile_mode = 1; 625 } 626 627 if (adreno_is_a640_family(gpu)) 628 gpu->ubwc_config.amsbc = 1; 629 630 if (adreno_is_a680(gpu)) 631 gpu->ubwc_config.macrotile_mode = 1; 632 633 if (adreno_is_a650(gpu) || 634 adreno_is_a660(gpu) || 635 adreno_is_a690(gpu) || 636 adreno_is_a730(gpu) || 637 adreno_is_a740_family(gpu)) { 638 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 639 gpu->ubwc_config.highest_bank_bit = 16; 640 gpu->ubwc_config.amsbc = 1; 641 gpu->ubwc_config.rgb565_predicator = 1; 642 gpu->ubwc_config.uavflagprd_inv = 2; 643 gpu->ubwc_config.macrotile_mode = 1; 644 } 645 646 if (adreno_is_a663(gpu)) { 647 gpu->ubwc_config.highest_bank_bit = 13; 648 gpu->ubwc_config.amsbc = 1; 649 gpu->ubwc_config.rgb565_predicator = 1; 650 gpu->ubwc_config.uavflagprd_inv = 2; 651 gpu->ubwc_config.macrotile_mode = 1; 652 gpu->ubwc_config.ubwc_swizzle = 0x4; 653 } 654 655 if (adreno_is_7c3(gpu)) { 656 gpu->ubwc_config.highest_bank_bit = 14; 657 gpu->ubwc_config.amsbc = 1; 658 gpu->ubwc_config.uavflagprd_inv = 2; 659 gpu->ubwc_config.macrotile_mode = 1; 660 } 661 662 if (adreno_is_a702(gpu)) { 663 gpu->ubwc_config.highest_bank_bit = 14; 664 gpu->ubwc_config.min_acc_len = 1; 665 } 666 } 667 668 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 669 { 670 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 671 /* 672 * We subtract 13 from the highest bank bit (13 is the minimum value 673 * allowed by hw) and write the lowest two bits of the remaining value 674 * as hbb_lo and the one above it as hbb_hi to the hardware. 675 */ 676 BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); 677 u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; 678 u32 hbb_hi = hbb >> 2; 679 u32 hbb_lo = hbb & 3; 680 u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; 681 u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); 682 683 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 684 level2_swizzling_dis << 12 | 685 adreno_gpu->ubwc_config.rgb565_predicator << 11 | 686 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | 687 adreno_gpu->ubwc_config.min_acc_len << 3 | 688 hbb_lo << 1 | ubwc_mode); 689 690 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 691 level2_swizzling_dis << 6 | hbb_hi << 4 | 692 adreno_gpu->ubwc_config.min_acc_len << 3 | 693 hbb_lo << 1 | ubwc_mode); 694 695 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 696 level2_swizzling_dis << 12 | hbb_hi << 10 | 697 adreno_gpu->ubwc_config.uavflagprd_inv << 4 | 698 adreno_gpu->ubwc_config.min_acc_len << 3 | 699 hbb_lo << 1 | ubwc_mode); 700 701 if (adreno_is_a7xx(adreno_gpu)) 702 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 703 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 704 705 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 706 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); 707 708 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 709 adreno_gpu->ubwc_config.macrotile_mode); 710 } 711 712 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 713 { 714 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 715 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 716 const struct adreno_reglist_list *reglist; 717 void *ptr = a6xx_gpu->pwrup_reglist_ptr; 718 struct cpu_gpu_lock *lock = ptr; 719 u32 *dest = (u32 *)&lock->regs[0]; 720 int i; 721 722 reglist = adreno_gpu->info->a6xx->pwrup_reglist; 723 724 lock->gpu_req = lock->cpu_req = lock->turn = 0; 725 lock->ifpc_list_len = 0; 726 lock->preemption_list_len = reglist->count; 727 728 /* 729 * For each entry in each of the lists, write the offset and the current 730 * register value into the GPU buffer 731 */ 732 for (i = 0; i < reglist->count; i++) { 733 *dest++ = reglist->regs[i]; 734 *dest++ = gpu_read(gpu, reglist->regs[i]); 735 } 736 737 /* 738 * The overall register list is composed of 739 * 1. Static IFPC-only registers 740 * 2. Static IFPC + preemption registers 741 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) 742 * 743 * The first two lists are static. Size of these lists are stored as 744 * number of pairs in ifpc_list_len and preemption_list_len 745 * respectively. With concurrent binning, Some of the perfcounter 746 * registers being virtualized, CP needs to know the pipe id to program 747 * the aperture inorder to restore the same. Thus, third list is a 748 * dynamic list with triplets as 749 * (<aperture, shifted 12 bits> <address> <data>), and the length is 750 * stored as number for triplets in dynamic_list_len. 751 */ 752 lock->dynamic_list_len = 0; 753 } 754 755 static int a7xx_preempt_start(struct msm_gpu *gpu) 756 { 757 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 758 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 759 struct msm_ringbuffer *ring = gpu->rb[0]; 760 761 if (gpu->nr_rings <= 1) 762 return 0; 763 764 /* Turn CP protection off */ 765 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 766 OUT_RING(ring, 0); 767 768 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); 769 770 /* Yield the floor on command completion */ 771 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 772 OUT_RING(ring, 0x00); 773 OUT_RING(ring, 0x00); 774 OUT_RING(ring, 0x00); 775 /* Generate interrupt on preemption completion */ 776 OUT_RING(ring, 0x00); 777 778 a6xx_flush(gpu, ring); 779 780 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 781 } 782 783 static int a6xx_cp_init(struct msm_gpu *gpu) 784 { 785 struct msm_ringbuffer *ring = gpu->rb[0]; 786 787 OUT_PKT7(ring, CP_ME_INIT, 8); 788 789 OUT_RING(ring, 0x0000002f); 790 791 /* Enable multiple hardware contexts */ 792 OUT_RING(ring, 0x00000003); 793 794 /* Enable error detection */ 795 OUT_RING(ring, 0x20000000); 796 797 /* Don't enable header dump */ 798 OUT_RING(ring, 0x00000000); 799 OUT_RING(ring, 0x00000000); 800 801 /* No workarounds enabled */ 802 OUT_RING(ring, 0x00000000); 803 804 /* Pad rest of the cmds with 0's */ 805 OUT_RING(ring, 0x00000000); 806 OUT_RING(ring, 0x00000000); 807 808 a6xx_flush(gpu, ring); 809 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 810 } 811 812 static int a7xx_cp_init(struct msm_gpu *gpu) 813 { 814 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 815 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 816 struct msm_ringbuffer *ring = gpu->rb[0]; 817 u32 mask; 818 819 /* Disable concurrent binning before sending CP init */ 820 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 821 OUT_RING(ring, BIT(27)); 822 823 OUT_PKT7(ring, CP_ME_INIT, 7); 824 825 /* Use multiple HW contexts */ 826 mask = BIT(0); 827 828 /* Enable error detection */ 829 mask |= BIT(1); 830 831 /* Set default reset state */ 832 mask |= BIT(3); 833 834 /* Disable save/restore of performance counters across preemption */ 835 mask |= BIT(6); 836 837 /* Enable the register init list with the spinlock */ 838 mask |= BIT(8); 839 840 OUT_RING(ring, mask); 841 842 /* Enable multiple hardware contexts */ 843 OUT_RING(ring, 0x00000003); 844 845 /* Enable error detection */ 846 OUT_RING(ring, 0x20000000); 847 848 /* Operation mode mask */ 849 OUT_RING(ring, 0x00000002); 850 851 /* *Don't* send a power up reg list for concurrent binning (TODO) */ 852 /* Lo address */ 853 OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); 854 /* Hi address */ 855 OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); 856 /* BIT(31) set => read the regs from the list */ 857 OUT_RING(ring, BIT(31)); 858 859 a6xx_flush(gpu, ring); 860 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 861 } 862 863 /* 864 * Check that the microcode version is new enough to include several key 865 * security fixes. Return true if the ucode is safe. 866 */ 867 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 868 struct drm_gem_object *obj) 869 { 870 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 871 struct msm_gpu *gpu = &adreno_gpu->base; 872 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 873 u32 *buf = msm_gem_get_vaddr(obj); 874 bool ret = false; 875 876 if (IS_ERR(buf)) 877 return false; 878 879 /* A7xx is safe! */ 880 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) 881 return true; 882 883 /* 884 * Targets up to a640 (a618, a630 and a640) need to check for a 885 * microcode version that is patched to support the whereami opcode or 886 * one that is new enough to include it by default. 887 * 888 * a650 tier targets don't need whereami but still need to be 889 * equal to or newer than 0.95 for other security fixes 890 * 891 * a660 targets have all the critical security fixes from the start 892 */ 893 if (!strcmp(sqe_name, "a630_sqe.fw")) { 894 /* 895 * If the lowest nibble is 0xa that is an indication that this 896 * microcode has been patched. The actual version is in dword 897 * [3] but we only care about the patchlevel which is the lowest 898 * nibble of dword [3] 899 * 900 * Otherwise check that the firmware is greater than or equal 901 * to 1.90 which was the first version that had this fix built 902 * in 903 */ 904 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 905 (buf[0] & 0xfff) >= 0x190) { 906 a6xx_gpu->has_whereami = true; 907 ret = true; 908 goto out; 909 } 910 911 DRM_DEV_ERROR(&gpu->pdev->dev, 912 "a630 SQE ucode is too old. Have version %x need at least %x\n", 913 buf[0] & 0xfff, 0x190); 914 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 915 if ((buf[0] & 0xfff) >= 0x095) { 916 ret = true; 917 goto out; 918 } 919 920 DRM_DEV_ERROR(&gpu->pdev->dev, 921 "a650 SQE ucode is too old. Have version %x need at least %x\n", 922 buf[0] & 0xfff, 0x095); 923 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 924 ret = true; 925 } else { 926 DRM_DEV_ERROR(&gpu->pdev->dev, 927 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 928 } 929 out: 930 msm_gem_put_vaddr(obj); 931 return ret; 932 } 933 934 static int a6xx_ucode_load(struct msm_gpu *gpu) 935 { 936 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 937 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 938 939 if (!a6xx_gpu->sqe_bo) { 940 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 941 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 942 943 if (IS_ERR(a6xx_gpu->sqe_bo)) { 944 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 945 946 a6xx_gpu->sqe_bo = NULL; 947 DRM_DEV_ERROR(&gpu->pdev->dev, 948 "Could not allocate SQE ucode: %d\n", ret); 949 950 return ret; 951 } 952 953 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 954 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 955 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 956 drm_gem_object_put(a6xx_gpu->sqe_bo); 957 958 a6xx_gpu->sqe_bo = NULL; 959 return -EPERM; 960 } 961 } 962 963 /* 964 * Expanded APRIV and targets that support WHERE_AM_I both need a 965 * privileged buffer to store the RPTR shadow 966 */ 967 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 968 !a6xx_gpu->shadow_bo) { 969 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 970 sizeof(u32) * gpu->nr_rings, 971 MSM_BO_WC | MSM_BO_MAP_PRIV, 972 gpu->aspace, &a6xx_gpu->shadow_bo, 973 &a6xx_gpu->shadow_iova); 974 975 if (IS_ERR(a6xx_gpu->shadow)) 976 return PTR_ERR(a6xx_gpu->shadow); 977 978 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 979 } 980 981 a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, 982 MSM_BO_WC | MSM_BO_MAP_PRIV, 983 gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, 984 &a6xx_gpu->pwrup_reglist_iova); 985 986 if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) 987 return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); 988 989 msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); 990 991 return 0; 992 } 993 994 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 995 { 996 static bool loaded; 997 int ret; 998 999 if (loaded) 1000 return 0; 1001 1002 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 1003 1004 loaded = !ret; 1005 return ret; 1006 } 1007 1008 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1009 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1010 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1011 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 1012 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 1013 A6XX_RBBM_INT_0_MASK_CP_RB | \ 1014 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1015 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1016 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1017 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1018 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 1019 1020 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1021 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1022 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 1023 A6XX_RBBM_INT_0_MASK_CP_SW | \ 1024 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1025 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 1026 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 1027 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1028 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1029 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1030 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1031 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 1032 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 1033 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1034 1035 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ 1036 A6XX_CP_APRIV_CNTL_RBFETCH | \ 1037 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \ 1038 A6XX_CP_APRIV_CNTL_RBRPWB) 1039 1040 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \ 1041 A6XX_CP_APRIV_CNTL_CDREAD | \ 1042 A6XX_CP_APRIV_CNTL_CDWRITE) 1043 1044 static int hw_init(struct msm_gpu *gpu) 1045 { 1046 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1047 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1048 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1049 u64 gmem_range_min; 1050 unsigned int i; 1051 int ret; 1052 1053 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1054 /* Make sure the GMU keeps the GPU on while we set it up */ 1055 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1056 if (ret) 1057 return ret; 1058 } 1059 1060 /* Clear GBIF halt in case GX domain was not collapsed */ 1061 if (adreno_is_a619_holi(adreno_gpu)) { 1062 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1063 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1064 1065 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 1066 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); 1067 } else if (a6xx_has_gbif(adreno_gpu)) { 1068 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1069 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1070 1071 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 1072 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); 1073 } 1074 1075 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 1076 1077 if (adreno_is_a619_holi(adreno_gpu)) 1078 a6xx_sptprac_enable(gmu); 1079 1080 /* 1081 * Disable the trusted memory range - we don't actually supported secure 1082 * memory rendering at this point in time and we don't want to block off 1083 * part of the virtual memory space. 1084 */ 1085 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 1086 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 1087 1088 if (!adreno_is_a7xx(adreno_gpu)) { 1089 /* Turn on 64 bit addressing for all blocks */ 1090 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 1091 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 1092 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 1093 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 1094 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 1095 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 1096 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 1097 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 1098 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 1099 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 1100 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 1101 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 1102 } 1103 1104 /* enable hardware clockgating */ 1105 a6xx_set_hwcg(gpu, true); 1106 1107 /* VBIF/GBIF start*/ 1108 if (adreno_is_a610_family(adreno_gpu) || 1109 adreno_is_a640_family(adreno_gpu) || 1110 adreno_is_a650_family(adreno_gpu) || 1111 adreno_is_a7xx(adreno_gpu)) { 1112 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 1113 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 1114 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 1115 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 1116 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 1117 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); 1118 } else { 1119 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 1120 } 1121 1122 if (adreno_is_a630(adreno_gpu)) 1123 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 1124 1125 if (adreno_is_a7xx(adreno_gpu)) 1126 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); 1127 1128 /* Make all blocks contribute to the GPU BUSY perf counter */ 1129 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 1130 1131 /* Disable L2 bypass in the UCHE */ 1132 if (adreno_is_a7xx(adreno_gpu)) { 1133 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 1134 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 1135 } else { 1136 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0); 1137 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 1138 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 1139 } 1140 1141 if (!(adreno_is_a650_family(adreno_gpu) || 1142 adreno_is_a702(adreno_gpu) || 1143 adreno_is_a730(adreno_gpu))) { 1144 gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; 1145 1146 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 1147 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); 1148 1149 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 1150 gmem_range_min + adreno_gpu->info->gmem - 1); 1151 } 1152 1153 if (adreno_is_a7xx(adreno_gpu)) 1154 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); 1155 else { 1156 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 1157 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 1158 } 1159 1160 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 1161 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1162 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1163 } else if (adreno_is_a610_family(adreno_gpu)) { 1164 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 1165 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 1166 } else if (!adreno_is_a7xx(adreno_gpu)) { 1167 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 1168 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1169 } 1170 1171 if (adreno_is_a660_family(adreno_gpu)) 1172 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1173 1174 /* Setting the mem pool size */ 1175 if (adreno_is_a610(adreno_gpu)) { 1176 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 1177 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 1178 } else if (adreno_is_a702(adreno_gpu)) { 1179 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); 1180 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); 1181 } else if (!adreno_is_a7xx(adreno_gpu)) 1182 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 1183 1184 1185 /* Set the default primFifo threshold values */ 1186 if (adreno_gpu->info->a6xx->prim_fifo_threshold) 1187 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 1188 adreno_gpu->info->a6xx->prim_fifo_threshold); 1189 1190 /* Set the AHB default slave response to "ERROR" */ 1191 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1192 1193 /* Turn on performance counters */ 1194 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1195 1196 if (adreno_is_a7xx(adreno_gpu)) { 1197 /* Turn on the IFPC counter (countable 4 on XOCLK4) */ 1198 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1199 FIELD_PREP(GENMASK(7, 0), 0x4)); 1200 } 1201 1202 /* Select CP0 to always count cycles */ 1203 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1204 1205 a6xx_set_ubwc_config(gpu); 1206 1207 /* Enable fault detection */ 1208 if (adreno_is_a730(adreno_gpu) || 1209 adreno_is_a740_family(adreno_gpu)) 1210 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); 1211 else if (adreno_is_a690(adreno_gpu)) 1212 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); 1213 else if (adreno_is_a619(adreno_gpu)) 1214 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1215 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 1216 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1217 else 1218 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1219 1220 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1221 1222 /* Set weights for bicubic filtering */ 1223 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1224 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1225 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1226 0x3fe05ff4); 1227 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1228 0x3fa0ebee); 1229 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1230 0x3f5193ed); 1231 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1232 0x3f0243f0); 1233 } 1234 1235 /* Set up the CX GMU counter 0 to count busy ticks */ 1236 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1237 1238 /* Enable the power counter */ 1239 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1240 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1241 1242 /* Protect registers from the CP */ 1243 a6xx_set_cp_protect(gpu); 1244 1245 if (adreno_is_a660_family(adreno_gpu)) { 1246 if (adreno_is_a690(adreno_gpu)) 1247 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); 1248 else 1249 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1250 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1251 } else if (adreno_is_a702(adreno_gpu)) { 1252 /* Something to do with the HLSQ cluster */ 1253 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); 1254 } 1255 1256 if (adreno_is_a690(adreno_gpu)) 1257 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); 1258 /* Set dualQ + disable afull for A660 GPU */ 1259 else if (adreno_is_a660(adreno_gpu) || adreno_is_a663(adreno_gpu)) 1260 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1261 else if (adreno_is_a7xx(adreno_gpu)) 1262 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 1263 FIELD_PREP(GENMASK(19, 16), 6) | 1264 FIELD_PREP(GENMASK(15, 12), 6) | 1265 FIELD_PREP(GENMASK(11, 8), 9) | 1266 BIT(3) | BIT(2) | 1267 FIELD_PREP(GENMASK(1, 0), 2)); 1268 1269 /* Enable expanded apriv for targets that support it */ 1270 if (gpu->hw_apriv) { 1271 if (adreno_is_a7xx(adreno_gpu)) { 1272 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1273 A7XX_BR_APRIVMASK); 1274 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, 1275 A7XX_APRIV_MASK); 1276 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, 1277 A7XX_APRIV_MASK); 1278 } else 1279 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1280 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); 1281 } 1282 1283 if (adreno_is_a750(adreno_gpu)) { 1284 /* Disable ubwc merged UFC request feature */ 1285 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); 1286 1287 /* Enable TP flaghint and other performance settings */ 1288 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); 1289 } else if (adreno_is_a7xx(adreno_gpu)) { 1290 /* Disable non-ubwc read reqs from passing write reqs */ 1291 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); 1292 } 1293 1294 /* Enable interrupts */ 1295 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 1296 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); 1297 1298 ret = adreno_hw_init(gpu); 1299 if (ret) 1300 goto out; 1301 1302 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1303 1304 /* Set the ringbuffer address */ 1305 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1306 1307 /* Targets that support extended APRIV can use the RPTR shadow from 1308 * hardware but all the other ones need to disable the feature. Targets 1309 * that support the WHERE_AM_I opcode can use that instead 1310 */ 1311 if (adreno_gpu->base.hw_apriv) 1312 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1313 else 1314 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1315 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1316 1317 /* Configure the RPTR shadow if needed: */ 1318 if (a6xx_gpu->shadow_bo) { 1319 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1320 shadowptr(a6xx_gpu, gpu->rb[0])); 1321 for (unsigned int i = 0; i < gpu->nr_rings; i++) 1322 a6xx_gpu->shadow[i] = 0; 1323 } 1324 1325 /* ..which means "always" on A7xx, also for BV shadow */ 1326 if (adreno_is_a7xx(adreno_gpu)) { 1327 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, 1328 rbmemptr(gpu->rb[0], bv_rptr)); 1329 } 1330 1331 a6xx_preempt_hw_init(gpu); 1332 1333 /* Always come up on rb 0 */ 1334 a6xx_gpu->cur_ring = gpu->rb[0]; 1335 1336 for (i = 0; i < gpu->nr_rings; i++) 1337 gpu->rb[i]->cur_ctx_seqno = 0; 1338 1339 /* Enable the SQE_to start the CP engine */ 1340 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1341 1342 if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { 1343 a7xx_patch_pwrup_reglist(gpu); 1344 a6xx_gpu->pwrup_reglist_emitted = true; 1345 } 1346 1347 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); 1348 if (ret) 1349 goto out; 1350 1351 /* 1352 * Try to load a zap shader into the secure world. If successful 1353 * we can use the CP to switch out of secure mode. If not then we 1354 * have no resource but to try to switch ourselves out manually. If we 1355 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1356 * be blocked and a permissions violation will soon follow. 1357 */ 1358 ret = a6xx_zap_shader_init(gpu); 1359 if (!ret) { 1360 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1361 OUT_RING(gpu->rb[0], 0x00000000); 1362 1363 a6xx_flush(gpu, gpu->rb[0]); 1364 if (!a6xx_idle(gpu, gpu->rb[0])) 1365 return -EINVAL; 1366 } else if (ret == -ENODEV) { 1367 /* 1368 * This device does not use zap shader (but print a warning 1369 * just in case someone got their dt wrong.. hopefully they 1370 * have a debug UART to realize the error of their ways... 1371 * if you mess this up you are about to crash horribly) 1372 */ 1373 dev_warn_once(gpu->dev->dev, 1374 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1375 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1376 ret = 0; 1377 } else { 1378 return ret; 1379 } 1380 1381 out: 1382 if (adreno_has_gmu_wrapper(adreno_gpu)) 1383 return ret; 1384 1385 /* Last step - yield the ringbuffer */ 1386 a7xx_preempt_start(gpu); 1387 1388 /* 1389 * Tell the GMU that we are done touching the GPU and it can start power 1390 * management 1391 */ 1392 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1393 1394 if (a6xx_gpu->gmu.legacy) { 1395 /* Take the GMU out of its special boot mode */ 1396 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1397 } 1398 1399 return ret; 1400 } 1401 1402 static int a6xx_hw_init(struct msm_gpu *gpu) 1403 { 1404 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1405 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1406 int ret; 1407 1408 mutex_lock(&a6xx_gpu->gmu.lock); 1409 ret = hw_init(gpu); 1410 mutex_unlock(&a6xx_gpu->gmu.lock); 1411 1412 return ret; 1413 } 1414 1415 static void a6xx_dump(struct msm_gpu *gpu) 1416 { 1417 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1418 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1419 adreno_dump(gpu); 1420 } 1421 1422 static void a6xx_recover(struct msm_gpu *gpu) 1423 { 1424 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1425 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1426 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1427 int i, active_submits; 1428 1429 adreno_dump_info(gpu); 1430 1431 for (i = 0; i < 8; i++) 1432 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1433 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1434 1435 if (hang_debug) 1436 a6xx_dump(gpu); 1437 1438 /* 1439 * To handle recovery specific sequences during the rpm suspend we are 1440 * about to trigger 1441 */ 1442 a6xx_gpu->hung = true; 1443 1444 /* Halt SQE first */ 1445 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1446 1447 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1448 1449 /* active_submit won't change until we make a submission */ 1450 mutex_lock(&gpu->active_lock); 1451 active_submits = gpu->active_submits; 1452 1453 /* 1454 * Temporarily clear active_submits count to silence a WARN() in the 1455 * runtime suspend cb 1456 */ 1457 gpu->active_submits = 0; 1458 1459 if (adreno_has_gmu_wrapper(adreno_gpu)) { 1460 /* Drain the outstanding traffic on memory buses */ 1461 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1462 1463 /* Reset the GPU to a clean state */ 1464 a6xx_gpu_sw_reset(gpu, true); 1465 a6xx_gpu_sw_reset(gpu, false); 1466 } 1467 1468 reinit_completion(&gmu->pd_gate); 1469 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1470 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1471 1472 /* Drop the rpm refcount from active submits */ 1473 if (active_submits) 1474 pm_runtime_put(&gpu->pdev->dev); 1475 1476 /* And the final one from recover worker */ 1477 pm_runtime_put_sync(&gpu->pdev->dev); 1478 1479 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1480 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1481 1482 dev_pm_genpd_remove_notifier(gmu->cxpd); 1483 1484 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1485 1486 if (active_submits) 1487 pm_runtime_get(&gpu->pdev->dev); 1488 1489 pm_runtime_get_sync(&gpu->pdev->dev); 1490 1491 gpu->active_submits = active_submits; 1492 mutex_unlock(&gpu->active_lock); 1493 1494 msm_gpu_hw_init(gpu); 1495 a6xx_gpu->hung = false; 1496 } 1497 1498 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1499 { 1500 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1501 static const char *uche_clients[7] = { 1502 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1503 }; 1504 u32 val; 1505 1506 if (adreno_is_a7xx(adreno_gpu)) { 1507 if (mid != 1 && mid != 2 && mid != 3 && mid != 8) 1508 return "UNKNOWN"; 1509 } else { 1510 if (mid < 1 || mid > 3) 1511 return "UNKNOWN"; 1512 } 1513 1514 /* 1515 * The source of the data depends on the mid ID read from FSYNR1. 1516 * and the client ID read from the UCHE block 1517 */ 1518 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1519 1520 if (adreno_is_a7xx(adreno_gpu)) { 1521 /* Bit 3 for mid=3 indicates BR or BV */ 1522 static const char *uche_clients_a7xx[16] = { 1523 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", 1524 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 1525 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", 1526 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 1527 }; 1528 1529 /* LPAC has the same clients as BR and BV, but because it is 1530 * compute-only some of them do not exist and there are holes 1531 * in the array. 1532 */ 1533 static const char *uche_clients_lpac_a7xx[8] = { 1534 "-", "LPAC_SP", "-", "-", 1535 "LPAC_HLSQ", "-", "-", "LPAC_TP", 1536 }; 1537 1538 val &= GENMASK(6, 0); 1539 1540 /* mid=3 refers to BR or BV */ 1541 if (mid == 3) { 1542 if (val < ARRAY_SIZE(uche_clients_a7xx)) 1543 return uche_clients_a7xx[val]; 1544 else 1545 return "UCHE"; 1546 } 1547 1548 /* mid=8 refers to LPAC */ 1549 if (mid == 8) { 1550 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) 1551 return uche_clients_lpac_a7xx[val]; 1552 else 1553 return "UCHE_LPAC"; 1554 } 1555 1556 /* mid=2 is a catchall for everything else in LPAC */ 1557 if (mid == 2) 1558 return "UCHE_LPAC"; 1559 1560 /* mid=1 is a catchall for everything else in BR/BV */ 1561 return "UCHE"; 1562 } else if (adreno_is_a660_family(adreno_gpu)) { 1563 static const char *uche_clients_a660[8] = { 1564 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", 1565 }; 1566 1567 static const char *uche_clients_a660_not[8] = { 1568 "not VFD", "not SP", "not VSC", "not VPC", 1569 "not HLSQ", "not PC", "not LRZ", "not TP", 1570 }; 1571 1572 val &= GENMASK(6, 0); 1573 1574 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) 1575 return uche_clients_a660[val]; 1576 1577 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) 1578 return uche_clients_a660_not[val]; 1579 1580 return "UCHE"; 1581 } else { 1582 /* mid = 3 is most precise and refers to only one block per client */ 1583 if (mid == 3) 1584 return uche_clients[val & 7]; 1585 1586 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1587 if (mid == 2) 1588 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1589 1590 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1591 return "UCHE"; 1592 } 1593 } 1594 1595 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1596 { 1597 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1598 1599 if (id == 0) 1600 return "CP"; 1601 else if (id == 4) 1602 return "CCU"; 1603 else if (id == 6) 1604 return "CDP Prefetch"; 1605 else if (id == 7) 1606 return "GMU"; 1607 else if (id == 5 && adreno_is_a7xx(adreno_gpu)) 1608 return "Flag cache"; 1609 1610 return a6xx_uche_fault_block(gpu, id); 1611 } 1612 1613 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1614 { 1615 struct msm_gpu *gpu = arg; 1616 struct adreno_smmu_fault_info *info = data; 1617 const char *block = "unknown"; 1618 1619 u32 scratch[] = { 1620 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1621 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1622 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1623 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1624 }; 1625 1626 if (info) 1627 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1628 1629 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1630 } 1631 1632 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1633 { 1634 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1635 1636 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1637 u32 val; 1638 1639 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1640 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1641 dev_err_ratelimited(&gpu->pdev->dev, 1642 "CP | opcode error | possible opcode=0x%8.8X\n", 1643 val); 1644 } 1645 1646 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1647 dev_err_ratelimited(&gpu->pdev->dev, 1648 "CP ucode error interrupt\n"); 1649 1650 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1651 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1652 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1653 1654 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1655 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1656 1657 dev_err_ratelimited(&gpu->pdev->dev, 1658 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1659 val & (1 << 20) ? "READ" : "WRITE", 1660 (val & 0x3ffff), val); 1661 } 1662 1663 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) 1664 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1665 1666 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1667 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1668 1669 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1670 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1671 1672 } 1673 1674 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1675 { 1676 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1677 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1678 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1679 1680 /* 1681 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1682 * but the fault handler will trigger the devcore dump, and we want 1683 * to otherwise resume normally rather than killing the submit, so 1684 * just bail. 1685 */ 1686 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1687 return; 1688 1689 /* 1690 * Force the GPU to stay on until after we finish 1691 * collecting information 1692 */ 1693 if (!adreno_has_gmu_wrapper(adreno_gpu)) 1694 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1695 1696 DRM_DEV_ERROR(&gpu->pdev->dev, 1697 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1698 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1699 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1700 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1701 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1702 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1703 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1704 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1705 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1706 1707 /* Turn off the hangcheck timer to keep it from bothering us */ 1708 timer_delete(&gpu->hangcheck_timer); 1709 1710 kthread_queue_work(gpu->worker, &gpu->recover_work); 1711 } 1712 1713 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1714 { 1715 u32 status; 1716 1717 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); 1718 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); 1719 1720 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1721 1722 /* 1723 * Ignore FASTBLEND violations, because the HW will silently fall back 1724 * to legacy blending. 1725 */ 1726 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1727 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1728 timer_delete(&gpu->hangcheck_timer); 1729 1730 kthread_queue_work(gpu->worker, &gpu->recover_work); 1731 } 1732 } 1733 1734 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1735 { 1736 struct msm_drm_private *priv = gpu->dev->dev_private; 1737 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1738 1739 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1740 1741 if (priv->disable_err_irq) 1742 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1743 1744 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1745 a6xx_fault_detect_irq(gpu); 1746 1747 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1748 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1749 1750 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1751 a6xx_cp_hw_err_irq(gpu); 1752 1753 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1754 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1755 1756 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1757 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1758 1759 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1760 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1761 1762 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1763 a7xx_sw_fuse_violation_irq(gpu); 1764 1765 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { 1766 msm_gpu_retire(gpu); 1767 a6xx_preempt_trigger(gpu); 1768 } 1769 1770 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1771 a6xx_preempt_irq(gpu); 1772 1773 return IRQ_HANDLED; 1774 } 1775 1776 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1777 { 1778 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1779 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1780 } 1781 1782 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1783 { 1784 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1785 struct msm_gpu *gpu = &adreno_gpu->base; 1786 u32 cntl1_regval = 0; 1787 1788 if (IS_ERR(a6xx_gpu->llc_mmio)) 1789 return; 1790 1791 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1792 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1793 1794 gpu_scid &= 0x1f; 1795 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1796 (gpu_scid << 15) | (gpu_scid << 20); 1797 1798 /* On A660, the SCID programming for UCHE traffic is done in 1799 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1800 */ 1801 if (adreno_is_a660_family(adreno_gpu)) 1802 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1803 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1804 } 1805 1806 /* 1807 * For targets with a MMU500, activate the slice but don't program the 1808 * register. The XBL will take care of that. 1809 */ 1810 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1811 if (!a6xx_gpu->have_mmu500) { 1812 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1813 1814 gpuhtw_scid &= 0x1f; 1815 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1816 } 1817 } 1818 1819 if (!cntl1_regval) 1820 return; 1821 1822 /* 1823 * Program the slice IDs for the various GPU blocks and GPU MMU 1824 * pagetables 1825 */ 1826 if (!a6xx_gpu->have_mmu500) { 1827 a6xx_llc_write(a6xx_gpu, 1828 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1829 1830 /* 1831 * Program cacheability overrides to not allocate cache 1832 * lines on a write miss 1833 */ 1834 a6xx_llc_rmw(a6xx_gpu, 1835 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1836 return; 1837 } 1838 1839 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1840 } 1841 1842 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1843 { 1844 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1845 struct msm_gpu *gpu = &adreno_gpu->base; 1846 1847 if (IS_ERR(a6xx_gpu->llc_mmio)) 1848 return; 1849 1850 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1851 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1852 1853 gpu_scid &= GENMASK(4, 0); 1854 1855 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 1856 FIELD_PREP(GENMASK(29, 25), gpu_scid) | 1857 FIELD_PREP(GENMASK(24, 20), gpu_scid) | 1858 FIELD_PREP(GENMASK(19, 15), gpu_scid) | 1859 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1860 FIELD_PREP(GENMASK(9, 5), gpu_scid) | 1861 FIELD_PREP(GENMASK(4, 0), gpu_scid)); 1862 1863 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 1864 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1865 BIT(8)); 1866 } 1867 1868 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 1869 } 1870 1871 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1872 { 1873 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1874 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1875 return; 1876 1877 llcc_slice_putd(a6xx_gpu->llc_slice); 1878 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1879 } 1880 1881 static void a6xx_llc_slices_init(struct platform_device *pdev, 1882 struct a6xx_gpu *a6xx_gpu, bool is_a7xx) 1883 { 1884 struct device_node *phandle; 1885 1886 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1887 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1888 return; 1889 1890 /* 1891 * There is a different programming path for A6xx targets with an 1892 * mmu500 attached, so detect if that is the case 1893 */ 1894 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1895 a6xx_gpu->have_mmu500 = (phandle && 1896 of_device_is_compatible(phandle, "arm,mmu-500")); 1897 of_node_put(phandle); 1898 1899 if (is_a7xx || !a6xx_gpu->have_mmu500) 1900 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); 1901 else 1902 a6xx_gpu->llc_mmio = NULL; 1903 1904 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1905 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1906 1907 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1908 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1909 } 1910 1911 static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) 1912 { 1913 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1914 struct msm_gpu *gpu = &adreno_gpu->base; 1915 u32 fuse_val; 1916 int ret; 1917 1918 if (adreno_is_a750(adreno_gpu)) { 1919 /* 1920 * Assume that if qcom scm isn't available, that whatever 1921 * replacement allows writing the fuse register ourselves. 1922 * Users of alternative firmware need to make sure this 1923 * register is writeable or indicate that it's not somehow. 1924 * Print a warning because if you mess this up you're about to 1925 * crash horribly. 1926 */ 1927 if (!qcom_scm_is_available()) { 1928 dev_warn_once(gpu->dev->dev, 1929 "SCM is not available, poking fuse register\n"); 1930 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, 1931 A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1932 A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | 1933 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); 1934 adreno_gpu->has_ray_tracing = true; 1935 return 0; 1936 } 1937 1938 ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | 1939 QCOM_SCM_GPU_TSENSE_EN_REQ); 1940 if (ret) 1941 return ret; 1942 1943 /* 1944 * On a750 raytracing may be disabled by the firmware, find out 1945 * whether that's the case. The scm call above sets the fuse 1946 * register. 1947 */ 1948 fuse_val = a6xx_llc_read(a6xx_gpu, 1949 REG_A7XX_CX_MISC_SW_FUSE_VALUE); 1950 adreno_gpu->has_ray_tracing = 1951 !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); 1952 } else if (adreno_is_a740(adreno_gpu)) { 1953 /* Raytracing is always enabled on a740 */ 1954 adreno_gpu->has_ray_tracing = true; 1955 } 1956 1957 return 0; 1958 } 1959 1960 1961 #define GBIF_CLIENT_HALT_MASK BIT(0) 1962 #define GBIF_ARB_HALT_MASK BIT(1) 1963 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 1964 #define VBIF_RESET_ACK_MASK 0xF0 1965 #define GPR0_GBIF_HALT_REQUEST 0x1E0 1966 1967 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 1968 { 1969 struct msm_gpu *gpu = &adreno_gpu->base; 1970 1971 if (adreno_is_a619_holi(adreno_gpu)) { 1972 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 1973 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 1974 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 1975 } else if (!a6xx_has_gbif(adreno_gpu)) { 1976 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 1977 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 1978 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 1979 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 1980 1981 return; 1982 } 1983 1984 if (gx_off) { 1985 /* Halt the gx side of GBIF */ 1986 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 1987 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 1988 } 1989 1990 /* Halt new client requests on GBIF */ 1991 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 1992 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1993 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 1994 1995 /* Halt all AXI requests on GBIF */ 1996 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 1997 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1998 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 1999 2000 /* The GBIF halt needs to be explicitly cleared */ 2001 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 2002 } 2003 2004 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 2005 { 2006 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 2007 if (adreno_is_a610(to_adreno_gpu(gpu))) 2008 return; 2009 2010 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 2011 /* Perform a bogus read and add a brief delay to ensure ordering. */ 2012 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 2013 udelay(1); 2014 2015 /* The reset line needs to be asserted for at least 100 us */ 2016 if (assert) 2017 udelay(100); 2018 } 2019 2020 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 2021 { 2022 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2023 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2024 int ret; 2025 2026 gpu->needs_hw_init = true; 2027 2028 trace_msm_gpu_resume(0); 2029 2030 mutex_lock(&a6xx_gpu->gmu.lock); 2031 ret = a6xx_gmu_resume(a6xx_gpu); 2032 mutex_unlock(&a6xx_gpu->gmu.lock); 2033 if (ret) 2034 return ret; 2035 2036 msm_devfreq_resume(gpu); 2037 2038 adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu); 2039 2040 return ret; 2041 } 2042 2043 static int a6xx_pm_resume(struct msm_gpu *gpu) 2044 { 2045 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2046 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2047 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2048 unsigned long freq = gpu->fast_rate; 2049 struct dev_pm_opp *opp; 2050 int ret; 2051 2052 gpu->needs_hw_init = true; 2053 2054 trace_msm_gpu_resume(0); 2055 2056 mutex_lock(&a6xx_gpu->gmu.lock); 2057 2058 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 2059 if (IS_ERR(opp)) { 2060 ret = PTR_ERR(opp); 2061 goto err_set_opp; 2062 } 2063 dev_pm_opp_put(opp); 2064 2065 /* Set the core clock and bus bw, having VDD scaling in mind */ 2066 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 2067 2068 pm_runtime_resume_and_get(gmu->dev); 2069 pm_runtime_resume_and_get(gmu->gxpd); 2070 2071 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 2072 if (ret) 2073 goto err_bulk_clk; 2074 2075 if (adreno_is_a619_holi(adreno_gpu)) 2076 a6xx_sptprac_enable(gmu); 2077 2078 /* If anything goes south, tear the GPU down piece by piece.. */ 2079 if (ret) { 2080 err_bulk_clk: 2081 pm_runtime_put(gmu->gxpd); 2082 pm_runtime_put(gmu->dev); 2083 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2084 } 2085 err_set_opp: 2086 mutex_unlock(&a6xx_gpu->gmu.lock); 2087 2088 if (!ret) 2089 msm_devfreq_resume(gpu); 2090 2091 return ret; 2092 } 2093 2094 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 2095 { 2096 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2097 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2098 int i, ret; 2099 2100 trace_msm_gpu_suspend(0); 2101 2102 a6xx_llc_deactivate(a6xx_gpu); 2103 2104 msm_devfreq_suspend(gpu); 2105 2106 mutex_lock(&a6xx_gpu->gmu.lock); 2107 ret = a6xx_gmu_stop(a6xx_gpu); 2108 mutex_unlock(&a6xx_gpu->gmu.lock); 2109 if (ret) 2110 return ret; 2111 2112 if (a6xx_gpu->shadow_bo) 2113 for (i = 0; i < gpu->nr_rings; i++) 2114 a6xx_gpu->shadow[i] = 0; 2115 2116 gpu->suspend_count++; 2117 2118 return 0; 2119 } 2120 2121 static int a6xx_pm_suspend(struct msm_gpu *gpu) 2122 { 2123 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2124 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2125 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2126 int i; 2127 2128 trace_msm_gpu_suspend(0); 2129 2130 msm_devfreq_suspend(gpu); 2131 2132 mutex_lock(&a6xx_gpu->gmu.lock); 2133 2134 /* Drain the outstanding traffic on memory buses */ 2135 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 2136 2137 if (adreno_is_a619_holi(adreno_gpu)) 2138 a6xx_sptprac_disable(gmu); 2139 2140 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2141 2142 pm_runtime_put_sync(gmu->gxpd); 2143 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2144 pm_runtime_put_sync(gmu->dev); 2145 2146 mutex_unlock(&a6xx_gpu->gmu.lock); 2147 2148 if (a6xx_gpu->shadow_bo) 2149 for (i = 0; i < gpu->nr_rings; i++) 2150 a6xx_gpu->shadow[i] = 0; 2151 2152 gpu->suspend_count++; 2153 2154 return 0; 2155 } 2156 2157 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2158 { 2159 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2160 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2161 2162 mutex_lock(&a6xx_gpu->gmu.lock); 2163 2164 /* Force the GPU power on so we can read this register */ 2165 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2166 2167 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2168 2169 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2170 2171 mutex_unlock(&a6xx_gpu->gmu.lock); 2172 2173 return 0; 2174 } 2175 2176 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2177 { 2178 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2179 return 0; 2180 } 2181 2182 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 2183 { 2184 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2185 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2186 2187 return a6xx_gpu->cur_ring; 2188 } 2189 2190 static void a6xx_destroy(struct msm_gpu *gpu) 2191 { 2192 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2193 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2194 2195 if (a6xx_gpu->sqe_bo) { 2196 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 2197 drm_gem_object_put(a6xx_gpu->sqe_bo); 2198 } 2199 2200 if (a6xx_gpu->shadow_bo) { 2201 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 2202 drm_gem_object_put(a6xx_gpu->shadow_bo); 2203 } 2204 2205 a6xx_llc_slices_destroy(a6xx_gpu); 2206 2207 a6xx_gmu_remove(a6xx_gpu); 2208 2209 adreno_gpu_cleanup(adreno_gpu); 2210 2211 kfree(a6xx_gpu); 2212 } 2213 2214 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2215 { 2216 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2217 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2218 u64 busy_cycles; 2219 2220 /* 19.2MHz */ 2221 *out_sample_rate = 19200000; 2222 2223 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2224 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2225 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2226 2227 return busy_cycles; 2228 } 2229 2230 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2231 bool suspended) 2232 { 2233 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2234 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2235 2236 mutex_lock(&a6xx_gpu->gmu.lock); 2237 a6xx_gmu_set_freq(gpu, opp, suspended); 2238 mutex_unlock(&a6xx_gpu->gmu.lock); 2239 } 2240 2241 static struct msm_gem_address_space * 2242 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 2243 { 2244 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2245 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2246 unsigned long quirks = 0; 2247 2248 /* 2249 * This allows GPU to set the bus attributes required to use system 2250 * cache on behalf of the iommu page table walker. 2251 */ 2252 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2253 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2254 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2255 2256 return adreno_iommu_create_address_space(gpu, pdev, quirks); 2257 } 2258 2259 static struct msm_gem_address_space * 2260 a6xx_create_private_address_space(struct msm_gpu *gpu) 2261 { 2262 struct msm_mmu *mmu; 2263 2264 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 2265 2266 if (IS_ERR(mmu)) 2267 return ERR_CAST(mmu); 2268 2269 return msm_gem_address_space_create(mmu, 2270 "gpu", ADRENO_VM_START, 2271 adreno_private_address_space_size(gpu)); 2272 } 2273 2274 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2275 { 2276 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2277 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2278 2279 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2280 return a6xx_gpu->shadow[ring->id]; 2281 2282 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2283 } 2284 2285 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2286 { 2287 struct msm_cp_state cp_state = { 2288 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2289 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2290 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2291 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2292 }; 2293 bool progress; 2294 2295 /* 2296 * Adjust the remaining data to account for what has already been 2297 * fetched from memory, but not yet consumed by the SQE. 2298 * 2299 * This is not *technically* correct, the amount buffered could 2300 * exceed the IB size due to hw prefetching ahead, but: 2301 * 2302 * (1) We aren't trying to find the exact position, just whether 2303 * progress has been made 2304 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2305 * to prevent prefetching into an unrelated submit. (And 2306 * either way, at some point the ROQ will be full.) 2307 */ 2308 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2309 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2310 2311 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2312 2313 ring->last_cp_state = cp_state; 2314 2315 return progress; 2316 } 2317 2318 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) 2319 { 2320 if (!info->speedbins) 2321 return UINT_MAX; 2322 2323 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) 2324 if (info->speedbins[i].fuse == fuse) 2325 return BIT(info->speedbins[i].speedbin); 2326 2327 return UINT_MAX; 2328 } 2329 2330 static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) 2331 { 2332 u32 supp_hw; 2333 u32 speedbin; 2334 int ret; 2335 2336 ret = adreno_read_speedbin(dev, &speedbin); 2337 /* 2338 * -ENOENT means that the platform doesn't support speedbin which is 2339 * fine 2340 */ 2341 if (ret == -ENOENT) { 2342 return 0; 2343 } else if (ret) { 2344 dev_err_probe(dev, ret, 2345 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2346 return ret; 2347 } 2348 2349 supp_hw = fuse_to_supp_hw(info, speedbin); 2350 2351 if (supp_hw == UINT_MAX) { 2352 DRM_DEV_ERROR(dev, 2353 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2354 speedbin); 2355 supp_hw = BIT(0); /* Default */ 2356 } 2357 2358 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2359 if (ret) 2360 return ret; 2361 2362 return 0; 2363 } 2364 2365 static const struct adreno_gpu_funcs funcs = { 2366 .base = { 2367 .get_param = adreno_get_param, 2368 .set_param = adreno_set_param, 2369 .hw_init = a6xx_hw_init, 2370 .ucode_load = a6xx_ucode_load, 2371 .pm_suspend = a6xx_gmu_pm_suspend, 2372 .pm_resume = a6xx_gmu_pm_resume, 2373 .recover = a6xx_recover, 2374 .submit = a6xx_submit, 2375 .active_ring = a6xx_active_ring, 2376 .irq = a6xx_irq, 2377 .destroy = a6xx_destroy, 2378 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2379 .show = a6xx_show, 2380 #endif 2381 .gpu_busy = a6xx_gpu_busy, 2382 .gpu_get_freq = a6xx_gmu_get_freq, 2383 .gpu_set_freq = a6xx_gpu_set_freq, 2384 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2385 .gpu_state_get = a6xx_gpu_state_get, 2386 .gpu_state_put = a6xx_gpu_state_put, 2387 #endif 2388 .create_address_space = a6xx_create_address_space, 2389 .create_private_address_space = a6xx_create_private_address_space, 2390 .get_rptr = a6xx_get_rptr, 2391 .progress = a6xx_progress, 2392 }, 2393 .get_timestamp = a6xx_gmu_get_timestamp, 2394 }; 2395 2396 static const struct adreno_gpu_funcs funcs_gmuwrapper = { 2397 .base = { 2398 .get_param = adreno_get_param, 2399 .set_param = adreno_set_param, 2400 .hw_init = a6xx_hw_init, 2401 .ucode_load = a6xx_ucode_load, 2402 .pm_suspend = a6xx_pm_suspend, 2403 .pm_resume = a6xx_pm_resume, 2404 .recover = a6xx_recover, 2405 .submit = a6xx_submit, 2406 .active_ring = a6xx_active_ring, 2407 .irq = a6xx_irq, 2408 .destroy = a6xx_destroy, 2409 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2410 .show = a6xx_show, 2411 #endif 2412 .gpu_busy = a6xx_gpu_busy, 2413 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2414 .gpu_state_get = a6xx_gpu_state_get, 2415 .gpu_state_put = a6xx_gpu_state_put, 2416 #endif 2417 .create_address_space = a6xx_create_address_space, 2418 .create_private_address_space = a6xx_create_private_address_space, 2419 .get_rptr = a6xx_get_rptr, 2420 .progress = a6xx_progress, 2421 }, 2422 .get_timestamp = a6xx_get_timestamp, 2423 }; 2424 2425 static const struct adreno_gpu_funcs funcs_a7xx = { 2426 .base = { 2427 .get_param = adreno_get_param, 2428 .set_param = adreno_set_param, 2429 .hw_init = a6xx_hw_init, 2430 .ucode_load = a6xx_ucode_load, 2431 .pm_suspend = a6xx_gmu_pm_suspend, 2432 .pm_resume = a6xx_gmu_pm_resume, 2433 .recover = a6xx_recover, 2434 .submit = a7xx_submit, 2435 .active_ring = a6xx_active_ring, 2436 .irq = a6xx_irq, 2437 .destroy = a6xx_destroy, 2438 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2439 .show = a6xx_show, 2440 #endif 2441 .gpu_busy = a6xx_gpu_busy, 2442 .gpu_get_freq = a6xx_gmu_get_freq, 2443 .gpu_set_freq = a6xx_gpu_set_freq, 2444 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2445 .gpu_state_get = a6xx_gpu_state_get, 2446 .gpu_state_put = a6xx_gpu_state_put, 2447 #endif 2448 .create_address_space = a6xx_create_address_space, 2449 .create_private_address_space = a6xx_create_private_address_space, 2450 .get_rptr = a6xx_get_rptr, 2451 .progress = a6xx_progress, 2452 }, 2453 .get_timestamp = a6xx_gmu_get_timestamp, 2454 }; 2455 2456 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2457 { 2458 struct msm_drm_private *priv = dev->dev_private; 2459 struct platform_device *pdev = priv->gpu_pdev; 2460 struct adreno_platform_config *config = pdev->dev.platform_data; 2461 struct device_node *node; 2462 struct a6xx_gpu *a6xx_gpu; 2463 struct adreno_gpu *adreno_gpu; 2464 struct msm_gpu *gpu; 2465 extern int enable_preemption; 2466 bool is_a7xx; 2467 int ret; 2468 2469 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 2470 if (!a6xx_gpu) 2471 return ERR_PTR(-ENOMEM); 2472 2473 adreno_gpu = &a6xx_gpu->base; 2474 gpu = &adreno_gpu->base; 2475 2476 mutex_init(&a6xx_gpu->gmu.lock); 2477 2478 adreno_gpu->registers = NULL; 2479 2480 /* Check if there is a GMU phandle and set it up */ 2481 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2482 /* FIXME: How do we gracefully handle this? */ 2483 BUG_ON(!node); 2484 2485 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2486 2487 adreno_gpu->base.hw_apriv = 2488 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); 2489 2490 /* gpu->info only gets assigned in adreno_gpu_init() */ 2491 is_a7xx = config->info->family == ADRENO_7XX_GEN1 || 2492 config->info->family == ADRENO_7XX_GEN2 || 2493 config->info->family == ADRENO_7XX_GEN3; 2494 2495 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); 2496 2497 ret = a6xx_set_supported_hw(&pdev->dev, config->info); 2498 if (ret) { 2499 a6xx_llc_slices_destroy(a6xx_gpu); 2500 kfree(a6xx_gpu); 2501 return ERR_PTR(ret); 2502 } 2503 2504 if ((enable_preemption == 1) || (enable_preemption == -1 && 2505 (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) 2506 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); 2507 else if (is_a7xx) 2508 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); 2509 else if (adreno_has_gmu_wrapper(adreno_gpu)) 2510 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); 2511 else 2512 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 2513 if (ret) { 2514 a6xx_destroy(&(a6xx_gpu->base.base)); 2515 return ERR_PTR(ret); 2516 } 2517 2518 /* 2519 * For now only clamp to idle freq for devices where this is known not 2520 * to cause power supply issues: 2521 */ 2522 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2523 priv->gpu_clamp_to_idle = true; 2524 2525 if (adreno_has_gmu_wrapper(adreno_gpu)) 2526 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2527 else 2528 ret = a6xx_gmu_init(a6xx_gpu, node); 2529 of_node_put(node); 2530 if (ret) { 2531 a6xx_destroy(&(a6xx_gpu->base.base)); 2532 return ERR_PTR(ret); 2533 } 2534 2535 if (adreno_is_a7xx(adreno_gpu)) { 2536 ret = a7xx_cx_mem_init(a6xx_gpu); 2537 if (ret) { 2538 a6xx_destroy(&(a6xx_gpu->base.base)); 2539 return ERR_PTR(ret); 2540 } 2541 } 2542 2543 adreno_gpu->uche_trap_base = 0x1fffffffff000ull; 2544 2545 if (gpu->aspace) 2546 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 2547 a6xx_fault_handler); 2548 2549 a6xx_calc_ubwc_config(adreno_gpu); 2550 /* Set up the preemption specific bits and pieces for each ringbuffer */ 2551 a6xx_preempt_init(gpu); 2552 2553 return gpu; 2554 } 2555