1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/firmware/qcom/qcom_scm.h> 14 #include <linux/pm_domain.h> 15 #include <linux/soc/qcom/llcc-qcom.h> 16 17 #define GPU_PAS_ID 13 18 19 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 20 { 21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 23 24 /* Check that the GMU is idle */ 25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 26 return false; 27 28 /* Check tha the CX master is idle */ 29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 30 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 31 return false; 32 33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 34 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 35 } 36 37 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 38 { 39 /* wait for CP to drain ringbuffer: */ 40 if (!adreno_idle(gpu, ring)) 41 return false; 42 43 if (spin_until(_a6xx_check_idle(gpu))) { 44 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 45 gpu->name, __builtin_return_address(0), 46 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 48 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 49 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 50 return false; 51 } 52 53 return true; 54 } 55 56 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 57 { 58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 59 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 60 61 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 63 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 66 } 67 } 68 69 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 70 { 71 uint32_t wptr; 72 unsigned long flags; 73 74 update_shadow_rptr(gpu, ring); 75 76 spin_lock_irqsave(&ring->preempt_lock, flags); 77 78 /* Copy the shadow to the actual register */ 79 ring->cur = ring->next; 80 81 /* Make sure to wrap wptr if we need to */ 82 wptr = get_wptr(ring); 83 84 spin_unlock_irqrestore(&ring->preempt_lock, flags); 85 86 /* Make sure everything is posted before making a decision */ 87 mb(); 88 89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 90 } 91 92 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 93 u64 iova) 94 { 95 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 96 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 97 CP_REG_TO_MEM_0_CNT(2) | 98 CP_REG_TO_MEM_0_64B); 99 OUT_RING(ring, lower_32_bits(iova)); 100 OUT_RING(ring, upper_32_bits(iova)); 101 } 102 103 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 104 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 105 { 106 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; 107 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 108 phys_addr_t ttbr; 109 u32 asid; 110 u64 memptr = rbmemptr(ring, ttbr0); 111 112 if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno) 113 return; 114 115 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 116 return; 117 118 if (!sysprof) { 119 if (!adreno_is_a7xx(adreno_gpu)) { 120 /* Turn off protected mode to write to special registers */ 121 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 122 OUT_RING(ring, 0); 123 } 124 125 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 126 OUT_RING(ring, 1); 127 } 128 129 /* Execute the table update */ 130 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 131 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 132 133 OUT_RING(ring, 134 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 135 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 136 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 137 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 138 139 /* 140 * Write the new TTBR0 to the memstore. This is good for debugging. 141 */ 142 OUT_PKT7(ring, CP_MEM_WRITE, 4); 143 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 144 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 145 OUT_RING(ring, lower_32_bits(ttbr)); 146 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); 147 148 /* 149 * Sync both threads after switching pagetables and enable BR only 150 * to make sure BV doesn't race ahead while BR is still switching 151 * pagetables. 152 */ 153 if (adreno_is_a7xx(&a6xx_gpu->base)) { 154 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 155 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 156 } 157 158 /* 159 * And finally, trigger a uche flush to be sure there isn't anything 160 * lingering in that part of the GPU 161 */ 162 163 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 164 OUT_RING(ring, CACHE_INVALIDATE); 165 166 if (!sysprof) { 167 /* 168 * Wait for SRAM clear after the pgtable update, so the 169 * two can happen in parallel: 170 */ 171 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 172 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 173 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 174 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 175 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 176 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 177 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 178 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 179 180 if (!adreno_is_a7xx(adreno_gpu)) { 181 /* Re-enable protected mode: */ 182 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 183 OUT_RING(ring, 1); 184 } 185 } 186 } 187 188 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 189 { 190 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 191 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 192 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 193 struct msm_ringbuffer *ring = submit->ring; 194 unsigned int i, ibs = 0; 195 196 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 197 198 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 199 rbmemptr_stats(ring, index, cpcycles_start)); 200 201 /* 202 * For PM4 the GMU register offsets are calculated from the base of the 203 * GPU registers so we need to add 0x1a800 to the register value on A630 204 * to get the right value from PM4. 205 */ 206 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 207 rbmemptr_stats(ring, index, alwayson_start)); 208 209 /* Invalidate CCU depth and color */ 210 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 211 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 212 213 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 214 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 215 216 /* Submit the commands */ 217 for (i = 0; i < submit->nr_cmds; i++) { 218 switch (submit->cmd[i].type) { 219 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 220 break; 221 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 222 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) 223 break; 224 fallthrough; 225 case MSM_SUBMIT_CMD_BUF: 226 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 227 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 228 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 229 OUT_RING(ring, submit->cmd[i].size); 230 ibs++; 231 break; 232 } 233 234 /* 235 * Periodically update shadow-wptr if needed, so that we 236 * can see partial progress of submits with large # of 237 * cmds.. otherwise we could needlessly stall waiting for 238 * ringbuffer state, simply due to looking at a shadow 239 * rptr value that has not been updated 240 */ 241 if ((ibs % 32) == 0) 242 update_shadow_rptr(gpu, ring); 243 } 244 245 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 246 rbmemptr_stats(ring, index, cpcycles_end)); 247 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 248 rbmemptr_stats(ring, index, alwayson_end)); 249 250 /* Write the fence to the scratch register */ 251 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 252 OUT_RING(ring, submit->seqno); 253 254 /* 255 * Execute a CACHE_FLUSH_TS event. This will ensure that the 256 * timestamp is written to the memory and then triggers the interrupt 257 */ 258 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 259 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 260 CP_EVENT_WRITE_0_IRQ); 261 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 262 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 263 OUT_RING(ring, submit->seqno); 264 265 trace_msm_gpu_submit_flush(submit, 266 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 267 268 a6xx_flush(gpu, ring); 269 } 270 271 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 272 { 273 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 274 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 275 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 276 struct msm_ringbuffer *ring = submit->ring; 277 unsigned int i, ibs = 0; 278 279 /* 280 * Toggle concurrent binning for pagetable switch and set the thread to 281 * BR since only it can execute the pagetable switch packets. 282 */ 283 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 284 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 285 286 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 287 288 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 289 rbmemptr_stats(ring, index, cpcycles_start)); 290 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 291 rbmemptr_stats(ring, index, alwayson_start)); 292 293 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 294 OUT_RING(ring, CP_SET_THREAD_BOTH); 295 296 OUT_PKT7(ring, CP_SET_MARKER, 1); 297 OUT_RING(ring, 0x101); /* IFPC disable */ 298 299 OUT_PKT7(ring, CP_SET_MARKER, 1); 300 OUT_RING(ring, 0x00d); /* IB1LIST start */ 301 302 /* Submit the commands */ 303 for (i = 0; i < submit->nr_cmds; i++) { 304 switch (submit->cmd[i].type) { 305 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 306 break; 307 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 308 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) 309 break; 310 fallthrough; 311 case MSM_SUBMIT_CMD_BUF: 312 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 313 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 314 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 315 OUT_RING(ring, submit->cmd[i].size); 316 ibs++; 317 break; 318 } 319 320 /* 321 * Periodically update shadow-wptr if needed, so that we 322 * can see partial progress of submits with large # of 323 * cmds.. otherwise we could needlessly stall waiting for 324 * ringbuffer state, simply due to looking at a shadow 325 * rptr value that has not been updated 326 */ 327 if ((ibs % 32) == 0) 328 update_shadow_rptr(gpu, ring); 329 } 330 331 OUT_PKT7(ring, CP_SET_MARKER, 1); 332 OUT_RING(ring, 0x00e); /* IB1LIST end */ 333 334 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 335 rbmemptr_stats(ring, index, cpcycles_end)); 336 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 337 rbmemptr_stats(ring, index, alwayson_end)); 338 339 /* Write the fence to the scratch register */ 340 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 341 OUT_RING(ring, submit->seqno); 342 343 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 344 OUT_RING(ring, CP_SET_THREAD_BR); 345 346 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 347 OUT_RING(ring, CCU_INVALIDATE_DEPTH); 348 349 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 350 OUT_RING(ring, CCU_INVALIDATE_COLOR); 351 352 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 353 OUT_RING(ring, CP_SET_THREAD_BV); 354 355 /* 356 * Make sure the timestamp is committed once BV pipe is 357 * completely done with this submission. 358 */ 359 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 360 OUT_RING(ring, CACHE_CLEAN | BIT(27)); 361 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 362 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 363 OUT_RING(ring, submit->seqno); 364 365 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 366 OUT_RING(ring, CP_SET_THREAD_BR); 367 368 /* 369 * This makes sure that BR doesn't race ahead and commit 370 * timestamp to memstore while BV is still processing 371 * this submission. 372 */ 373 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 374 OUT_RING(ring, 0); 375 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 376 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 377 OUT_RING(ring, submit->seqno); 378 379 /* write the ringbuffer timestamp */ 380 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 381 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); 382 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 383 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 384 OUT_RING(ring, submit->seqno); 385 386 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 387 OUT_RING(ring, CP_SET_THREAD_BOTH); 388 389 OUT_PKT7(ring, CP_SET_MARKER, 1); 390 OUT_RING(ring, 0x100); /* IFPC enable */ 391 392 trace_msm_gpu_submit_flush(submit, 393 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 394 395 a6xx_flush(gpu, ring); 396 } 397 398 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 399 { 400 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 401 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 402 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 403 const struct adreno_reglist *reg; 404 unsigned int i; 405 u32 val, clock_cntl_on, cgc_mode; 406 407 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 408 return; 409 410 if (adreno_is_a630(adreno_gpu)) 411 clock_cntl_on = 0x8aa8aa02; 412 else if (adreno_is_a610(adreno_gpu)) 413 clock_cntl_on = 0xaaa8aa82; 414 else if (adreno_is_a702(adreno_gpu)) 415 clock_cntl_on = 0xaaaaaa82; 416 else 417 clock_cntl_on = 0x8aa8aa82; 418 419 if (adreno_is_a7xx(adreno_gpu)) { 420 cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000; 421 422 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 423 state ? cgc_mode : 0); 424 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 425 state ? 0x10111 : 0); 426 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 427 state ? 0x5555 : 0); 428 } 429 430 if (!adreno_gpu->info->a6xx->hwcg) { 431 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 432 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); 433 434 if (state) { 435 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); 436 437 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, 438 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 439 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 440 return; 441 } 442 443 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 444 } 445 446 return; 447 } 448 449 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 450 451 /* Don't re-program the registers if they are already correct */ 452 if ((!state && !val) || (state && (val == clock_cntl_on))) 453 return; 454 455 /* Disable SP clock before programming HWCG registers */ 456 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 457 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 458 459 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) 460 gpu_write(gpu, reg->offset, state ? reg->value : 0); 461 462 /* Enable SP clock */ 463 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 464 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 465 466 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 467 } 468 469 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 470 { 471 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 472 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 473 unsigned i; 474 475 /* 476 * Enable access protection to privileged registers, fault on an access 477 * protect violation and select the last span to protect from the start 478 * address all the way to the end of the register address space 479 */ 480 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 481 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | 482 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | 483 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); 484 485 for (i = 0; i < protect->count - 1; i++) { 486 /* Intentionally skip writing to some registers */ 487 if (protect->regs[i]) 488 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); 489 } 490 /* last CP_PROTECT to have "infinite" length on the last entry */ 491 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); 492 } 493 494 static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 495 { 496 /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ 497 gpu->ubwc_config.rgb565_predicator = 0; 498 /* Unknown, introduced with A650 family */ 499 gpu->ubwc_config.uavflagprd_inv = 0; 500 /* Whether the minimum access length is 64 bits */ 501 gpu->ubwc_config.min_acc_len = 0; 502 /* Entirely magic, per-GPU-gen value */ 503 gpu->ubwc_config.ubwc_mode = 0; 504 /* 505 * The Highest Bank Bit value represents the bit of the highest DDR bank. 506 * This should ideally use DRAM type detection. 507 */ 508 gpu->ubwc_config.highest_bank_bit = 15; 509 510 if (adreno_is_a610(gpu)) { 511 gpu->ubwc_config.highest_bank_bit = 13; 512 gpu->ubwc_config.min_acc_len = 1; 513 gpu->ubwc_config.ubwc_mode = 1; 514 } 515 516 if (adreno_is_a618(gpu)) 517 gpu->ubwc_config.highest_bank_bit = 14; 518 519 if (adreno_is_a619(gpu)) 520 /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ 521 gpu->ubwc_config.highest_bank_bit = 13; 522 523 if (adreno_is_a619_holi(gpu)) 524 gpu->ubwc_config.highest_bank_bit = 13; 525 526 if (adreno_is_a640_family(gpu)) 527 gpu->ubwc_config.amsbc = 1; 528 529 if (adreno_is_a650(gpu) || 530 adreno_is_a660(gpu) || 531 adreno_is_a690(gpu) || 532 adreno_is_a730(gpu) || 533 adreno_is_a740_family(gpu)) { 534 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 535 gpu->ubwc_config.highest_bank_bit = 16; 536 gpu->ubwc_config.amsbc = 1; 537 gpu->ubwc_config.rgb565_predicator = 1; 538 gpu->ubwc_config.uavflagprd_inv = 2; 539 } 540 541 if (adreno_is_7c3(gpu)) { 542 gpu->ubwc_config.highest_bank_bit = 14; 543 gpu->ubwc_config.amsbc = 1; 544 gpu->ubwc_config.rgb565_predicator = 1; 545 gpu->ubwc_config.uavflagprd_inv = 2; 546 } 547 548 if (adreno_is_a702(gpu)) { 549 gpu->ubwc_config.highest_bank_bit = 14; 550 gpu->ubwc_config.min_acc_len = 1; 551 gpu->ubwc_config.ubwc_mode = 0; 552 } 553 } 554 555 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 556 { 557 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 558 /* 559 * We subtract 13 from the highest bank bit (13 is the minimum value 560 * allowed by hw) and write the lowest two bits of the remaining value 561 * as hbb_lo and the one above it as hbb_hi to the hardware. 562 */ 563 BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); 564 u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; 565 u32 hbb_hi = hbb >> 2; 566 u32 hbb_lo = hbb & 3; 567 568 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 569 adreno_gpu->ubwc_config.rgb565_predicator << 11 | 570 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | 571 adreno_gpu->ubwc_config.min_acc_len << 3 | 572 hbb_lo << 1 | adreno_gpu->ubwc_config.ubwc_mode); 573 574 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | 575 adreno_gpu->ubwc_config.min_acc_len << 3 | 576 hbb_lo << 1 | adreno_gpu->ubwc_config.ubwc_mode); 577 578 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | 579 adreno_gpu->ubwc_config.uavflagprd_inv << 4 | 580 adreno_gpu->ubwc_config.min_acc_len << 3 | 581 hbb_lo << 1 | adreno_gpu->ubwc_config.ubwc_mode); 582 583 if (adreno_is_a7xx(adreno_gpu)) 584 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 585 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 586 587 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 588 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); 589 } 590 591 static int a6xx_cp_init(struct msm_gpu *gpu) 592 { 593 struct msm_ringbuffer *ring = gpu->rb[0]; 594 595 OUT_PKT7(ring, CP_ME_INIT, 8); 596 597 OUT_RING(ring, 0x0000002f); 598 599 /* Enable multiple hardware contexts */ 600 OUT_RING(ring, 0x00000003); 601 602 /* Enable error detection */ 603 OUT_RING(ring, 0x20000000); 604 605 /* Don't enable header dump */ 606 OUT_RING(ring, 0x00000000); 607 OUT_RING(ring, 0x00000000); 608 609 /* No workarounds enabled */ 610 OUT_RING(ring, 0x00000000); 611 612 /* Pad rest of the cmds with 0's */ 613 OUT_RING(ring, 0x00000000); 614 OUT_RING(ring, 0x00000000); 615 616 a6xx_flush(gpu, ring); 617 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 618 } 619 620 static int a7xx_cp_init(struct msm_gpu *gpu) 621 { 622 struct msm_ringbuffer *ring = gpu->rb[0]; 623 u32 mask; 624 625 /* Disable concurrent binning before sending CP init */ 626 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 627 OUT_RING(ring, BIT(27)); 628 629 OUT_PKT7(ring, CP_ME_INIT, 7); 630 631 /* Use multiple HW contexts */ 632 mask = BIT(0); 633 634 /* Enable error detection */ 635 mask |= BIT(1); 636 637 /* Set default reset state */ 638 mask |= BIT(3); 639 640 /* Disable save/restore of performance counters across preemption */ 641 mask |= BIT(6); 642 643 /* Enable the register init list with the spinlock */ 644 mask |= BIT(8); 645 646 OUT_RING(ring, mask); 647 648 /* Enable multiple hardware contexts */ 649 OUT_RING(ring, 0x00000003); 650 651 /* Enable error detection */ 652 OUT_RING(ring, 0x20000000); 653 654 /* Operation mode mask */ 655 OUT_RING(ring, 0x00000002); 656 657 /* *Don't* send a power up reg list for concurrent binning (TODO) */ 658 /* Lo address */ 659 OUT_RING(ring, 0x00000000); 660 /* Hi address */ 661 OUT_RING(ring, 0x00000000); 662 /* BIT(31) set => read the regs from the list */ 663 OUT_RING(ring, 0x00000000); 664 665 a6xx_flush(gpu, ring); 666 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 667 } 668 669 /* 670 * Check that the microcode version is new enough to include several key 671 * security fixes. Return true if the ucode is safe. 672 */ 673 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 674 struct drm_gem_object *obj) 675 { 676 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 677 struct msm_gpu *gpu = &adreno_gpu->base; 678 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 679 u32 *buf = msm_gem_get_vaddr(obj); 680 bool ret = false; 681 682 if (IS_ERR(buf)) 683 return false; 684 685 /* A7xx is safe! */ 686 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) 687 return true; 688 689 /* 690 * Targets up to a640 (a618, a630 and a640) need to check for a 691 * microcode version that is patched to support the whereami opcode or 692 * one that is new enough to include it by default. 693 * 694 * a650 tier targets don't need whereami but still need to be 695 * equal to or newer than 0.95 for other security fixes 696 * 697 * a660 targets have all the critical security fixes from the start 698 */ 699 if (!strcmp(sqe_name, "a630_sqe.fw")) { 700 /* 701 * If the lowest nibble is 0xa that is an indication that this 702 * microcode has been patched. The actual version is in dword 703 * [3] but we only care about the patchlevel which is the lowest 704 * nibble of dword [3] 705 * 706 * Otherwise check that the firmware is greater than or equal 707 * to 1.90 which was the first version that had this fix built 708 * in 709 */ 710 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 711 (buf[0] & 0xfff) >= 0x190) { 712 a6xx_gpu->has_whereami = true; 713 ret = true; 714 goto out; 715 } 716 717 DRM_DEV_ERROR(&gpu->pdev->dev, 718 "a630 SQE ucode is too old. Have version %x need at least %x\n", 719 buf[0] & 0xfff, 0x190); 720 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 721 if ((buf[0] & 0xfff) >= 0x095) { 722 ret = true; 723 goto out; 724 } 725 726 DRM_DEV_ERROR(&gpu->pdev->dev, 727 "a650 SQE ucode is too old. Have version %x need at least %x\n", 728 buf[0] & 0xfff, 0x095); 729 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 730 ret = true; 731 } else { 732 DRM_DEV_ERROR(&gpu->pdev->dev, 733 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 734 } 735 out: 736 msm_gem_put_vaddr(obj); 737 return ret; 738 } 739 740 static int a6xx_ucode_load(struct msm_gpu *gpu) 741 { 742 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 743 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 744 745 if (!a6xx_gpu->sqe_bo) { 746 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 747 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 748 749 if (IS_ERR(a6xx_gpu->sqe_bo)) { 750 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 751 752 a6xx_gpu->sqe_bo = NULL; 753 DRM_DEV_ERROR(&gpu->pdev->dev, 754 "Could not allocate SQE ucode: %d\n", ret); 755 756 return ret; 757 } 758 759 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 760 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 761 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 762 drm_gem_object_put(a6xx_gpu->sqe_bo); 763 764 a6xx_gpu->sqe_bo = NULL; 765 return -EPERM; 766 } 767 } 768 769 /* 770 * Expanded APRIV and targets that support WHERE_AM_I both need a 771 * privileged buffer to store the RPTR shadow 772 */ 773 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 774 !a6xx_gpu->shadow_bo) { 775 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 776 sizeof(u32) * gpu->nr_rings, 777 MSM_BO_WC | MSM_BO_MAP_PRIV, 778 gpu->aspace, &a6xx_gpu->shadow_bo, 779 &a6xx_gpu->shadow_iova); 780 781 if (IS_ERR(a6xx_gpu->shadow)) 782 return PTR_ERR(a6xx_gpu->shadow); 783 784 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 785 } 786 787 return 0; 788 } 789 790 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 791 { 792 static bool loaded; 793 int ret; 794 795 if (loaded) 796 return 0; 797 798 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 799 800 loaded = !ret; 801 return ret; 802 } 803 804 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 805 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 806 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 807 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 808 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 809 A6XX_RBBM_INT_0_MASK_CP_RB | \ 810 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 811 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 812 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 813 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 814 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 815 816 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 817 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 818 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 819 A6XX_RBBM_INT_0_MASK_CP_SW | \ 820 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 821 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 822 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 823 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 824 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 825 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 826 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 827 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 828 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 829 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 830 831 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ 832 A6XX_CP_APRIV_CNTL_RBFETCH | \ 833 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \ 834 A6XX_CP_APRIV_CNTL_RBRPWB) 835 836 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \ 837 A6XX_CP_APRIV_CNTL_CDREAD | \ 838 A6XX_CP_APRIV_CNTL_CDWRITE) 839 840 static int hw_init(struct msm_gpu *gpu) 841 { 842 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 843 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 844 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 845 u64 gmem_range_min; 846 int ret; 847 848 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 849 /* Make sure the GMU keeps the GPU on while we set it up */ 850 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 851 if (ret) 852 return ret; 853 } 854 855 /* Clear GBIF halt in case GX domain was not collapsed */ 856 if (adreno_is_a619_holi(adreno_gpu)) { 857 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 858 gpu_read(gpu, REG_A6XX_GBIF_HALT); 859 860 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 861 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); 862 } else if (a6xx_has_gbif(adreno_gpu)) { 863 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 864 gpu_read(gpu, REG_A6XX_GBIF_HALT); 865 866 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 867 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); 868 } 869 870 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 871 872 if (adreno_is_a619_holi(adreno_gpu)) 873 a6xx_sptprac_enable(gmu); 874 875 /* 876 * Disable the trusted memory range - we don't actually supported secure 877 * memory rendering at this point in time and we don't want to block off 878 * part of the virtual memory space. 879 */ 880 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 881 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 882 883 if (!adreno_is_a7xx(adreno_gpu)) { 884 /* Turn on 64 bit addressing for all blocks */ 885 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 886 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 887 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 888 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 889 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 890 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 891 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 892 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 893 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 894 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 895 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 896 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 897 } 898 899 /* enable hardware clockgating */ 900 a6xx_set_hwcg(gpu, true); 901 902 /* VBIF/GBIF start*/ 903 if (adreno_is_a610_family(adreno_gpu) || 904 adreno_is_a640_family(adreno_gpu) || 905 adreno_is_a650_family(adreno_gpu) || 906 adreno_is_a7xx(adreno_gpu)) { 907 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 908 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 909 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 910 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 911 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 912 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); 913 } else { 914 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 915 } 916 917 if (adreno_is_a630(adreno_gpu)) 918 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 919 920 if (adreno_is_a7xx(adreno_gpu)) 921 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); 922 923 /* Make all blocks contribute to the GPU BUSY perf counter */ 924 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 925 926 /* Disable L2 bypass in the UCHE */ 927 if (adreno_is_a7xx(adreno_gpu)) { 928 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 929 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 930 } else { 931 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); 932 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 933 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 934 } 935 936 if (!(adreno_is_a650_family(adreno_gpu) || 937 adreno_is_a702(adreno_gpu) || 938 adreno_is_a730(adreno_gpu))) { 939 gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; 940 941 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 942 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); 943 944 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 945 gmem_range_min + adreno_gpu->info->gmem - 1); 946 } 947 948 if (adreno_is_a7xx(adreno_gpu)) 949 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); 950 else { 951 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 952 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 953 } 954 955 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 956 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 957 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 958 } else if (adreno_is_a610_family(adreno_gpu)) { 959 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 960 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 961 } else if (!adreno_is_a7xx(adreno_gpu)) { 962 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 963 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 964 } 965 966 if (adreno_is_a660_family(adreno_gpu)) 967 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 968 969 /* Setting the mem pool size */ 970 if (adreno_is_a610(adreno_gpu)) { 971 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 972 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 973 } else if (adreno_is_a702(adreno_gpu)) { 974 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); 975 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); 976 } else if (!adreno_is_a7xx(adreno_gpu)) 977 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 978 979 /* Setting the primFifo thresholds default values, 980 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer 981 */ 982 if (adreno_is_a702(adreno_gpu)) 983 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000); 984 else if (adreno_is_a690(adreno_gpu)) 985 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200); 986 else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) 987 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); 988 else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 989 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); 990 else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) 991 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); 992 else if (adreno_is_a619(adreno_gpu)) 993 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); 994 else if (adreno_is_a610(adreno_gpu)) 995 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); 996 else if (!adreno_is_a7xx(adreno_gpu)) 997 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); 998 999 /* Set the AHB default slave response to "ERROR" */ 1000 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1001 1002 /* Turn on performance counters */ 1003 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1004 1005 if (adreno_is_a7xx(adreno_gpu)) { 1006 /* Turn on the IFPC counter (countable 4 on XOCLK4) */ 1007 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1008 FIELD_PREP(GENMASK(7, 0), 0x4)); 1009 } 1010 1011 /* Select CP0 to always count cycles */ 1012 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1013 1014 a6xx_set_ubwc_config(gpu); 1015 1016 /* Enable fault detection */ 1017 if (adreno_is_a730(adreno_gpu) || 1018 adreno_is_a740_family(adreno_gpu)) 1019 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); 1020 else if (adreno_is_a690(adreno_gpu)) 1021 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); 1022 else if (adreno_is_a619(adreno_gpu)) 1023 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1024 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 1025 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1026 else 1027 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1028 1029 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1030 1031 /* Set weights for bicubic filtering */ 1032 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1033 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1034 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1035 0x3fe05ff4); 1036 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1037 0x3fa0ebee); 1038 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1039 0x3f5193ed); 1040 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1041 0x3f0243f0); 1042 } 1043 1044 /* Set up the CX GMU counter 0 to count busy ticks */ 1045 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1046 1047 /* Enable the power counter */ 1048 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1049 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1050 1051 /* Protect registers from the CP */ 1052 a6xx_set_cp_protect(gpu); 1053 1054 if (adreno_is_a660_family(adreno_gpu)) { 1055 if (adreno_is_a690(adreno_gpu)) 1056 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); 1057 else 1058 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1059 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1060 } else if (adreno_is_a702(adreno_gpu)) { 1061 /* Something to do with the HLSQ cluster */ 1062 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); 1063 } 1064 1065 if (adreno_is_a690(adreno_gpu)) 1066 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); 1067 /* Set dualQ + disable afull for A660 GPU */ 1068 else if (adreno_is_a660(adreno_gpu)) 1069 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1070 else if (adreno_is_a7xx(adreno_gpu)) 1071 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 1072 FIELD_PREP(GENMASK(19, 16), 6) | 1073 FIELD_PREP(GENMASK(15, 12), 6) | 1074 FIELD_PREP(GENMASK(11, 8), 9) | 1075 BIT(3) | BIT(2) | 1076 FIELD_PREP(GENMASK(1, 0), 2)); 1077 1078 /* Enable expanded apriv for targets that support it */ 1079 if (gpu->hw_apriv) { 1080 if (adreno_is_a7xx(adreno_gpu)) { 1081 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1082 A7XX_BR_APRIVMASK); 1083 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, 1084 A7XX_APRIV_MASK); 1085 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, 1086 A7XX_APRIV_MASK); 1087 } else 1088 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1089 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); 1090 } 1091 1092 if (adreno_is_a750(adreno_gpu)) { 1093 /* Disable ubwc merged UFC request feature */ 1094 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); 1095 1096 /* Enable TP flaghint and other performance settings */ 1097 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); 1098 } else if (adreno_is_a7xx(adreno_gpu)) { 1099 /* Disable non-ubwc read reqs from passing write reqs */ 1100 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); 1101 } 1102 1103 /* Enable interrupts */ 1104 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 1105 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); 1106 1107 ret = adreno_hw_init(gpu); 1108 if (ret) 1109 goto out; 1110 1111 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1112 1113 /* Set the ringbuffer address */ 1114 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1115 1116 /* Targets that support extended APRIV can use the RPTR shadow from 1117 * hardware but all the other ones need to disable the feature. Targets 1118 * that support the WHERE_AM_I opcode can use that instead 1119 */ 1120 if (adreno_gpu->base.hw_apriv) 1121 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1122 else 1123 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1124 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1125 1126 /* Configure the RPTR shadow if needed: */ 1127 if (a6xx_gpu->shadow_bo) { 1128 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1129 shadowptr(a6xx_gpu, gpu->rb[0])); 1130 } 1131 1132 /* ..which means "always" on A7xx, also for BV shadow */ 1133 if (adreno_is_a7xx(adreno_gpu)) { 1134 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, 1135 rbmemptr(gpu->rb[0], bv_fence)); 1136 } 1137 1138 /* Always come up on rb 0 */ 1139 a6xx_gpu->cur_ring = gpu->rb[0]; 1140 1141 gpu->cur_ctx_seqno = 0; 1142 1143 /* Enable the SQE_to start the CP engine */ 1144 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1145 1146 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); 1147 if (ret) 1148 goto out; 1149 1150 /* 1151 * Try to load a zap shader into the secure world. If successful 1152 * we can use the CP to switch out of secure mode. If not then we 1153 * have no resource but to try to switch ourselves out manually. If we 1154 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1155 * be blocked and a permissions violation will soon follow. 1156 */ 1157 ret = a6xx_zap_shader_init(gpu); 1158 if (!ret) { 1159 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1160 OUT_RING(gpu->rb[0], 0x00000000); 1161 1162 a6xx_flush(gpu, gpu->rb[0]); 1163 if (!a6xx_idle(gpu, gpu->rb[0])) 1164 return -EINVAL; 1165 } else if (ret == -ENODEV) { 1166 /* 1167 * This device does not use zap shader (but print a warning 1168 * just in case someone got their dt wrong.. hopefully they 1169 * have a debug UART to realize the error of their ways... 1170 * if you mess this up you are about to crash horribly) 1171 */ 1172 dev_warn_once(gpu->dev->dev, 1173 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1174 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1175 ret = 0; 1176 } else { 1177 return ret; 1178 } 1179 1180 out: 1181 if (adreno_has_gmu_wrapper(adreno_gpu)) 1182 return ret; 1183 /* 1184 * Tell the GMU that we are done touching the GPU and it can start power 1185 * management 1186 */ 1187 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1188 1189 if (a6xx_gpu->gmu.legacy) { 1190 /* Take the GMU out of its special boot mode */ 1191 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1192 } 1193 1194 return ret; 1195 } 1196 1197 static int a6xx_hw_init(struct msm_gpu *gpu) 1198 { 1199 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1200 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1201 int ret; 1202 1203 mutex_lock(&a6xx_gpu->gmu.lock); 1204 ret = hw_init(gpu); 1205 mutex_unlock(&a6xx_gpu->gmu.lock); 1206 1207 return ret; 1208 } 1209 1210 static void a6xx_dump(struct msm_gpu *gpu) 1211 { 1212 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1213 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1214 adreno_dump(gpu); 1215 } 1216 1217 static void a6xx_recover(struct msm_gpu *gpu) 1218 { 1219 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1220 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1221 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1222 int i, active_submits; 1223 1224 adreno_dump_info(gpu); 1225 1226 for (i = 0; i < 8; i++) 1227 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1228 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1229 1230 if (hang_debug) 1231 a6xx_dump(gpu); 1232 1233 /* 1234 * To handle recovery specific sequences during the rpm suspend we are 1235 * about to trigger 1236 */ 1237 a6xx_gpu->hung = true; 1238 1239 /* Halt SQE first */ 1240 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1241 1242 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1243 1244 /* active_submit won't change until we make a submission */ 1245 mutex_lock(&gpu->active_lock); 1246 active_submits = gpu->active_submits; 1247 1248 /* 1249 * Temporarily clear active_submits count to silence a WARN() in the 1250 * runtime suspend cb 1251 */ 1252 gpu->active_submits = 0; 1253 1254 if (adreno_has_gmu_wrapper(adreno_gpu)) { 1255 /* Drain the outstanding traffic on memory buses */ 1256 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1257 1258 /* Reset the GPU to a clean state */ 1259 a6xx_gpu_sw_reset(gpu, true); 1260 a6xx_gpu_sw_reset(gpu, false); 1261 } 1262 1263 reinit_completion(&gmu->pd_gate); 1264 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1265 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1266 1267 /* Drop the rpm refcount from active submits */ 1268 if (active_submits) 1269 pm_runtime_put(&gpu->pdev->dev); 1270 1271 /* And the final one from recover worker */ 1272 pm_runtime_put_sync(&gpu->pdev->dev); 1273 1274 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1275 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1276 1277 dev_pm_genpd_remove_notifier(gmu->cxpd); 1278 1279 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1280 1281 if (active_submits) 1282 pm_runtime_get(&gpu->pdev->dev); 1283 1284 pm_runtime_get_sync(&gpu->pdev->dev); 1285 1286 gpu->active_submits = active_submits; 1287 mutex_unlock(&gpu->active_lock); 1288 1289 msm_gpu_hw_init(gpu); 1290 a6xx_gpu->hung = false; 1291 } 1292 1293 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1294 { 1295 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1296 static const char *uche_clients[7] = { 1297 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1298 }; 1299 u32 val; 1300 1301 if (adreno_is_a7xx(adreno_gpu)) { 1302 if (mid != 1 && mid != 2 && mid != 3 && mid != 8) 1303 return "UNKNOWN"; 1304 } else { 1305 if (mid < 1 || mid > 3) 1306 return "UNKNOWN"; 1307 } 1308 1309 /* 1310 * The source of the data depends on the mid ID read from FSYNR1. 1311 * and the client ID read from the UCHE block 1312 */ 1313 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1314 1315 if (adreno_is_a7xx(adreno_gpu)) { 1316 /* Bit 3 for mid=3 indicates BR or BV */ 1317 static const char *uche_clients_a7xx[16] = { 1318 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", 1319 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 1320 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", 1321 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 1322 }; 1323 1324 /* LPAC has the same clients as BR and BV, but because it is 1325 * compute-only some of them do not exist and there are holes 1326 * in the array. 1327 */ 1328 static const char *uche_clients_lpac_a7xx[8] = { 1329 "-", "LPAC_SP", "-", "-", 1330 "LPAC_HLSQ", "-", "-", "LPAC_TP", 1331 }; 1332 1333 val &= GENMASK(6, 0); 1334 1335 /* mid=3 refers to BR or BV */ 1336 if (mid == 3) { 1337 if (val < ARRAY_SIZE(uche_clients_a7xx)) 1338 return uche_clients_a7xx[val]; 1339 else 1340 return "UCHE"; 1341 } 1342 1343 /* mid=8 refers to LPAC */ 1344 if (mid == 8) { 1345 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) 1346 return uche_clients_lpac_a7xx[val]; 1347 else 1348 return "UCHE_LPAC"; 1349 } 1350 1351 /* mid=2 is a catchall for everything else in LPAC */ 1352 if (mid == 2) 1353 return "UCHE_LPAC"; 1354 1355 /* mid=1 is a catchall for everything else in BR/BV */ 1356 return "UCHE"; 1357 } else if (adreno_is_a660_family(adreno_gpu)) { 1358 static const char *uche_clients_a660[8] = { 1359 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", 1360 }; 1361 1362 static const char *uche_clients_a660_not[8] = { 1363 "not VFD", "not SP", "not VSC", "not VPC", 1364 "not HLSQ", "not PC", "not LRZ", "not TP", 1365 }; 1366 1367 val &= GENMASK(6, 0); 1368 1369 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) 1370 return uche_clients_a660[val]; 1371 1372 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) 1373 return uche_clients_a660_not[val]; 1374 1375 return "UCHE"; 1376 } else { 1377 /* mid = 3 is most precise and refers to only one block per client */ 1378 if (mid == 3) 1379 return uche_clients[val & 7]; 1380 1381 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1382 if (mid == 2) 1383 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1384 1385 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1386 return "UCHE"; 1387 } 1388 } 1389 1390 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1391 { 1392 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1393 1394 if (id == 0) 1395 return "CP"; 1396 else if (id == 4) 1397 return "CCU"; 1398 else if (id == 6) 1399 return "CDP Prefetch"; 1400 else if (id == 7) 1401 return "GMU"; 1402 else if (id == 5 && adreno_is_a7xx(adreno_gpu)) 1403 return "Flag cache"; 1404 1405 return a6xx_uche_fault_block(gpu, id); 1406 } 1407 1408 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1409 { 1410 struct msm_gpu *gpu = arg; 1411 struct adreno_smmu_fault_info *info = data; 1412 const char *block = "unknown"; 1413 1414 u32 scratch[] = { 1415 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1416 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1417 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1418 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1419 }; 1420 1421 if (info) 1422 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1423 1424 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1425 } 1426 1427 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1428 { 1429 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1430 1431 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1432 u32 val; 1433 1434 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1435 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1436 dev_err_ratelimited(&gpu->pdev->dev, 1437 "CP | opcode error | possible opcode=0x%8.8X\n", 1438 val); 1439 } 1440 1441 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1442 dev_err_ratelimited(&gpu->pdev->dev, 1443 "CP ucode error interrupt\n"); 1444 1445 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1446 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1447 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1448 1449 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1450 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1451 1452 dev_err_ratelimited(&gpu->pdev->dev, 1453 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1454 val & (1 << 20) ? "READ" : "WRITE", 1455 (val & 0x3ffff), val); 1456 } 1457 1458 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) 1459 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1460 1461 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1462 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1463 1464 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1465 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1466 1467 } 1468 1469 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1470 { 1471 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1472 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1473 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1474 1475 /* 1476 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1477 * but the fault handler will trigger the devcore dump, and we want 1478 * to otherwise resume normally rather than killing the submit, so 1479 * just bail. 1480 */ 1481 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1482 return; 1483 1484 /* 1485 * Force the GPU to stay on until after we finish 1486 * collecting information 1487 */ 1488 if (!adreno_has_gmu_wrapper(adreno_gpu)) 1489 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1490 1491 DRM_DEV_ERROR(&gpu->pdev->dev, 1492 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1493 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1494 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1495 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1496 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1497 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1498 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1499 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1500 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1501 1502 /* Turn off the hangcheck timer to keep it from bothering us */ 1503 del_timer(&gpu->hangcheck_timer); 1504 1505 kthread_queue_work(gpu->worker, &gpu->recover_work); 1506 } 1507 1508 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1509 { 1510 u32 status; 1511 1512 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); 1513 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); 1514 1515 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1516 1517 /* 1518 * Ignore FASTBLEND violations, because the HW will silently fall back 1519 * to legacy blending. 1520 */ 1521 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1522 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1523 del_timer(&gpu->hangcheck_timer); 1524 1525 kthread_queue_work(gpu->worker, &gpu->recover_work); 1526 } 1527 } 1528 1529 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1530 { 1531 struct msm_drm_private *priv = gpu->dev->dev_private; 1532 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1533 1534 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1535 1536 if (priv->disable_err_irq) 1537 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1538 1539 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1540 a6xx_fault_detect_irq(gpu); 1541 1542 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1543 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1544 1545 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1546 a6xx_cp_hw_err_irq(gpu); 1547 1548 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1549 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1550 1551 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1552 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1553 1554 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1555 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1556 1557 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1558 a7xx_sw_fuse_violation_irq(gpu); 1559 1560 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 1561 msm_gpu_retire(gpu); 1562 1563 return IRQ_HANDLED; 1564 } 1565 1566 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1567 { 1568 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1569 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1570 } 1571 1572 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1573 { 1574 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1575 struct msm_gpu *gpu = &adreno_gpu->base; 1576 u32 cntl1_regval = 0; 1577 1578 if (IS_ERR(a6xx_gpu->llc_mmio)) 1579 return; 1580 1581 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1582 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1583 1584 gpu_scid &= 0x1f; 1585 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1586 (gpu_scid << 15) | (gpu_scid << 20); 1587 1588 /* On A660, the SCID programming for UCHE traffic is done in 1589 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1590 */ 1591 if (adreno_is_a660_family(adreno_gpu)) 1592 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1593 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1594 } 1595 1596 /* 1597 * For targets with a MMU500, activate the slice but don't program the 1598 * register. The XBL will take care of that. 1599 */ 1600 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1601 if (!a6xx_gpu->have_mmu500) { 1602 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1603 1604 gpuhtw_scid &= 0x1f; 1605 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1606 } 1607 } 1608 1609 if (!cntl1_regval) 1610 return; 1611 1612 /* 1613 * Program the slice IDs for the various GPU blocks and GPU MMU 1614 * pagetables 1615 */ 1616 if (!a6xx_gpu->have_mmu500) { 1617 a6xx_llc_write(a6xx_gpu, 1618 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1619 1620 /* 1621 * Program cacheability overrides to not allocate cache 1622 * lines on a write miss 1623 */ 1624 a6xx_llc_rmw(a6xx_gpu, 1625 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1626 return; 1627 } 1628 1629 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1630 } 1631 1632 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1633 { 1634 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1635 struct msm_gpu *gpu = &adreno_gpu->base; 1636 1637 if (IS_ERR(a6xx_gpu->llc_mmio)) 1638 return; 1639 1640 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1641 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1642 1643 gpu_scid &= GENMASK(4, 0); 1644 1645 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 1646 FIELD_PREP(GENMASK(29, 25), gpu_scid) | 1647 FIELD_PREP(GENMASK(24, 20), gpu_scid) | 1648 FIELD_PREP(GENMASK(19, 15), gpu_scid) | 1649 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1650 FIELD_PREP(GENMASK(9, 5), gpu_scid) | 1651 FIELD_PREP(GENMASK(4, 0), gpu_scid)); 1652 1653 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 1654 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1655 BIT(8)); 1656 } 1657 1658 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 1659 } 1660 1661 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1662 { 1663 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1664 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1665 return; 1666 1667 llcc_slice_putd(a6xx_gpu->llc_slice); 1668 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1669 } 1670 1671 static void a6xx_llc_slices_init(struct platform_device *pdev, 1672 struct a6xx_gpu *a6xx_gpu, bool is_a7xx) 1673 { 1674 struct device_node *phandle; 1675 1676 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1677 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1678 return; 1679 1680 /* 1681 * There is a different programming path for A6xx targets with an 1682 * mmu500 attached, so detect if that is the case 1683 */ 1684 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1685 a6xx_gpu->have_mmu500 = (phandle && 1686 of_device_is_compatible(phandle, "arm,mmu-500")); 1687 of_node_put(phandle); 1688 1689 if (is_a7xx || !a6xx_gpu->have_mmu500) 1690 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); 1691 else 1692 a6xx_gpu->llc_mmio = NULL; 1693 1694 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1695 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1696 1697 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1698 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1699 } 1700 1701 static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) 1702 { 1703 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1704 struct msm_gpu *gpu = &adreno_gpu->base; 1705 u32 fuse_val; 1706 int ret; 1707 1708 if (adreno_is_a750(adreno_gpu)) { 1709 /* 1710 * Assume that if qcom scm isn't available, that whatever 1711 * replacement allows writing the fuse register ourselves. 1712 * Users of alternative firmware need to make sure this 1713 * register is writeable or indicate that it's not somehow. 1714 * Print a warning because if you mess this up you're about to 1715 * crash horribly. 1716 */ 1717 if (!qcom_scm_is_available()) { 1718 dev_warn_once(gpu->dev->dev, 1719 "SCM is not available, poking fuse register\n"); 1720 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, 1721 A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1722 A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | 1723 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); 1724 adreno_gpu->has_ray_tracing = true; 1725 return 0; 1726 } 1727 1728 ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | 1729 QCOM_SCM_GPU_TSENSE_EN_REQ); 1730 if (ret) 1731 return ret; 1732 1733 /* 1734 * On a750 raytracing may be disabled by the firmware, find out 1735 * whether that's the case. The scm call above sets the fuse 1736 * register. 1737 */ 1738 fuse_val = a6xx_llc_read(a6xx_gpu, 1739 REG_A7XX_CX_MISC_SW_FUSE_VALUE); 1740 adreno_gpu->has_ray_tracing = 1741 !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); 1742 } else if (adreno_is_a740(adreno_gpu)) { 1743 /* Raytracing is always enabled on a740 */ 1744 adreno_gpu->has_ray_tracing = true; 1745 } 1746 1747 return 0; 1748 } 1749 1750 1751 #define GBIF_CLIENT_HALT_MASK BIT(0) 1752 #define GBIF_ARB_HALT_MASK BIT(1) 1753 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 1754 #define VBIF_RESET_ACK_MASK 0xF0 1755 #define GPR0_GBIF_HALT_REQUEST 0x1E0 1756 1757 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 1758 { 1759 struct msm_gpu *gpu = &adreno_gpu->base; 1760 1761 if (adreno_is_a619_holi(adreno_gpu)) { 1762 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 1763 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 1764 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 1765 } else if (!a6xx_has_gbif(adreno_gpu)) { 1766 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 1767 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 1768 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 1769 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 1770 1771 return; 1772 } 1773 1774 if (gx_off) { 1775 /* Halt the gx side of GBIF */ 1776 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 1777 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 1778 } 1779 1780 /* Halt new client requests on GBIF */ 1781 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 1782 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1783 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 1784 1785 /* Halt all AXI requests on GBIF */ 1786 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 1787 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1788 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 1789 1790 /* The GBIF halt needs to be explicitly cleared */ 1791 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 1792 } 1793 1794 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 1795 { 1796 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 1797 if (adreno_is_a610(to_adreno_gpu(gpu))) 1798 return; 1799 1800 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 1801 /* Perform a bogus read and add a brief delay to ensure ordering. */ 1802 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 1803 udelay(1); 1804 1805 /* The reset line needs to be asserted for at least 100 us */ 1806 if (assert) 1807 udelay(100); 1808 } 1809 1810 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 1811 { 1812 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1813 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1814 int ret; 1815 1816 gpu->needs_hw_init = true; 1817 1818 trace_msm_gpu_resume(0); 1819 1820 mutex_lock(&a6xx_gpu->gmu.lock); 1821 ret = a6xx_gmu_resume(a6xx_gpu); 1822 mutex_unlock(&a6xx_gpu->gmu.lock); 1823 if (ret) 1824 return ret; 1825 1826 msm_devfreq_resume(gpu); 1827 1828 adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu); 1829 1830 return ret; 1831 } 1832 1833 static int a6xx_pm_resume(struct msm_gpu *gpu) 1834 { 1835 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1836 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1837 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1838 unsigned long freq = gpu->fast_rate; 1839 struct dev_pm_opp *opp; 1840 int ret; 1841 1842 gpu->needs_hw_init = true; 1843 1844 trace_msm_gpu_resume(0); 1845 1846 mutex_lock(&a6xx_gpu->gmu.lock); 1847 1848 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 1849 if (IS_ERR(opp)) { 1850 ret = PTR_ERR(opp); 1851 goto err_set_opp; 1852 } 1853 dev_pm_opp_put(opp); 1854 1855 /* Set the core clock and bus bw, having VDD scaling in mind */ 1856 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 1857 1858 pm_runtime_resume_and_get(gmu->dev); 1859 pm_runtime_resume_and_get(gmu->gxpd); 1860 1861 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 1862 if (ret) 1863 goto err_bulk_clk; 1864 1865 if (adreno_is_a619_holi(adreno_gpu)) 1866 a6xx_sptprac_enable(gmu); 1867 1868 /* If anything goes south, tear the GPU down piece by piece.. */ 1869 if (ret) { 1870 err_bulk_clk: 1871 pm_runtime_put(gmu->gxpd); 1872 pm_runtime_put(gmu->dev); 1873 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 1874 } 1875 err_set_opp: 1876 mutex_unlock(&a6xx_gpu->gmu.lock); 1877 1878 if (!ret) 1879 msm_devfreq_resume(gpu); 1880 1881 return ret; 1882 } 1883 1884 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 1885 { 1886 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1887 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1888 int i, ret; 1889 1890 trace_msm_gpu_suspend(0); 1891 1892 a6xx_llc_deactivate(a6xx_gpu); 1893 1894 msm_devfreq_suspend(gpu); 1895 1896 mutex_lock(&a6xx_gpu->gmu.lock); 1897 ret = a6xx_gmu_stop(a6xx_gpu); 1898 mutex_unlock(&a6xx_gpu->gmu.lock); 1899 if (ret) 1900 return ret; 1901 1902 if (a6xx_gpu->shadow_bo) 1903 for (i = 0; i < gpu->nr_rings; i++) 1904 a6xx_gpu->shadow[i] = 0; 1905 1906 gpu->suspend_count++; 1907 1908 return 0; 1909 } 1910 1911 static int a6xx_pm_suspend(struct msm_gpu *gpu) 1912 { 1913 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1914 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1915 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1916 int i; 1917 1918 trace_msm_gpu_suspend(0); 1919 1920 msm_devfreq_suspend(gpu); 1921 1922 mutex_lock(&a6xx_gpu->gmu.lock); 1923 1924 /* Drain the outstanding traffic on memory buses */ 1925 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1926 1927 if (adreno_is_a619_holi(adreno_gpu)) 1928 a6xx_sptprac_disable(gmu); 1929 1930 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 1931 1932 pm_runtime_put_sync(gmu->gxpd); 1933 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 1934 pm_runtime_put_sync(gmu->dev); 1935 1936 mutex_unlock(&a6xx_gpu->gmu.lock); 1937 1938 if (a6xx_gpu->shadow_bo) 1939 for (i = 0; i < gpu->nr_rings; i++) 1940 a6xx_gpu->shadow[i] = 0; 1941 1942 gpu->suspend_count++; 1943 1944 return 0; 1945 } 1946 1947 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1948 { 1949 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1950 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1951 1952 mutex_lock(&a6xx_gpu->gmu.lock); 1953 1954 /* Force the GPU power on so we can read this register */ 1955 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1956 1957 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 1958 1959 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1960 1961 mutex_unlock(&a6xx_gpu->gmu.lock); 1962 1963 return 0; 1964 } 1965 1966 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1967 { 1968 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 1969 return 0; 1970 } 1971 1972 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 1973 { 1974 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1975 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1976 1977 return a6xx_gpu->cur_ring; 1978 } 1979 1980 static void a6xx_destroy(struct msm_gpu *gpu) 1981 { 1982 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1983 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1984 1985 if (a6xx_gpu->sqe_bo) { 1986 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 1987 drm_gem_object_put(a6xx_gpu->sqe_bo); 1988 } 1989 1990 if (a6xx_gpu->shadow_bo) { 1991 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 1992 drm_gem_object_put(a6xx_gpu->shadow_bo); 1993 } 1994 1995 a6xx_llc_slices_destroy(a6xx_gpu); 1996 1997 a6xx_gmu_remove(a6xx_gpu); 1998 1999 adreno_gpu_cleanup(adreno_gpu); 2000 2001 kfree(a6xx_gpu); 2002 } 2003 2004 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2005 { 2006 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2007 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2008 u64 busy_cycles; 2009 2010 /* 19.2MHz */ 2011 *out_sample_rate = 19200000; 2012 2013 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2014 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2015 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2016 2017 return busy_cycles; 2018 } 2019 2020 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2021 bool suspended) 2022 { 2023 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2024 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2025 2026 mutex_lock(&a6xx_gpu->gmu.lock); 2027 a6xx_gmu_set_freq(gpu, opp, suspended); 2028 mutex_unlock(&a6xx_gpu->gmu.lock); 2029 } 2030 2031 static struct msm_gem_address_space * 2032 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 2033 { 2034 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2035 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2036 unsigned long quirks = 0; 2037 2038 /* 2039 * This allows GPU to set the bus attributes required to use system 2040 * cache on behalf of the iommu page table walker. 2041 */ 2042 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2043 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2044 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2045 2046 return adreno_iommu_create_address_space(gpu, pdev, quirks); 2047 } 2048 2049 static struct msm_gem_address_space * 2050 a6xx_create_private_address_space(struct msm_gpu *gpu) 2051 { 2052 struct msm_mmu *mmu; 2053 2054 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 2055 2056 if (IS_ERR(mmu)) 2057 return ERR_CAST(mmu); 2058 2059 return msm_gem_address_space_create(mmu, 2060 "gpu", 0x100000000ULL, 2061 adreno_private_address_space_size(gpu)); 2062 } 2063 2064 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2065 { 2066 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2067 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2068 2069 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2070 return a6xx_gpu->shadow[ring->id]; 2071 2072 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2073 } 2074 2075 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2076 { 2077 struct msm_cp_state cp_state = { 2078 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2079 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2080 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2081 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2082 }; 2083 bool progress; 2084 2085 /* 2086 * Adjust the remaining data to account for what has already been 2087 * fetched from memory, but not yet consumed by the SQE. 2088 * 2089 * This is not *technically* correct, the amount buffered could 2090 * exceed the IB size due to hw prefetching ahead, but: 2091 * 2092 * (1) We aren't trying to find the exact position, just whether 2093 * progress has been made 2094 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2095 * to prevent prefetching into an unrelated submit. (And 2096 * either way, at some point the ROQ will be full.) 2097 */ 2098 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2099 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2100 2101 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2102 2103 ring->last_cp_state = cp_state; 2104 2105 return progress; 2106 } 2107 2108 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) 2109 { 2110 if (!info->speedbins) 2111 return UINT_MAX; 2112 2113 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) 2114 if (info->speedbins[i].fuse == fuse) 2115 return BIT(info->speedbins[i].speedbin); 2116 2117 return UINT_MAX; 2118 } 2119 2120 static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) 2121 { 2122 u32 supp_hw; 2123 u32 speedbin; 2124 int ret; 2125 2126 ret = adreno_read_speedbin(dev, &speedbin); 2127 /* 2128 * -ENOENT means that the platform doesn't support speedbin which is 2129 * fine 2130 */ 2131 if (ret == -ENOENT) { 2132 return 0; 2133 } else if (ret) { 2134 dev_err_probe(dev, ret, 2135 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2136 return ret; 2137 } 2138 2139 supp_hw = fuse_to_supp_hw(info, speedbin); 2140 2141 if (supp_hw == UINT_MAX) { 2142 DRM_DEV_ERROR(dev, 2143 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2144 speedbin); 2145 supp_hw = BIT(0); /* Default */ 2146 } 2147 2148 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2149 if (ret) 2150 return ret; 2151 2152 return 0; 2153 } 2154 2155 static const struct adreno_gpu_funcs funcs = { 2156 .base = { 2157 .get_param = adreno_get_param, 2158 .set_param = adreno_set_param, 2159 .hw_init = a6xx_hw_init, 2160 .ucode_load = a6xx_ucode_load, 2161 .pm_suspend = a6xx_gmu_pm_suspend, 2162 .pm_resume = a6xx_gmu_pm_resume, 2163 .recover = a6xx_recover, 2164 .submit = a6xx_submit, 2165 .active_ring = a6xx_active_ring, 2166 .irq = a6xx_irq, 2167 .destroy = a6xx_destroy, 2168 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2169 .show = a6xx_show, 2170 #endif 2171 .gpu_busy = a6xx_gpu_busy, 2172 .gpu_get_freq = a6xx_gmu_get_freq, 2173 .gpu_set_freq = a6xx_gpu_set_freq, 2174 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2175 .gpu_state_get = a6xx_gpu_state_get, 2176 .gpu_state_put = a6xx_gpu_state_put, 2177 #endif 2178 .create_address_space = a6xx_create_address_space, 2179 .create_private_address_space = a6xx_create_private_address_space, 2180 .get_rptr = a6xx_get_rptr, 2181 .progress = a6xx_progress, 2182 }, 2183 .get_timestamp = a6xx_gmu_get_timestamp, 2184 }; 2185 2186 static const struct adreno_gpu_funcs funcs_gmuwrapper = { 2187 .base = { 2188 .get_param = adreno_get_param, 2189 .set_param = adreno_set_param, 2190 .hw_init = a6xx_hw_init, 2191 .ucode_load = a6xx_ucode_load, 2192 .pm_suspend = a6xx_pm_suspend, 2193 .pm_resume = a6xx_pm_resume, 2194 .recover = a6xx_recover, 2195 .submit = a6xx_submit, 2196 .active_ring = a6xx_active_ring, 2197 .irq = a6xx_irq, 2198 .destroy = a6xx_destroy, 2199 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2200 .show = a6xx_show, 2201 #endif 2202 .gpu_busy = a6xx_gpu_busy, 2203 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2204 .gpu_state_get = a6xx_gpu_state_get, 2205 .gpu_state_put = a6xx_gpu_state_put, 2206 #endif 2207 .create_address_space = a6xx_create_address_space, 2208 .create_private_address_space = a6xx_create_private_address_space, 2209 .get_rptr = a6xx_get_rptr, 2210 .progress = a6xx_progress, 2211 }, 2212 .get_timestamp = a6xx_get_timestamp, 2213 }; 2214 2215 static const struct adreno_gpu_funcs funcs_a7xx = { 2216 .base = { 2217 .get_param = adreno_get_param, 2218 .set_param = adreno_set_param, 2219 .hw_init = a6xx_hw_init, 2220 .ucode_load = a6xx_ucode_load, 2221 .pm_suspend = a6xx_gmu_pm_suspend, 2222 .pm_resume = a6xx_gmu_pm_resume, 2223 .recover = a6xx_recover, 2224 .submit = a7xx_submit, 2225 .active_ring = a6xx_active_ring, 2226 .irq = a6xx_irq, 2227 .destroy = a6xx_destroy, 2228 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2229 .show = a6xx_show, 2230 #endif 2231 .gpu_busy = a6xx_gpu_busy, 2232 .gpu_get_freq = a6xx_gmu_get_freq, 2233 .gpu_set_freq = a6xx_gpu_set_freq, 2234 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2235 .gpu_state_get = a6xx_gpu_state_get, 2236 .gpu_state_put = a6xx_gpu_state_put, 2237 #endif 2238 .create_address_space = a6xx_create_address_space, 2239 .create_private_address_space = a6xx_create_private_address_space, 2240 .get_rptr = a6xx_get_rptr, 2241 .progress = a6xx_progress, 2242 }, 2243 .get_timestamp = a6xx_gmu_get_timestamp, 2244 }; 2245 2246 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2247 { 2248 struct msm_drm_private *priv = dev->dev_private; 2249 struct platform_device *pdev = priv->gpu_pdev; 2250 struct adreno_platform_config *config = pdev->dev.platform_data; 2251 struct device_node *node; 2252 struct a6xx_gpu *a6xx_gpu; 2253 struct adreno_gpu *adreno_gpu; 2254 struct msm_gpu *gpu; 2255 bool is_a7xx; 2256 int ret; 2257 2258 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 2259 if (!a6xx_gpu) 2260 return ERR_PTR(-ENOMEM); 2261 2262 adreno_gpu = &a6xx_gpu->base; 2263 gpu = &adreno_gpu->base; 2264 2265 mutex_init(&a6xx_gpu->gmu.lock); 2266 2267 adreno_gpu->registers = NULL; 2268 2269 /* Check if there is a GMU phandle and set it up */ 2270 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2271 /* FIXME: How do we gracefully handle this? */ 2272 BUG_ON(!node); 2273 2274 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2275 2276 adreno_gpu->base.hw_apriv = 2277 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); 2278 2279 /* gpu->info only gets assigned in adreno_gpu_init() */ 2280 is_a7xx = config->info->family == ADRENO_7XX_GEN1 || 2281 config->info->family == ADRENO_7XX_GEN2 || 2282 config->info->family == ADRENO_7XX_GEN3; 2283 2284 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); 2285 2286 ret = a6xx_set_supported_hw(&pdev->dev, config->info); 2287 if (ret) { 2288 a6xx_llc_slices_destroy(a6xx_gpu); 2289 kfree(a6xx_gpu); 2290 return ERR_PTR(ret); 2291 } 2292 2293 if (is_a7xx) 2294 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); 2295 else if (adreno_has_gmu_wrapper(adreno_gpu)) 2296 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); 2297 else 2298 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 2299 if (ret) { 2300 a6xx_destroy(&(a6xx_gpu->base.base)); 2301 return ERR_PTR(ret); 2302 } 2303 2304 /* 2305 * For now only clamp to idle freq for devices where this is known not 2306 * to cause power supply issues: 2307 */ 2308 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2309 priv->gpu_clamp_to_idle = true; 2310 2311 if (adreno_has_gmu_wrapper(adreno_gpu)) 2312 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2313 else 2314 ret = a6xx_gmu_init(a6xx_gpu, node); 2315 of_node_put(node); 2316 if (ret) { 2317 a6xx_destroy(&(a6xx_gpu->base.base)); 2318 return ERR_PTR(ret); 2319 } 2320 2321 if (adreno_is_a7xx(adreno_gpu)) { 2322 ret = a7xx_cx_mem_init(a6xx_gpu); 2323 if (ret) { 2324 a6xx_destroy(&(a6xx_gpu->base.base)); 2325 return ERR_PTR(ret); 2326 } 2327 } 2328 2329 if (gpu->aspace) 2330 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 2331 a6xx_fault_handler); 2332 2333 a6xx_calc_ubwc_config(adreno_gpu); 2334 2335 return gpu; 2336 } 2337