1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/firmware/qcom/qcom_scm.h> 14 #include <linux/pm_domain.h> 15 #include <linux/soc/qcom/llcc-qcom.h> 16 17 #define GPU_PAS_ID 13 18 19 static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu) 20 { 21 u64 count_hi, count_lo, temp; 22 23 do { 24 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); 25 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); 26 temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); 27 } while (unlikely(count_hi != temp)); 28 29 return (count_hi << 32) | count_lo; 30 } 31 32 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) 33 { 34 /* Success if !writedropped0/1 */ 35 if (!(status & mask)) 36 return true; 37 38 udelay(10); 39 40 /* Try to update fenced register again */ 41 gpu_write(gpu, offset, value); 42 43 /* We can't do a posted write here because the power domain could be 44 * in collapse state. So use the heaviest barrier instead 45 */ 46 mb(); 47 return false; 48 } 49 50 static int fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u32 value, u32 mask) 51 { 52 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 53 struct msm_gpu *gpu = &adreno_gpu->base; 54 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 55 u32 status; 56 57 gpu_write(gpu, offset, value); 58 59 /* Nothing else to be done in the case of no-GMU */ 60 if (adreno_has_gmu_wrapper(adreno_gpu)) 61 return 0; 62 63 /* We can't do a posted write here because the power domain could be 64 * in collapse state. So use the heaviest barrier instead 65 */ 66 mb(); 67 68 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, 69 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) 70 return 0; 71 72 /* Try again for another 1ms before failing */ 73 gpu_write(gpu, offset, value); 74 mb(); 75 76 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, 77 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) { 78 /* 79 * The 'delay' warning is here because the pause to print this 80 * warning will allow gpu to move to power collapse which 81 * defeats the purpose of continuous polling for 2 ms 82 */ 83 dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", 84 offset); 85 return 0; 86 } 87 88 dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", 89 offset); 90 91 return -ETIMEDOUT; 92 } 93 94 int a6xx_fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u64 value, u32 mask, bool is_64b) 95 { 96 int ret; 97 98 ret = fenced_write(a6xx_gpu, offset, lower_32_bits(value), mask); 99 if (ret) 100 return ret; 101 102 if (!is_64b) 103 return 0; 104 105 ret = fenced_write(a6xx_gpu, offset + 1, upper_32_bits(value), mask); 106 107 return ret; 108 } 109 110 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 111 { 112 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 113 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 114 115 /* Check that the GMU is idle */ 116 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 117 return false; 118 119 /* Check tha the CX master is idle */ 120 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 121 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 122 return false; 123 124 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 125 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 126 } 127 128 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 129 { 130 /* wait for CP to drain ringbuffer: */ 131 if (!adreno_idle(gpu, ring)) 132 return false; 133 134 if (spin_until(_a6xx_check_idle(gpu))) { 135 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 136 gpu->name, __builtin_return_address(0), 137 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 138 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 139 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 140 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 141 return false; 142 } 143 144 return true; 145 } 146 147 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 148 { 149 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 150 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 151 152 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 153 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 154 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 155 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 156 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 157 } 158 } 159 160 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 161 { 162 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 163 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 164 uint32_t wptr; 165 unsigned long flags; 166 167 update_shadow_rptr(gpu, ring); 168 169 spin_lock_irqsave(&ring->preempt_lock, flags); 170 171 /* Copy the shadow to the actual register */ 172 ring->cur = ring->next; 173 174 /* Make sure to wrap wptr if we need to */ 175 wptr = get_wptr(ring); 176 177 /* Update HW if this is the current ring and we are not in preempt*/ 178 if (!a6xx_in_preempt(a6xx_gpu)) { 179 if (a6xx_gpu->cur_ring == ring) 180 a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false); 181 else 182 ring->restore_wptr = true; 183 } else { 184 ring->restore_wptr = true; 185 } 186 187 spin_unlock_irqrestore(&ring->preempt_lock, flags); 188 } 189 190 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 191 u64 iova) 192 { 193 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 194 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 195 CP_REG_TO_MEM_0_CNT(2) | 196 CP_REG_TO_MEM_0_64B); 197 OUT_RING(ring, lower_32_bits(iova)); 198 OUT_RING(ring, upper_32_bits(iova)); 199 } 200 201 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 202 struct msm_ringbuffer *ring, struct msm_gem_submit *submit) 203 { 204 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; 205 struct msm_context *ctx = submit->queue->ctx; 206 struct drm_gpuvm *vm = msm_context_vm(submit->dev, ctx); 207 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 208 phys_addr_t ttbr; 209 u32 asid; 210 u64 memptr = rbmemptr(ring, ttbr0); 211 212 if (ctx->seqno == ring->cur_ctx_seqno) 213 return; 214 215 if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid)) 216 return; 217 218 if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { 219 /* Wait for previous submit to complete before continuing: */ 220 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 221 OUT_RING(ring, 0); 222 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 223 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 224 OUT_RING(ring, submit->seqno - 1); 225 226 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 227 OUT_RING(ring, CP_SET_THREAD_BOTH); 228 229 /* Reset state used to synchronize BR and BV */ 230 OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1); 231 OUT_RING(ring, 232 CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS | 233 CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE | 234 CP_RESET_CONTEXT_STATE_0_CLEAR_BV_BR_COUNTER | 235 CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS); 236 237 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 238 OUT_RING(ring, CP_SET_THREAD_BR); 239 } 240 241 if (!sysprof) { 242 if (!adreno_is_a7xx(adreno_gpu)) { 243 /* Turn off protected mode to write to special registers */ 244 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 245 OUT_RING(ring, 0); 246 } 247 248 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 249 OUT_RING(ring, 1); 250 } 251 252 /* Execute the table update */ 253 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 254 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 255 256 OUT_RING(ring, 257 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 258 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 259 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 260 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 261 262 /* 263 * Write the new TTBR0 to the memstore. This is good for debugging. 264 * Needed for preemption 265 */ 266 OUT_PKT7(ring, CP_MEM_WRITE, 5); 267 OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_LO(lower_32_bits(memptr))); 268 OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_HI(upper_32_bits(memptr))); 269 OUT_RING(ring, lower_32_bits(ttbr)); 270 OUT_RING(ring, upper_32_bits(ttbr)); 271 OUT_RING(ring, ctx->seqno); 272 273 /* 274 * Sync both threads after switching pagetables and enable BR only 275 * to make sure BV doesn't race ahead while BR is still switching 276 * pagetables. 277 */ 278 if (adreno_is_a7xx(&a6xx_gpu->base)) { 279 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 280 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 281 } 282 283 /* 284 * And finally, trigger a uche flush to be sure there isn't anything 285 * lingering in that part of the GPU 286 */ 287 288 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 289 OUT_RING(ring, CACHE_INVALIDATE); 290 291 if (!sysprof) { 292 /* 293 * Wait for SRAM clear after the pgtable update, so the 294 * two can happen in parallel: 295 */ 296 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 297 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 298 OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO( 299 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 300 OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0)); 301 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 302 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 303 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 304 305 if (!adreno_is_a7xx(adreno_gpu)) { 306 /* Re-enable protected mode: */ 307 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 308 OUT_RING(ring, 1); 309 } 310 } 311 } 312 313 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 314 { 315 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 316 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 317 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 318 struct msm_ringbuffer *ring = submit->ring; 319 unsigned int i, ibs = 0; 320 321 adreno_check_and_reenable_stall(adreno_gpu); 322 323 a6xx_set_pagetable(a6xx_gpu, ring, submit); 324 325 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 326 rbmemptr_stats(ring, index, cpcycles_start)); 327 328 /* 329 * For PM4 the GMU register offsets are calculated from the base of the 330 * GPU registers so we need to add 0x1a800 to the register value on A630 331 * to get the right value from PM4. 332 */ 333 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 334 rbmemptr_stats(ring, index, alwayson_start)); 335 336 /* Invalidate CCU depth and color */ 337 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 338 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 339 340 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 341 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 342 343 /* Submit the commands */ 344 for (i = 0; i < submit->nr_cmds; i++) { 345 switch (submit->cmd[i].type) { 346 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 347 break; 348 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 349 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 350 break; 351 fallthrough; 352 case MSM_SUBMIT_CMD_BUF: 353 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3); 354 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 355 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 356 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size)); 357 ibs++; 358 break; 359 } 360 361 /* 362 * Periodically update shadow-wptr if needed, so that we 363 * can see partial progress of submits with large # of 364 * cmds.. otherwise we could needlessly stall waiting for 365 * ringbuffer state, simply due to looking at a shadow 366 * rptr value that has not been updated 367 */ 368 if ((ibs % 32) == 0) 369 update_shadow_rptr(gpu, ring); 370 } 371 372 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 373 rbmemptr_stats(ring, index, cpcycles_end)); 374 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 375 rbmemptr_stats(ring, index, alwayson_end)); 376 377 /* Write the fence to the scratch register */ 378 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 379 OUT_RING(ring, submit->seqno); 380 381 /* 382 * Execute a CACHE_FLUSH_TS event. This will ensure that the 383 * timestamp is written to the memory and then triggers the interrupt 384 */ 385 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 386 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 387 CP_EVENT_WRITE_0_IRQ); 388 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 389 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 390 OUT_RING(ring, submit->seqno); 391 392 trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu)); 393 394 a6xx_flush(gpu, ring); 395 } 396 397 static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, 398 struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) 399 { 400 u64 preempt_postamble; 401 402 OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); 403 404 OUT_RING(ring, SMMU_INFO); 405 /* don't save SMMU, we write the record from the kernel instead */ 406 OUT_RING(ring, 0); 407 OUT_RING(ring, 0); 408 409 /* privileged and non secure buffer save */ 410 OUT_RING(ring, NON_SECURE_SAVE_ADDR); 411 OUT_RING(ring, lower_32_bits( 412 a6xx_gpu->preempt_iova[ring->id])); 413 OUT_RING(ring, upper_32_bits( 414 a6xx_gpu->preempt_iova[ring->id])); 415 416 /* user context buffer save, seems to be unnused by fw */ 417 OUT_RING(ring, NON_PRIV_SAVE_ADDR); 418 OUT_RING(ring, 0); 419 OUT_RING(ring, 0); 420 421 OUT_RING(ring, COUNTER); 422 /* seems OK to set to 0 to disable it */ 423 OUT_RING(ring, 0); 424 OUT_RING(ring, 0); 425 426 /* Emit postamble to clear perfcounters */ 427 preempt_postamble = a6xx_gpu->preempt_postamble_iova; 428 429 OUT_PKT7(ring, CP_SET_AMBLE, 3); 430 OUT_RING(ring, lower_32_bits(preempt_postamble)); 431 OUT_RING(ring, upper_32_bits(preempt_postamble)); 432 OUT_RING(ring, CP_SET_AMBLE_2_DWORDS( 433 a6xx_gpu->preempt_postamble_len) | 434 CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE)); 435 } 436 437 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 438 { 439 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 440 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 441 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 442 struct msm_ringbuffer *ring = submit->ring; 443 unsigned int i, ibs = 0; 444 445 adreno_check_and_reenable_stall(adreno_gpu); 446 447 /* 448 * Toggle concurrent binning for pagetable switch and set the thread to 449 * BR since only it can execute the pagetable switch packets. 450 */ 451 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 452 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 453 454 a6xx_set_pagetable(a6xx_gpu, ring, submit); 455 456 /* 457 * If preemption is enabled, then set the pseudo register for the save 458 * sequence 459 */ 460 if (gpu->nr_rings > 1) 461 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); 462 463 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 464 rbmemptr_stats(ring, index, cpcycles_start)); 465 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 466 rbmemptr_stats(ring, index, alwayson_start)); 467 468 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 469 OUT_RING(ring, CP_SET_THREAD_BOTH); 470 471 OUT_PKT7(ring, CP_SET_MARKER, 1); 472 OUT_RING(ring, 0x101); /* IFPC disable */ 473 474 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 475 OUT_PKT7(ring, CP_SET_MARKER, 1); 476 OUT_RING(ring, 0x00d); /* IB1LIST start */ 477 } 478 479 /* Submit the commands */ 480 for (i = 0; i < submit->nr_cmds; i++) { 481 switch (submit->cmd[i].type) { 482 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 483 break; 484 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 485 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 486 break; 487 fallthrough; 488 case MSM_SUBMIT_CMD_BUF: 489 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3); 490 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 491 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 492 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size)); 493 ibs++; 494 break; 495 } 496 497 /* 498 * Periodically update shadow-wptr if needed, so that we 499 * can see partial progress of submits with large # of 500 * cmds.. otherwise we could needlessly stall waiting for 501 * ringbuffer state, simply due to looking at a shadow 502 * rptr value that has not been updated 503 */ 504 if ((ibs % 32) == 0) 505 update_shadow_rptr(gpu, ring); 506 } 507 508 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 509 OUT_PKT7(ring, CP_SET_MARKER, 1); 510 OUT_RING(ring, 0x00e); /* IB1LIST end */ 511 } 512 513 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 514 rbmemptr_stats(ring, index, cpcycles_end)); 515 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 516 rbmemptr_stats(ring, index, alwayson_end)); 517 518 /* Write the fence to the scratch register */ 519 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 520 OUT_RING(ring, submit->seqno); 521 522 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 523 OUT_RING(ring, CP_SET_THREAD_BR); 524 525 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 526 OUT_RING(ring, CCU_INVALIDATE_DEPTH); 527 528 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 529 OUT_RING(ring, CCU_INVALIDATE_COLOR); 530 531 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 532 OUT_RING(ring, CP_SET_THREAD_BV); 533 534 /* 535 * Make sure the timestamp is committed once BV pipe is 536 * completely done with this submission. 537 */ 538 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 539 OUT_RING(ring, CACHE_CLEAN | BIT(27)); 540 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 541 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 542 OUT_RING(ring, submit->seqno); 543 544 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 545 OUT_RING(ring, CP_SET_THREAD_BR); 546 547 /* 548 * This makes sure that BR doesn't race ahead and commit 549 * timestamp to memstore while BV is still processing 550 * this submission. 551 */ 552 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 553 OUT_RING(ring, 0); 554 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 555 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 556 OUT_RING(ring, submit->seqno); 557 558 a6xx_gpu->last_seqno[ring->id] = submit->seqno; 559 560 /* write the ringbuffer timestamp */ 561 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 562 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); 563 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 564 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 565 OUT_RING(ring, submit->seqno); 566 567 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 568 OUT_RING(ring, CP_SET_THREAD_BOTH); 569 570 OUT_PKT7(ring, CP_SET_MARKER, 1); 571 OUT_RING(ring, 0x100); /* IFPC enable */ 572 573 /* If preemption is enabled */ 574 if (gpu->nr_rings > 1) { 575 /* Yield the floor on command completion */ 576 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 577 578 /* 579 * If dword[2:1] are non zero, they specify an address for 580 * the CP to write the value of dword[3] to on preemption 581 * complete. Write 0 to skip the write 582 */ 583 OUT_RING(ring, 0x00); 584 OUT_RING(ring, 0x00); 585 /* Data value - not used if the address above is 0 */ 586 OUT_RING(ring, 0x01); 587 /* generate interrupt on preemption completion */ 588 OUT_RING(ring, 0x00); 589 } 590 591 592 trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu)); 593 594 a6xx_flush(gpu, ring); 595 596 /* Check to see if we need to start preemption */ 597 a6xx_preempt_trigger(gpu); 598 } 599 600 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 601 { 602 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 603 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 604 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 605 const struct adreno_reglist *reg; 606 unsigned int i; 607 u32 cgc_delay, cgc_hyst; 608 u32 val, clock_cntl_on; 609 610 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 611 return; 612 613 if (adreno_is_a630(adreno_gpu)) 614 clock_cntl_on = 0x8aa8aa02; 615 else if (adreno_is_a610(adreno_gpu)) 616 clock_cntl_on = 0xaaa8aa82; 617 else if (adreno_is_a702(adreno_gpu)) 618 clock_cntl_on = 0xaaaaaa82; 619 else 620 clock_cntl_on = 0x8aa8aa82; 621 622 cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; 623 cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; 624 625 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 626 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 627 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 628 state ? cgc_delay : 0); 629 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 630 state ? cgc_hyst : 0); 631 632 if (!adreno_gpu->info->a6xx->hwcg) { 633 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 634 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); 635 636 if (state) { 637 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); 638 639 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, 640 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 641 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 642 return; 643 } 644 645 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 646 } 647 648 return; 649 } 650 651 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 652 653 /* Don't re-program the registers if they are already correct */ 654 if ((!state && !val) || (state && (val == clock_cntl_on))) 655 return; 656 657 /* Disable SP clock before programming HWCG registers */ 658 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 659 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 660 661 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) 662 gpu_write(gpu, reg->offset, state ? reg->value : 0); 663 664 /* Enable SP clock */ 665 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 666 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 667 668 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 669 } 670 671 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 672 { 673 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 674 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 675 unsigned i; 676 677 /* 678 * Enable access protection to privileged registers, fault on an access 679 * protect violation and select the last span to protect from the start 680 * address all the way to the end of the register address space 681 */ 682 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 683 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | 684 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | 685 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); 686 687 for (i = 0; i < protect->count - 1; i++) { 688 /* Intentionally skip writing to some registers */ 689 if (protect->regs[i]) 690 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); 691 } 692 /* last CP_PROTECT to have "infinite" length on the last entry */ 693 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); 694 } 695 696 static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 697 { 698 const struct qcom_ubwc_cfg_data *common_cfg; 699 struct qcom_ubwc_cfg_data *cfg = &gpu->_ubwc_config; 700 701 /* Inherit the common config and make some necessary fixups */ 702 common_cfg = qcom_ubwc_config_get_data(); 703 if (IS_ERR(common_cfg)) 704 return PTR_ERR(common_cfg); 705 706 /* Copy the data into the internal struct to drop the const qualifier (temporarily) */ 707 *cfg = *common_cfg; 708 709 cfg->ubwc_swizzle = 0x6; 710 cfg->highest_bank_bit = 15; 711 712 if (adreno_is_a610(gpu)) { 713 cfg->highest_bank_bit = 13; 714 cfg->ubwc_swizzle = 0x7; 715 } 716 717 if (adreno_is_a618(gpu)) 718 cfg->highest_bank_bit = 14; 719 720 if (adreno_is_a619(gpu)) 721 /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ 722 cfg->highest_bank_bit = 13; 723 724 if (adreno_is_a619_holi(gpu)) 725 cfg->highest_bank_bit = 13; 726 727 if (adreno_is_a621(gpu)) 728 cfg->highest_bank_bit = 13; 729 730 if (adreno_is_a623(gpu)) 731 cfg->highest_bank_bit = 16; 732 733 if (adreno_is_a650(gpu) || 734 adreno_is_a660(gpu) || 735 adreno_is_a690(gpu) || 736 adreno_is_a730(gpu) || 737 adreno_is_a740_family(gpu)) { 738 /* TODO: get ddr type from bootloader and use 15 for LPDDR4 */ 739 cfg->highest_bank_bit = 16; 740 } 741 742 if (adreno_is_a663(gpu)) { 743 cfg->highest_bank_bit = 13; 744 cfg->ubwc_swizzle = 0x4; 745 } 746 747 if (adreno_is_7c3(gpu)) 748 cfg->highest_bank_bit = 14; 749 750 if (adreno_is_a702(gpu)) 751 cfg->highest_bank_bit = 14; 752 753 if (cfg->highest_bank_bit != common_cfg->highest_bank_bit) 754 DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs %u (UBWC_CFG)\n", 755 cfg->highest_bank_bit, common_cfg->highest_bank_bit); 756 757 if (cfg->ubwc_swizzle != common_cfg->ubwc_swizzle) 758 DRM_WARN_ONCE("Inconclusive ubwc_swizzle value: %u (GPU) vs %u (UBWC_CFG)\n", 759 cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); 760 761 gpu->ubwc_config = &gpu->_ubwc_config; 762 763 return 0; 764 } 765 766 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 767 { 768 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 769 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; 770 /* 771 * We subtract 13 from the highest bank bit (13 is the minimum value 772 * allowed by hw) and write the lowest two bits of the remaining value 773 * as hbb_lo and the one above it as hbb_hi to the hardware. 774 */ 775 BUG_ON(cfg->highest_bank_bit < 13); 776 u32 hbb = cfg->highest_bank_bit - 13; 777 bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; 778 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); 779 bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); 780 bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; 781 bool min_acc_len_64b = false; 782 u8 uavflagprd_inv = 0; 783 u32 hbb_hi = hbb >> 2; 784 u32 hbb_lo = hbb & 3; 785 786 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 787 uavflagprd_inv = 2; 788 789 if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 790 min_acc_len_64b = true; 791 792 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 793 level2_swizzling_dis << 12 | 794 rgb565_predicator << 11 | 795 hbb_hi << 10 | amsbc << 4 | 796 min_acc_len_64b << 3 | 797 hbb_lo << 1 | ubwc_mode); 798 799 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 800 level2_swizzling_dis << 6 | hbb_hi << 4 | 801 min_acc_len_64b << 3 | 802 hbb_lo << 1 | ubwc_mode); 803 804 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 805 level2_swizzling_dis << 12 | hbb_hi << 10 | 806 uavflagprd_inv << 4 | 807 min_acc_len_64b << 3 | 808 hbb_lo << 1 | ubwc_mode); 809 810 if (adreno_is_a7xx(adreno_gpu)) 811 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 812 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 813 814 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 815 min_acc_len_64b << 23 | hbb_lo << 21); 816 817 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 818 cfg->macrotile_mode); 819 } 820 821 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 822 { 823 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 824 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 825 const struct adreno_reglist_list *reglist; 826 void *ptr = a6xx_gpu->pwrup_reglist_ptr; 827 struct cpu_gpu_lock *lock = ptr; 828 u32 *dest = (u32 *)&lock->regs[0]; 829 int i; 830 831 lock->gpu_req = lock->cpu_req = lock->turn = 0; 832 833 reglist = adreno_gpu->info->a6xx->ifpc_reglist; 834 lock->ifpc_list_len = reglist->count; 835 836 /* 837 * For each entry in each of the lists, write the offset and the current 838 * register value into the GPU buffer 839 */ 840 for (i = 0; i < reglist->count; i++) { 841 *dest++ = reglist->regs[i]; 842 *dest++ = gpu_read(gpu, reglist->regs[i]); 843 } 844 845 reglist = adreno_gpu->info->a6xx->pwrup_reglist; 846 lock->preemption_list_len = reglist->count; 847 848 for (i = 0; i < reglist->count; i++) { 849 *dest++ = reglist->regs[i]; 850 *dest++ = gpu_read(gpu, reglist->regs[i]); 851 } 852 853 /* 854 * The overall register list is composed of 855 * 1. Static IFPC-only registers 856 * 2. Static IFPC + preemption registers 857 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) 858 * 859 * The first two lists are static. Size of these lists are stored as 860 * number of pairs in ifpc_list_len and preemption_list_len 861 * respectively. With concurrent binning, Some of the perfcounter 862 * registers being virtualized, CP needs to know the pipe id to program 863 * the aperture inorder to restore the same. Thus, third list is a 864 * dynamic list with triplets as 865 * (<aperture, shifted 12 bits> <address> <data>), and the length is 866 * stored as number for triplets in dynamic_list_len. 867 */ 868 lock->dynamic_list_len = 0; 869 } 870 871 static int a7xx_preempt_start(struct msm_gpu *gpu) 872 { 873 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 874 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 875 struct msm_ringbuffer *ring = gpu->rb[0]; 876 877 if (gpu->nr_rings <= 1) 878 return 0; 879 880 /* Turn CP protection off */ 881 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 882 OUT_RING(ring, 0); 883 884 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); 885 886 /* Yield the floor on command completion */ 887 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 888 OUT_RING(ring, 0x00); 889 OUT_RING(ring, 0x00); 890 OUT_RING(ring, 0x00); 891 /* Generate interrupt on preemption completion */ 892 OUT_RING(ring, 0x00); 893 894 a6xx_flush(gpu, ring); 895 896 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 897 } 898 899 static int a6xx_cp_init(struct msm_gpu *gpu) 900 { 901 struct msm_ringbuffer *ring = gpu->rb[0]; 902 903 OUT_PKT7(ring, CP_ME_INIT, 8); 904 905 OUT_RING(ring, 0x0000002f); 906 907 /* Enable multiple hardware contexts */ 908 OUT_RING(ring, 0x00000003); 909 910 /* Enable error detection */ 911 OUT_RING(ring, 0x20000000); 912 913 /* Don't enable header dump */ 914 OUT_RING(ring, 0x00000000); 915 OUT_RING(ring, 0x00000000); 916 917 /* No workarounds enabled */ 918 OUT_RING(ring, 0x00000000); 919 920 /* Pad rest of the cmds with 0's */ 921 OUT_RING(ring, 0x00000000); 922 OUT_RING(ring, 0x00000000); 923 924 a6xx_flush(gpu, ring); 925 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 926 } 927 928 static int a7xx_cp_init(struct msm_gpu *gpu) 929 { 930 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 931 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 932 struct msm_ringbuffer *ring = gpu->rb[0]; 933 u32 mask; 934 935 /* Disable concurrent binning before sending CP init */ 936 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 937 OUT_RING(ring, BIT(27)); 938 939 OUT_PKT7(ring, CP_ME_INIT, 7); 940 941 /* Use multiple HW contexts */ 942 mask = BIT(0); 943 944 /* Enable error detection */ 945 mask |= BIT(1); 946 947 /* Set default reset state */ 948 mask |= BIT(3); 949 950 /* Disable save/restore of performance counters across preemption */ 951 mask |= BIT(6); 952 953 /* Enable the register init list with the spinlock */ 954 mask |= BIT(8); 955 956 OUT_RING(ring, mask); 957 958 /* Enable multiple hardware contexts */ 959 OUT_RING(ring, 0x00000003); 960 961 /* Enable error detection */ 962 OUT_RING(ring, 0x20000000); 963 964 /* Operation mode mask */ 965 OUT_RING(ring, 0x00000002); 966 967 /* *Don't* send a power up reg list for concurrent binning (TODO) */ 968 /* Lo address */ 969 OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); 970 /* Hi address */ 971 OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); 972 /* BIT(31) set => read the regs from the list */ 973 OUT_RING(ring, BIT(31)); 974 975 a6xx_flush(gpu, ring); 976 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 977 } 978 979 /* 980 * Check that the microcode version is new enough to include several key 981 * security fixes. Return true if the ucode is safe. 982 */ 983 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 984 struct drm_gem_object *obj) 985 { 986 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 987 struct msm_gpu *gpu = &adreno_gpu->base; 988 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 989 u32 *buf = msm_gem_get_vaddr(obj); 990 bool ret = false; 991 992 if (IS_ERR(buf)) 993 return false; 994 995 /* A7xx is safe! */ 996 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) 997 return true; 998 999 /* 1000 * Targets up to a640 (a618, a630 and a640) need to check for a 1001 * microcode version that is patched to support the whereami opcode or 1002 * one that is new enough to include it by default. 1003 * 1004 * a650 tier targets don't need whereami but still need to be 1005 * equal to or newer than 0.95 for other security fixes 1006 * 1007 * a660 targets have all the critical security fixes from the start 1008 */ 1009 if (!strcmp(sqe_name, "a630_sqe.fw")) { 1010 /* 1011 * If the lowest nibble is 0xa that is an indication that this 1012 * microcode has been patched. The actual version is in dword 1013 * [3] but we only care about the patchlevel which is the lowest 1014 * nibble of dword [3] 1015 * 1016 * Otherwise check that the firmware is greater than or equal 1017 * to 1.90 which was the first version that had this fix built 1018 * in 1019 */ 1020 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 1021 (buf[0] & 0xfff) >= 0x190) { 1022 a6xx_gpu->has_whereami = true; 1023 ret = true; 1024 goto out; 1025 } 1026 1027 DRM_DEV_ERROR(&gpu->pdev->dev, 1028 "a630 SQE ucode is too old. Have version %x need at least %x\n", 1029 buf[0] & 0xfff, 0x190); 1030 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 1031 if ((buf[0] & 0xfff) >= 0x095) { 1032 ret = true; 1033 goto out; 1034 } 1035 1036 DRM_DEV_ERROR(&gpu->pdev->dev, 1037 "a650 SQE ucode is too old. Have version %x need at least %x\n", 1038 buf[0] & 0xfff, 0x095); 1039 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 1040 ret = true; 1041 } else { 1042 DRM_DEV_ERROR(&gpu->pdev->dev, 1043 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 1044 } 1045 out: 1046 msm_gem_put_vaddr(obj); 1047 return ret; 1048 } 1049 1050 static int a6xx_ucode_load(struct msm_gpu *gpu) 1051 { 1052 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1053 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1054 1055 if (!a6xx_gpu->sqe_bo) { 1056 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 1057 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 1058 1059 if (IS_ERR(a6xx_gpu->sqe_bo)) { 1060 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 1061 1062 a6xx_gpu->sqe_bo = NULL; 1063 DRM_DEV_ERROR(&gpu->pdev->dev, 1064 "Could not allocate SQE ucode: %d\n", ret); 1065 1066 return ret; 1067 } 1068 1069 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 1070 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 1071 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm); 1072 drm_gem_object_put(a6xx_gpu->sqe_bo); 1073 1074 a6xx_gpu->sqe_bo = NULL; 1075 return -EPERM; 1076 } 1077 } 1078 1079 /* 1080 * Expanded APRIV and targets that support WHERE_AM_I both need a 1081 * privileged buffer to store the RPTR shadow 1082 */ 1083 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 1084 !a6xx_gpu->shadow_bo) { 1085 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 1086 sizeof(u32) * gpu->nr_rings, 1087 MSM_BO_WC | MSM_BO_MAP_PRIV, 1088 gpu->vm, &a6xx_gpu->shadow_bo, 1089 &a6xx_gpu->shadow_iova); 1090 1091 if (IS_ERR(a6xx_gpu->shadow)) 1092 return PTR_ERR(a6xx_gpu->shadow); 1093 1094 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 1095 } 1096 1097 a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, 1098 MSM_BO_WC | MSM_BO_MAP_PRIV, 1099 gpu->vm, &a6xx_gpu->pwrup_reglist_bo, 1100 &a6xx_gpu->pwrup_reglist_iova); 1101 1102 if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) 1103 return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); 1104 1105 msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); 1106 1107 return 0; 1108 } 1109 1110 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 1111 { 1112 static bool loaded; 1113 int ret; 1114 1115 if (loaded) 1116 return 0; 1117 1118 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 1119 1120 loaded = !ret; 1121 return ret; 1122 } 1123 1124 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1125 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1126 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1127 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 1128 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 1129 A6XX_RBBM_INT_0_MASK_CP_RB | \ 1130 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1131 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1132 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1133 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1134 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 1135 1136 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1137 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1138 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 1139 A6XX_RBBM_INT_0_MASK_CP_SW | \ 1140 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1141 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 1142 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 1143 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1144 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1145 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1146 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1147 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 1148 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 1149 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1150 1151 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ 1152 A6XX_CP_APRIV_CNTL_RBFETCH | \ 1153 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \ 1154 A6XX_CP_APRIV_CNTL_RBRPWB) 1155 1156 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \ 1157 A6XX_CP_APRIV_CNTL_CDREAD | \ 1158 A6XX_CP_APRIV_CNTL_CDWRITE) 1159 1160 static int hw_init(struct msm_gpu *gpu) 1161 { 1162 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1163 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1164 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1165 u64 gmem_range_min; 1166 unsigned int i; 1167 int ret; 1168 1169 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1170 /* Make sure the GMU keeps the GPU on while we set it up */ 1171 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1172 if (ret) 1173 return ret; 1174 } 1175 1176 /* Clear GBIF halt in case GX domain was not collapsed */ 1177 if (adreno_is_a619_holi(adreno_gpu)) { 1178 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1179 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1180 1181 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 1182 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); 1183 } else if (a6xx_has_gbif(adreno_gpu)) { 1184 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1185 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1186 1187 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 1188 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); 1189 } 1190 1191 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 1192 1193 if (adreno_is_a619_holi(adreno_gpu)) 1194 a6xx_sptprac_enable(gmu); 1195 1196 /* 1197 * Disable the trusted memory range - we don't actually supported secure 1198 * memory rendering at this point in time and we don't want to block off 1199 * part of the virtual memory space. 1200 */ 1201 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 1202 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 1203 1204 if (!adreno_is_a7xx(adreno_gpu)) { 1205 /* Turn on 64 bit addressing for all blocks */ 1206 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 1207 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 1208 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 1209 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 1210 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 1211 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 1212 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 1213 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 1214 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 1215 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 1216 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 1217 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 1218 } 1219 1220 /* enable hardware clockgating */ 1221 a6xx_set_hwcg(gpu, true); 1222 1223 /* VBIF/GBIF start*/ 1224 if (adreno_is_a610_family(adreno_gpu) || 1225 adreno_is_a640_family(adreno_gpu) || 1226 adreno_is_a650_family(adreno_gpu) || 1227 adreno_is_a7xx(adreno_gpu)) { 1228 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 1229 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 1230 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 1231 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 1232 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 1233 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); 1234 } else { 1235 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 1236 } 1237 1238 if (adreno_is_a630(adreno_gpu)) 1239 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 1240 1241 if (adreno_is_a7xx(adreno_gpu)) 1242 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); 1243 1244 /* Make all blocks contribute to the GPU BUSY perf counter */ 1245 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 1246 1247 /* Disable L2 bypass in the UCHE */ 1248 if (adreno_is_a7xx(adreno_gpu)) { 1249 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 1250 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 1251 } else { 1252 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0); 1253 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 1254 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 1255 } 1256 1257 if (!(adreno_is_a650_family(adreno_gpu) || 1258 adreno_is_a702(adreno_gpu) || 1259 adreno_is_a730(adreno_gpu))) { 1260 gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; 1261 1262 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 1263 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); 1264 1265 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 1266 gmem_range_min + adreno_gpu->info->gmem - 1); 1267 } 1268 1269 if (adreno_is_a7xx(adreno_gpu)) 1270 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); 1271 else { 1272 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 1273 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 1274 } 1275 1276 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 1277 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1278 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1279 } else if (adreno_is_a610_family(adreno_gpu)) { 1280 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 1281 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 1282 } else if (!adreno_is_a7xx(adreno_gpu)) { 1283 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 1284 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1285 } 1286 1287 if (adreno_is_a660_family(adreno_gpu)) 1288 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1289 1290 /* Setting the mem pool size */ 1291 if (adreno_is_a610(adreno_gpu)) { 1292 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 1293 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 1294 } else if (adreno_is_a702(adreno_gpu)) { 1295 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); 1296 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); 1297 } else if (!adreno_is_a7xx(adreno_gpu)) 1298 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 1299 1300 1301 /* Set the default primFifo threshold values */ 1302 if (adreno_gpu->info->a6xx->prim_fifo_threshold) 1303 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 1304 adreno_gpu->info->a6xx->prim_fifo_threshold); 1305 1306 /* Set the AHB default slave response to "ERROR" */ 1307 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1308 1309 /* Turn on performance counters */ 1310 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1311 1312 if (adreno_is_a7xx(adreno_gpu)) { 1313 /* Turn on the IFPC counter (countable 4 on XOCLK4) */ 1314 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1315 FIELD_PREP(GENMASK(7, 0), 0x4)); 1316 } 1317 1318 /* Select CP0 to always count cycles */ 1319 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1320 1321 a6xx_set_ubwc_config(gpu); 1322 1323 /* Enable fault detection */ 1324 if (adreno_is_a730(adreno_gpu) || 1325 adreno_is_a740_family(adreno_gpu)) 1326 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); 1327 else if (adreno_is_a690(adreno_gpu)) 1328 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); 1329 else if (adreno_is_a619(adreno_gpu)) 1330 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1331 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 1332 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1333 else 1334 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1335 1336 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1337 1338 /* Set weights for bicubic filtering */ 1339 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1340 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); 1341 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1342 0x3fe05ff4); 1343 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1344 0x3fa0ebee); 1345 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1346 0x3f5193ed); 1347 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1348 0x3f0243f0); 1349 } 1350 1351 /* Set up the CX GMU counter 0 to count busy ticks */ 1352 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1353 1354 /* Enable the power counter */ 1355 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1356 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1357 1358 /* Protect registers from the CP */ 1359 a6xx_set_cp_protect(gpu); 1360 1361 if (adreno_is_a660_family(adreno_gpu)) { 1362 if (adreno_is_a690(adreno_gpu)) 1363 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); 1364 else 1365 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1366 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1367 } else if (adreno_is_a702(adreno_gpu)) { 1368 /* Something to do with the HLSQ cluster */ 1369 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); 1370 } 1371 1372 if (adreno_is_a690(adreno_gpu)) 1373 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); 1374 /* Set dualQ + disable afull for A660 GPU */ 1375 else if (adreno_is_a660(adreno_gpu) || adreno_is_a663(adreno_gpu)) 1376 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1377 else if (adreno_is_a7xx(adreno_gpu)) 1378 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 1379 FIELD_PREP(GENMASK(19, 16), 6) | 1380 FIELD_PREP(GENMASK(15, 12), 6) | 1381 FIELD_PREP(GENMASK(11, 8), 9) | 1382 BIT(3) | BIT(2) | 1383 FIELD_PREP(GENMASK(1, 0), 2)); 1384 1385 /* Enable expanded apriv for targets that support it */ 1386 if (gpu->hw_apriv) { 1387 if (adreno_is_a7xx(adreno_gpu)) { 1388 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1389 A7XX_BR_APRIVMASK); 1390 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, 1391 A7XX_APRIV_MASK); 1392 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, 1393 A7XX_APRIV_MASK); 1394 } else 1395 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1396 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); 1397 } 1398 1399 if (adreno_is_a750(adreno_gpu)) { 1400 /* Disable ubwc merged UFC request feature */ 1401 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); 1402 1403 /* Enable TP flaghint and other performance settings */ 1404 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); 1405 } else if (adreno_is_a7xx(adreno_gpu)) { 1406 /* Disable non-ubwc read reqs from passing write reqs */ 1407 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); 1408 } 1409 1410 /* Enable interrupts */ 1411 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 1412 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); 1413 1414 ret = adreno_hw_init(gpu); 1415 if (ret) 1416 goto out; 1417 1418 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1419 1420 /* Set the ringbuffer address */ 1421 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1422 1423 /* Targets that support extended APRIV can use the RPTR shadow from 1424 * hardware but all the other ones need to disable the feature. Targets 1425 * that support the WHERE_AM_I opcode can use that instead 1426 */ 1427 if (adreno_gpu->base.hw_apriv) 1428 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1429 else 1430 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1431 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1432 1433 /* Configure the RPTR shadow if needed: */ 1434 if (a6xx_gpu->shadow_bo) { 1435 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1436 shadowptr(a6xx_gpu, gpu->rb[0])); 1437 for (unsigned int i = 0; i < gpu->nr_rings; i++) 1438 a6xx_gpu->shadow[i] = 0; 1439 } 1440 1441 /* ..which means "always" on A7xx, also for BV shadow */ 1442 if (adreno_is_a7xx(adreno_gpu)) { 1443 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, 1444 rbmemptr(gpu->rb[0], bv_rptr)); 1445 } 1446 1447 a6xx_preempt_hw_init(gpu); 1448 1449 /* Always come up on rb 0 */ 1450 a6xx_gpu->cur_ring = gpu->rb[0]; 1451 1452 for (i = 0; i < gpu->nr_rings; i++) 1453 gpu->rb[i]->cur_ctx_seqno = 0; 1454 1455 /* Enable the SQE_to start the CP engine */ 1456 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1457 1458 if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { 1459 a7xx_patch_pwrup_reglist(gpu); 1460 a6xx_gpu->pwrup_reglist_emitted = true; 1461 } 1462 1463 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); 1464 if (ret) 1465 goto out; 1466 1467 /* 1468 * Try to load a zap shader into the secure world. If successful 1469 * we can use the CP to switch out of secure mode. If not then we 1470 * have no resource but to try to switch ourselves out manually. If we 1471 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1472 * be blocked and a permissions violation will soon follow. 1473 */ 1474 ret = a6xx_zap_shader_init(gpu); 1475 if (!ret) { 1476 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1477 OUT_RING(gpu->rb[0], 0x00000000); 1478 1479 a6xx_flush(gpu, gpu->rb[0]); 1480 if (!a6xx_idle(gpu, gpu->rb[0])) 1481 return -EINVAL; 1482 } else if (ret == -ENODEV) { 1483 /* 1484 * This device does not use zap shader (but print a warning 1485 * just in case someone got their dt wrong.. hopefully they 1486 * have a debug UART to realize the error of their ways... 1487 * if you mess this up you are about to crash horribly) 1488 */ 1489 dev_warn_once(gpu->dev->dev, 1490 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1491 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1492 ret = 0; 1493 } else { 1494 return ret; 1495 } 1496 1497 out: 1498 if (adreno_has_gmu_wrapper(adreno_gpu)) 1499 return ret; 1500 1501 /* Last step - yield the ringbuffer */ 1502 a7xx_preempt_start(gpu); 1503 1504 /* 1505 * Tell the GMU that we are done touching the GPU and it can start power 1506 * management 1507 */ 1508 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1509 1510 if (a6xx_gpu->gmu.legacy) { 1511 /* Take the GMU out of its special boot mode */ 1512 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1513 } 1514 1515 return ret; 1516 } 1517 1518 static int a6xx_hw_init(struct msm_gpu *gpu) 1519 { 1520 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1521 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1522 int ret; 1523 1524 mutex_lock(&a6xx_gpu->gmu.lock); 1525 ret = hw_init(gpu); 1526 mutex_unlock(&a6xx_gpu->gmu.lock); 1527 1528 return ret; 1529 } 1530 1531 static void a6xx_dump(struct msm_gpu *gpu) 1532 { 1533 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1534 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1535 adreno_dump(gpu); 1536 } 1537 1538 static void a6xx_recover(struct msm_gpu *gpu) 1539 { 1540 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1541 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1542 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1543 int i, active_submits; 1544 1545 adreno_dump_info(gpu); 1546 1547 if (a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) { 1548 /* Sometimes crashstate capture is skipped, so SQE should be halted here again */ 1549 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1550 1551 for (i = 0; i < 8; i++) 1552 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1553 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1554 1555 if (hang_debug) 1556 a6xx_dump(gpu); 1557 1558 } 1559 1560 /* 1561 * To handle recovery specific sequences during the rpm suspend we are 1562 * about to trigger 1563 */ 1564 1565 a6xx_gpu->hung = true; 1566 1567 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1568 1569 /* active_submit won't change until we make a submission */ 1570 mutex_lock(&gpu->active_lock); 1571 active_submits = gpu->active_submits; 1572 1573 /* 1574 * Temporarily clear active_submits count to silence a WARN() in the 1575 * runtime suspend cb 1576 */ 1577 gpu->active_submits = 0; 1578 1579 if (adreno_has_gmu_wrapper(adreno_gpu)) { 1580 /* Drain the outstanding traffic on memory buses */ 1581 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1582 1583 /* Reset the GPU to a clean state */ 1584 a6xx_gpu_sw_reset(gpu, true); 1585 a6xx_gpu_sw_reset(gpu, false); 1586 } 1587 1588 reinit_completion(&gmu->pd_gate); 1589 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1590 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1591 1592 /* Drop the rpm refcount from active submits */ 1593 if (active_submits) 1594 pm_runtime_put(&gpu->pdev->dev); 1595 1596 /* And the final one from recover worker */ 1597 pm_runtime_put_sync(&gpu->pdev->dev); 1598 1599 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1600 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1601 1602 dev_pm_genpd_remove_notifier(gmu->cxpd); 1603 1604 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1605 1606 if (active_submits) 1607 pm_runtime_get(&gpu->pdev->dev); 1608 1609 pm_runtime_get_sync(&gpu->pdev->dev); 1610 1611 gpu->active_submits = active_submits; 1612 mutex_unlock(&gpu->active_lock); 1613 1614 msm_gpu_hw_init(gpu); 1615 a6xx_gpu->hung = false; 1616 } 1617 1618 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1619 { 1620 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1621 static const char *uche_clients[7] = { 1622 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1623 }; 1624 u32 val; 1625 1626 if (adreno_is_a7xx(adreno_gpu)) { 1627 if (mid != 1 && mid != 2 && mid != 3 && mid != 8) 1628 return "UNKNOWN"; 1629 } else { 1630 if (mid < 1 || mid > 3) 1631 return "UNKNOWN"; 1632 } 1633 1634 /* 1635 * The source of the data depends on the mid ID read from FSYNR1. 1636 * and the client ID read from the UCHE block 1637 */ 1638 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1639 1640 if (adreno_is_a7xx(adreno_gpu)) { 1641 /* Bit 3 for mid=3 indicates BR or BV */ 1642 static const char *uche_clients_a7xx[16] = { 1643 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", 1644 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 1645 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", 1646 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 1647 }; 1648 1649 /* LPAC has the same clients as BR and BV, but because it is 1650 * compute-only some of them do not exist and there are holes 1651 * in the array. 1652 */ 1653 static const char *uche_clients_lpac_a7xx[8] = { 1654 "-", "LPAC_SP", "-", "-", 1655 "LPAC_HLSQ", "-", "-", "LPAC_TP", 1656 }; 1657 1658 val &= GENMASK(6, 0); 1659 1660 /* mid=3 refers to BR or BV */ 1661 if (mid == 3) { 1662 if (val < ARRAY_SIZE(uche_clients_a7xx)) 1663 return uche_clients_a7xx[val]; 1664 else 1665 return "UCHE"; 1666 } 1667 1668 /* mid=8 refers to LPAC */ 1669 if (mid == 8) { 1670 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) 1671 return uche_clients_lpac_a7xx[val]; 1672 else 1673 return "UCHE_LPAC"; 1674 } 1675 1676 /* mid=2 is a catchall for everything else in LPAC */ 1677 if (mid == 2) 1678 return "UCHE_LPAC"; 1679 1680 /* mid=1 is a catchall for everything else in BR/BV */ 1681 return "UCHE"; 1682 } else if (adreno_is_a660_family(adreno_gpu)) { 1683 static const char *uche_clients_a660[8] = { 1684 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", 1685 }; 1686 1687 static const char *uche_clients_a660_not[8] = { 1688 "not VFD", "not SP", "not VSC", "not VPC", 1689 "not HLSQ", "not PC", "not LRZ", "not TP", 1690 }; 1691 1692 val &= GENMASK(6, 0); 1693 1694 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) 1695 return uche_clients_a660[val]; 1696 1697 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) 1698 return uche_clients_a660_not[val]; 1699 1700 return "UCHE"; 1701 } else { 1702 /* mid = 3 is most precise and refers to only one block per client */ 1703 if (mid == 3) 1704 return uche_clients[val & 7]; 1705 1706 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1707 if (mid == 2) 1708 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1709 1710 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1711 return "UCHE"; 1712 } 1713 } 1714 1715 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1716 { 1717 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1718 1719 if (id == 0) 1720 return "CP"; 1721 else if (id == 4) 1722 return "CCU"; 1723 else if (id == 6) 1724 return "CDP Prefetch"; 1725 else if (id == 7) 1726 return "GMU"; 1727 else if (id == 5 && adreno_is_a7xx(adreno_gpu)) 1728 return "Flag cache"; 1729 1730 return a6xx_uche_fault_block(gpu, id); 1731 } 1732 1733 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1734 { 1735 struct msm_gpu *gpu = arg; 1736 struct adreno_smmu_fault_info *info = data; 1737 const char *block = "unknown"; 1738 1739 u32 scratch[] = { 1740 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1741 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1742 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1743 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1744 }; 1745 1746 if (info) 1747 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1748 1749 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1750 } 1751 1752 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1753 { 1754 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1755 1756 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1757 u32 val; 1758 1759 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1760 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1761 dev_err_ratelimited(&gpu->pdev->dev, 1762 "CP | opcode error | possible opcode=0x%8.8X\n", 1763 val); 1764 } 1765 1766 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1767 dev_err_ratelimited(&gpu->pdev->dev, 1768 "CP ucode error interrupt\n"); 1769 1770 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1771 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1772 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1773 1774 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1775 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1776 1777 dev_err_ratelimited(&gpu->pdev->dev, 1778 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1779 val & (1 << 20) ? "READ" : "WRITE", 1780 (val & 0x3ffff), val); 1781 } 1782 1783 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) 1784 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1785 1786 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1787 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1788 1789 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1790 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1791 1792 } 1793 1794 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1795 { 1796 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1797 1798 /* 1799 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1800 * but the fault handler will trigger the devcore dump, and we want 1801 * to otherwise resume normally rather than killing the submit, so 1802 * just bail. 1803 */ 1804 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1805 return; 1806 1807 DRM_DEV_ERROR(&gpu->pdev->dev, 1808 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1809 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1810 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1811 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1812 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1813 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1814 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1815 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1816 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1817 1818 /* Turn off the hangcheck timer to keep it from bothering us */ 1819 timer_delete(&gpu->hangcheck_timer); 1820 1821 /* Turn off interrupts to avoid triggering recovery again */ 1822 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 0); 1823 1824 kthread_queue_work(gpu->worker, &gpu->recover_work); 1825 } 1826 1827 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1828 { 1829 u32 status; 1830 1831 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); 1832 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); 1833 1834 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1835 1836 /* 1837 * Ignore FASTBLEND violations, because the HW will silently fall back 1838 * to legacy blending. 1839 */ 1840 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1841 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1842 timer_delete(&gpu->hangcheck_timer); 1843 1844 kthread_queue_work(gpu->worker, &gpu->recover_work); 1845 } 1846 } 1847 1848 static void a6xx_gpu_keepalive_vote(struct msm_gpu *gpu, bool on) 1849 { 1850 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1851 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1852 1853 if (adreno_has_gmu_wrapper(adreno_gpu)) 1854 return; 1855 1856 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, on); 1857 } 1858 1859 static int irq_poll_fence(struct msm_gpu *gpu) 1860 { 1861 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1862 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1863 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1864 u32 status; 1865 1866 if (adreno_has_gmu_wrapper(adreno_gpu)) 1867 return 0; 1868 1869 if (gmu_poll_timeout_atomic(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, status, !status, 1, 100)) { 1870 u32 rbbm_unmasked = gmu_read(gmu, REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS); 1871 1872 dev_err_ratelimited(&gpu->pdev->dev, 1873 "irq fence poll timeout, fence_ctrl=0x%x, unmasked_status=0x%x\n", 1874 status, rbbm_unmasked); 1875 return -ETIMEDOUT; 1876 } 1877 1878 return 0; 1879 } 1880 1881 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1882 { 1883 struct msm_drm_private *priv = gpu->dev->dev_private; 1884 1885 /* Set keepalive vote to avoid power collapse after RBBM_INT_0_STATUS is read */ 1886 a6xx_gpu_keepalive_vote(gpu, true); 1887 1888 if (irq_poll_fence(gpu)) 1889 goto done; 1890 1891 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1892 1893 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1894 1895 if (priv->disable_err_irq) 1896 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1897 1898 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1899 a6xx_fault_detect_irq(gpu); 1900 1901 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1902 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1903 1904 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1905 a6xx_cp_hw_err_irq(gpu); 1906 1907 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1908 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1909 1910 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1911 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1912 1913 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1914 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1915 1916 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1917 a7xx_sw_fuse_violation_irq(gpu); 1918 1919 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { 1920 msm_gpu_retire(gpu); 1921 a6xx_preempt_trigger(gpu); 1922 } 1923 1924 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1925 a6xx_preempt_irq(gpu); 1926 1927 done: 1928 a6xx_gpu_keepalive_vote(gpu, false); 1929 1930 return IRQ_HANDLED; 1931 } 1932 1933 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1934 { 1935 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1936 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1937 } 1938 1939 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1940 { 1941 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1942 struct msm_gpu *gpu = &adreno_gpu->base; 1943 u32 cntl1_regval = 0; 1944 1945 if (IS_ERR(a6xx_gpu->llc_mmio)) 1946 return; 1947 1948 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1949 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1950 1951 gpu_scid &= 0x1f; 1952 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1953 (gpu_scid << 15) | (gpu_scid << 20); 1954 1955 /* On A660, the SCID programming for UCHE traffic is done in 1956 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1957 */ 1958 if (adreno_is_a660_family(adreno_gpu)) 1959 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1960 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1961 } 1962 1963 /* 1964 * For targets with a MMU500, activate the slice but don't program the 1965 * register. The XBL will take care of that. 1966 */ 1967 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1968 if (!a6xx_gpu->have_mmu500) { 1969 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1970 1971 gpuhtw_scid &= 0x1f; 1972 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1973 } 1974 } 1975 1976 if (!cntl1_regval) 1977 return; 1978 1979 /* 1980 * Program the slice IDs for the various GPU blocks and GPU MMU 1981 * pagetables 1982 */ 1983 if (!a6xx_gpu->have_mmu500) { 1984 a6xx_llc_write(a6xx_gpu, 1985 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1986 1987 /* 1988 * Program cacheability overrides to not allocate cache 1989 * lines on a write miss 1990 */ 1991 a6xx_llc_rmw(a6xx_gpu, 1992 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1993 return; 1994 } 1995 1996 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1997 } 1998 1999 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 2000 { 2001 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 2002 struct msm_gpu *gpu = &adreno_gpu->base; 2003 2004 if (IS_ERR(a6xx_gpu->llc_mmio)) 2005 return; 2006 2007 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 2008 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 2009 2010 gpu_scid &= GENMASK(4, 0); 2011 2012 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 2013 FIELD_PREP(GENMASK(29, 25), gpu_scid) | 2014 FIELD_PREP(GENMASK(24, 20), gpu_scid) | 2015 FIELD_PREP(GENMASK(19, 15), gpu_scid) | 2016 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 2017 FIELD_PREP(GENMASK(9, 5), gpu_scid) | 2018 FIELD_PREP(GENMASK(4, 0), gpu_scid)); 2019 2020 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 2021 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 2022 BIT(8)); 2023 } 2024 2025 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 2026 } 2027 2028 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 2029 { 2030 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 2031 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 2032 return; 2033 2034 llcc_slice_putd(a6xx_gpu->llc_slice); 2035 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 2036 } 2037 2038 static void a6xx_llc_slices_init(struct platform_device *pdev, 2039 struct a6xx_gpu *a6xx_gpu, bool is_a7xx) 2040 { 2041 struct device_node *phandle; 2042 2043 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 2044 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 2045 return; 2046 2047 /* 2048 * There is a different programming path for A6xx targets with an 2049 * mmu500 attached, so detect if that is the case 2050 */ 2051 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 2052 a6xx_gpu->have_mmu500 = (phandle && 2053 of_device_is_compatible(phandle, "arm,mmu-500")); 2054 of_node_put(phandle); 2055 2056 if (is_a7xx || !a6xx_gpu->have_mmu500) 2057 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); 2058 else 2059 a6xx_gpu->llc_mmio = NULL; 2060 2061 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 2062 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 2063 2064 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 2065 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 2066 } 2067 2068 static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) 2069 { 2070 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 2071 struct msm_gpu *gpu = &adreno_gpu->base; 2072 u32 fuse_val; 2073 int ret; 2074 2075 if (adreno_is_a750(adreno_gpu)) { 2076 /* 2077 * Assume that if qcom scm isn't available, that whatever 2078 * replacement allows writing the fuse register ourselves. 2079 * Users of alternative firmware need to make sure this 2080 * register is writeable or indicate that it's not somehow. 2081 * Print a warning because if you mess this up you're about to 2082 * crash horribly. 2083 */ 2084 if (!qcom_scm_is_available()) { 2085 dev_warn_once(gpu->dev->dev, 2086 "SCM is not available, poking fuse register\n"); 2087 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, 2088 A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 2089 A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | 2090 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); 2091 adreno_gpu->has_ray_tracing = true; 2092 return 0; 2093 } 2094 2095 ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | 2096 QCOM_SCM_GPU_TSENSE_EN_REQ); 2097 if (ret) 2098 return ret; 2099 2100 /* 2101 * On a750 raytracing may be disabled by the firmware, find out 2102 * whether that's the case. The scm call above sets the fuse 2103 * register. 2104 */ 2105 fuse_val = a6xx_llc_read(a6xx_gpu, 2106 REG_A7XX_CX_MISC_SW_FUSE_VALUE); 2107 adreno_gpu->has_ray_tracing = 2108 !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); 2109 } else if (adreno_is_a740(adreno_gpu)) { 2110 /* Raytracing is always enabled on a740 */ 2111 adreno_gpu->has_ray_tracing = true; 2112 } 2113 2114 return 0; 2115 } 2116 2117 2118 #define GBIF_CLIENT_HALT_MASK BIT(0) 2119 #define GBIF_ARB_HALT_MASK BIT(1) 2120 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 2121 #define VBIF_RESET_ACK_MASK 0xF0 2122 #define GPR0_GBIF_HALT_REQUEST 0x1E0 2123 2124 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 2125 { 2126 struct msm_gpu *gpu = &adreno_gpu->base; 2127 2128 if (adreno_is_a619_holi(adreno_gpu)) { 2129 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 2130 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 2131 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 2132 } else if (!a6xx_has_gbif(adreno_gpu)) { 2133 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 2134 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 2135 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 2136 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 2137 2138 return; 2139 } 2140 2141 if (gx_off) { 2142 /* Halt the gx side of GBIF */ 2143 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 2144 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 2145 } 2146 2147 /* Halt new client requests on GBIF */ 2148 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 2149 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 2150 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 2151 2152 /* Halt all AXI requests on GBIF */ 2153 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 2154 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 2155 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 2156 2157 /* The GBIF halt needs to be explicitly cleared */ 2158 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 2159 } 2160 2161 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 2162 { 2163 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 2164 if (adreno_is_a610(to_adreno_gpu(gpu))) 2165 return; 2166 2167 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 2168 /* Perform a bogus read and add a brief delay to ensure ordering. */ 2169 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 2170 udelay(1); 2171 2172 /* The reset line needs to be asserted for at least 100 us */ 2173 if (assert) 2174 udelay(100); 2175 } 2176 2177 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 2178 { 2179 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2180 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2181 int ret; 2182 2183 gpu->needs_hw_init = true; 2184 2185 trace_msm_gpu_resume(0); 2186 2187 mutex_lock(&a6xx_gpu->gmu.lock); 2188 ret = a6xx_gmu_resume(a6xx_gpu); 2189 mutex_unlock(&a6xx_gpu->gmu.lock); 2190 if (ret) 2191 return ret; 2192 2193 msm_devfreq_resume(gpu); 2194 2195 adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu); 2196 2197 return ret; 2198 } 2199 2200 static int a6xx_pm_resume(struct msm_gpu *gpu) 2201 { 2202 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2203 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2204 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2205 unsigned long freq = gpu->fast_rate; 2206 struct dev_pm_opp *opp; 2207 int ret; 2208 2209 gpu->needs_hw_init = true; 2210 2211 trace_msm_gpu_resume(0); 2212 2213 mutex_lock(&a6xx_gpu->gmu.lock); 2214 2215 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 2216 if (IS_ERR(opp)) { 2217 ret = PTR_ERR(opp); 2218 goto err_set_opp; 2219 } 2220 dev_pm_opp_put(opp); 2221 2222 /* Set the core clock and bus bw, having VDD scaling in mind */ 2223 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 2224 2225 pm_runtime_resume_and_get(gmu->dev); 2226 pm_runtime_resume_and_get(gmu->gxpd); 2227 2228 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 2229 if (ret) 2230 goto err_bulk_clk; 2231 2232 if (adreno_is_a619_holi(adreno_gpu)) 2233 a6xx_sptprac_enable(gmu); 2234 2235 /* If anything goes south, tear the GPU down piece by piece.. */ 2236 if (ret) { 2237 err_bulk_clk: 2238 pm_runtime_put(gmu->gxpd); 2239 pm_runtime_put(gmu->dev); 2240 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2241 } 2242 err_set_opp: 2243 mutex_unlock(&a6xx_gpu->gmu.lock); 2244 2245 if (!ret) 2246 msm_devfreq_resume(gpu); 2247 2248 return ret; 2249 } 2250 2251 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 2252 { 2253 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2254 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2255 int i, ret; 2256 2257 trace_msm_gpu_suspend(0); 2258 2259 a6xx_llc_deactivate(a6xx_gpu); 2260 2261 msm_devfreq_suspend(gpu); 2262 2263 mutex_lock(&a6xx_gpu->gmu.lock); 2264 ret = a6xx_gmu_stop(a6xx_gpu); 2265 mutex_unlock(&a6xx_gpu->gmu.lock); 2266 if (ret) 2267 return ret; 2268 2269 if (a6xx_gpu->shadow_bo) 2270 for (i = 0; i < gpu->nr_rings; i++) 2271 a6xx_gpu->shadow[i] = 0; 2272 2273 gpu->suspend_count++; 2274 2275 return 0; 2276 } 2277 2278 static int a6xx_pm_suspend(struct msm_gpu *gpu) 2279 { 2280 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2281 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2282 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2283 int i; 2284 2285 trace_msm_gpu_suspend(0); 2286 2287 msm_devfreq_suspend(gpu); 2288 2289 mutex_lock(&a6xx_gpu->gmu.lock); 2290 2291 /* Drain the outstanding traffic on memory buses */ 2292 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 2293 2294 if (adreno_is_a619_holi(adreno_gpu)) 2295 a6xx_sptprac_disable(gmu); 2296 2297 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2298 2299 pm_runtime_put_sync(gmu->gxpd); 2300 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2301 pm_runtime_put_sync(gmu->dev); 2302 2303 mutex_unlock(&a6xx_gpu->gmu.lock); 2304 2305 if (a6xx_gpu->shadow_bo) 2306 for (i = 0; i < gpu->nr_rings; i++) 2307 a6xx_gpu->shadow[i] = 0; 2308 2309 gpu->suspend_count++; 2310 2311 return 0; 2312 } 2313 2314 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2315 { 2316 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2317 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2318 2319 *value = read_gmu_ao_counter(a6xx_gpu); 2320 2321 return 0; 2322 } 2323 2324 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2325 { 2326 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2327 return 0; 2328 } 2329 2330 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 2331 { 2332 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2333 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2334 2335 return a6xx_gpu->cur_ring; 2336 } 2337 2338 static void a6xx_destroy(struct msm_gpu *gpu) 2339 { 2340 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2341 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2342 2343 if (a6xx_gpu->sqe_bo) { 2344 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm); 2345 drm_gem_object_put(a6xx_gpu->sqe_bo); 2346 } 2347 2348 if (a6xx_gpu->shadow_bo) { 2349 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm); 2350 drm_gem_object_put(a6xx_gpu->shadow_bo); 2351 } 2352 2353 a6xx_llc_slices_destroy(a6xx_gpu); 2354 2355 a6xx_gmu_remove(a6xx_gpu); 2356 2357 adreno_gpu_cleanup(adreno_gpu); 2358 2359 kfree(a6xx_gpu); 2360 } 2361 2362 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2363 { 2364 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2365 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2366 u64 busy_cycles; 2367 2368 /* 19.2MHz */ 2369 *out_sample_rate = 19200000; 2370 2371 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2372 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2373 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2374 2375 return busy_cycles; 2376 } 2377 2378 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2379 bool suspended) 2380 { 2381 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2382 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2383 2384 mutex_lock(&a6xx_gpu->gmu.lock); 2385 a6xx_gmu_set_freq(gpu, opp, suspended); 2386 mutex_unlock(&a6xx_gpu->gmu.lock); 2387 } 2388 2389 static struct drm_gpuvm * 2390 a6xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev) 2391 { 2392 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2393 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2394 unsigned long quirks = 0; 2395 2396 /* 2397 * This allows GPU to set the bus attributes required to use system 2398 * cache on behalf of the iommu page table walker. 2399 */ 2400 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2401 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2402 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2403 2404 return adreno_iommu_create_vm(gpu, pdev, quirks); 2405 } 2406 2407 static struct drm_gpuvm * 2408 a6xx_create_private_vm(struct msm_gpu *gpu, bool kernel_managed) 2409 { 2410 struct msm_mmu *mmu; 2411 2412 mmu = msm_iommu_pagetable_create(to_msm_vm(gpu->vm)->mmu, kernel_managed); 2413 2414 if (IS_ERR(mmu)) 2415 return ERR_CAST(mmu); 2416 2417 return msm_gem_vm_create(gpu->dev, mmu, "gpu", ADRENO_VM_START, 2418 adreno_private_vm_size(gpu), kernel_managed); 2419 } 2420 2421 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2422 { 2423 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2424 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2425 2426 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2427 return a6xx_gpu->shadow[ring->id]; 2428 2429 /* 2430 * This is true only on an A6XX_GEN1 with GMU, has IFPC enabled and a super old SQE firmware 2431 * without 'whereami' support 2432 */ 2433 WARN_ONCE((to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC), 2434 "Can't read CP_RB_RPTR register reliably\n"); 2435 2436 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2437 } 2438 2439 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2440 { 2441 struct msm_cp_state cp_state; 2442 bool progress; 2443 2444 /* 2445 * With IFPC, KMD doesn't know whether GX power domain is collapsed 2446 * or not. So, we can't blindly read the below registers in GX domain. 2447 * Lets trust the hang detection in HW and lie to the caller that 2448 * there was progress. 2449 */ 2450 if (to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC) 2451 return true; 2452 2453 cp_state = (struct msm_cp_state) { 2454 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2455 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2456 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2457 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2458 }; 2459 2460 /* 2461 * Adjust the remaining data to account for what has already been 2462 * fetched from memory, but not yet consumed by the SQE. 2463 * 2464 * This is not *technically* correct, the amount buffered could 2465 * exceed the IB size due to hw prefetching ahead, but: 2466 * 2467 * (1) We aren't trying to find the exact position, just whether 2468 * progress has been made 2469 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2470 * to prevent prefetching into an unrelated submit. (And 2471 * either way, at some point the ROQ will be full.) 2472 */ 2473 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2474 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2475 2476 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2477 2478 ring->last_cp_state = cp_state; 2479 2480 return progress; 2481 } 2482 2483 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) 2484 { 2485 if (!info->speedbins) 2486 return UINT_MAX; 2487 2488 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) 2489 if (info->speedbins[i].fuse == fuse) 2490 return BIT(info->speedbins[i].speedbin); 2491 2492 return UINT_MAX; 2493 } 2494 2495 static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) 2496 { 2497 u32 supp_hw; 2498 u32 speedbin; 2499 int ret; 2500 2501 ret = adreno_read_speedbin(dev, &speedbin); 2502 /* 2503 * -ENOENT means that the platform doesn't support speedbin which is 2504 * fine 2505 */ 2506 if (ret == -ENOENT) { 2507 return 0; 2508 } else if (ret) { 2509 dev_err_probe(dev, ret, 2510 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2511 return ret; 2512 } 2513 2514 supp_hw = fuse_to_supp_hw(info, speedbin); 2515 2516 if (supp_hw == UINT_MAX) { 2517 DRM_DEV_ERROR(dev, 2518 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2519 speedbin); 2520 supp_hw = BIT(0); /* Default */ 2521 } 2522 2523 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2524 if (ret) 2525 return ret; 2526 2527 return 0; 2528 } 2529 2530 static const struct adreno_gpu_funcs funcs = { 2531 .base = { 2532 .get_param = adreno_get_param, 2533 .set_param = adreno_set_param, 2534 .hw_init = a6xx_hw_init, 2535 .ucode_load = a6xx_ucode_load, 2536 .pm_suspend = a6xx_gmu_pm_suspend, 2537 .pm_resume = a6xx_gmu_pm_resume, 2538 .recover = a6xx_recover, 2539 .submit = a6xx_submit, 2540 .active_ring = a6xx_active_ring, 2541 .irq = a6xx_irq, 2542 .destroy = a6xx_destroy, 2543 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2544 .show = a6xx_show, 2545 #endif 2546 .gpu_busy = a6xx_gpu_busy, 2547 .gpu_get_freq = a6xx_gmu_get_freq, 2548 .gpu_set_freq = a6xx_gpu_set_freq, 2549 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2550 .gpu_state_get = a6xx_gpu_state_get, 2551 .gpu_state_put = a6xx_gpu_state_put, 2552 #endif 2553 .create_vm = a6xx_create_vm, 2554 .create_private_vm = a6xx_create_private_vm, 2555 .get_rptr = a6xx_get_rptr, 2556 .progress = a6xx_progress, 2557 .sysprof_setup = a6xx_gmu_sysprof_setup, 2558 }, 2559 .get_timestamp = a6xx_gmu_get_timestamp, 2560 }; 2561 2562 static const struct adreno_gpu_funcs funcs_gmuwrapper = { 2563 .base = { 2564 .get_param = adreno_get_param, 2565 .set_param = adreno_set_param, 2566 .hw_init = a6xx_hw_init, 2567 .ucode_load = a6xx_ucode_load, 2568 .pm_suspend = a6xx_pm_suspend, 2569 .pm_resume = a6xx_pm_resume, 2570 .recover = a6xx_recover, 2571 .submit = a6xx_submit, 2572 .active_ring = a6xx_active_ring, 2573 .irq = a6xx_irq, 2574 .destroy = a6xx_destroy, 2575 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2576 .show = a6xx_show, 2577 #endif 2578 .gpu_busy = a6xx_gpu_busy, 2579 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2580 .gpu_state_get = a6xx_gpu_state_get, 2581 .gpu_state_put = a6xx_gpu_state_put, 2582 #endif 2583 .create_vm = a6xx_create_vm, 2584 .create_private_vm = a6xx_create_private_vm, 2585 .get_rptr = a6xx_get_rptr, 2586 .progress = a6xx_progress, 2587 }, 2588 .get_timestamp = a6xx_get_timestamp, 2589 }; 2590 2591 static const struct adreno_gpu_funcs funcs_a7xx = { 2592 .base = { 2593 .get_param = adreno_get_param, 2594 .set_param = adreno_set_param, 2595 .hw_init = a6xx_hw_init, 2596 .ucode_load = a6xx_ucode_load, 2597 .pm_suspend = a6xx_gmu_pm_suspend, 2598 .pm_resume = a6xx_gmu_pm_resume, 2599 .recover = a6xx_recover, 2600 .submit = a7xx_submit, 2601 .active_ring = a6xx_active_ring, 2602 .irq = a6xx_irq, 2603 .destroy = a6xx_destroy, 2604 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2605 .show = a6xx_show, 2606 #endif 2607 .gpu_busy = a6xx_gpu_busy, 2608 .gpu_get_freq = a6xx_gmu_get_freq, 2609 .gpu_set_freq = a6xx_gpu_set_freq, 2610 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2611 .gpu_state_get = a6xx_gpu_state_get, 2612 .gpu_state_put = a6xx_gpu_state_put, 2613 #endif 2614 .create_vm = a6xx_create_vm, 2615 .create_private_vm = a6xx_create_private_vm, 2616 .get_rptr = a6xx_get_rptr, 2617 .progress = a6xx_progress, 2618 .sysprof_setup = a6xx_gmu_sysprof_setup, 2619 }, 2620 .get_timestamp = a6xx_gmu_get_timestamp, 2621 }; 2622 2623 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2624 { 2625 struct msm_drm_private *priv = dev->dev_private; 2626 struct platform_device *pdev = priv->gpu_pdev; 2627 struct adreno_platform_config *config = pdev->dev.platform_data; 2628 struct device_node *node; 2629 struct a6xx_gpu *a6xx_gpu; 2630 struct adreno_gpu *adreno_gpu; 2631 struct msm_gpu *gpu; 2632 extern int enable_preemption; 2633 bool is_a7xx; 2634 int ret; 2635 2636 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 2637 if (!a6xx_gpu) 2638 return ERR_PTR(-ENOMEM); 2639 2640 adreno_gpu = &a6xx_gpu->base; 2641 gpu = &adreno_gpu->base; 2642 2643 mutex_init(&a6xx_gpu->gmu.lock); 2644 2645 adreno_gpu->registers = NULL; 2646 2647 /* Check if there is a GMU phandle and set it up */ 2648 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2649 /* FIXME: How do we gracefully handle this? */ 2650 BUG_ON(!node); 2651 2652 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2653 2654 adreno_gpu->base.hw_apriv = 2655 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); 2656 2657 /* gpu->info only gets assigned in adreno_gpu_init() */ 2658 is_a7xx = config->info->family == ADRENO_7XX_GEN1 || 2659 config->info->family == ADRENO_7XX_GEN2 || 2660 config->info->family == ADRENO_7XX_GEN3; 2661 2662 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); 2663 2664 ret = a6xx_set_supported_hw(&pdev->dev, config->info); 2665 if (ret) { 2666 a6xx_llc_slices_destroy(a6xx_gpu); 2667 kfree(a6xx_gpu); 2668 return ERR_PTR(ret); 2669 } 2670 2671 if ((enable_preemption == 1) || (enable_preemption == -1 && 2672 (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) 2673 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); 2674 else if (is_a7xx) 2675 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); 2676 else if (adreno_has_gmu_wrapper(adreno_gpu)) 2677 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); 2678 else 2679 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 2680 if (ret) { 2681 a6xx_destroy(&(a6xx_gpu->base.base)); 2682 return ERR_PTR(ret); 2683 } 2684 2685 /* 2686 * For now only clamp to idle freq for devices where this is known not 2687 * to cause power supply issues: 2688 */ 2689 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2690 priv->gpu_clamp_to_idle = true; 2691 2692 if (adreno_has_gmu_wrapper(adreno_gpu)) 2693 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2694 else 2695 ret = a6xx_gmu_init(a6xx_gpu, node); 2696 of_node_put(node); 2697 if (ret) { 2698 a6xx_destroy(&(a6xx_gpu->base.base)); 2699 return ERR_PTR(ret); 2700 } 2701 2702 if (adreno_is_a7xx(adreno_gpu)) { 2703 ret = a7xx_cx_mem_init(a6xx_gpu); 2704 if (ret) { 2705 a6xx_destroy(&(a6xx_gpu->base.base)); 2706 return ERR_PTR(ret); 2707 } 2708 } 2709 2710 adreno_gpu->uche_trap_base = 0x1fffffffff000ull; 2711 2712 msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, 2713 a6xx_fault_handler); 2714 2715 ret = a6xx_calc_ubwc_config(adreno_gpu); 2716 if (ret) { 2717 a6xx_destroy(&(a6xx_gpu->base.base)); 2718 return ERR_PTR(ret); 2719 } 2720 2721 /* Set up the preemption specific bits and pieces for each ringbuffer */ 2722 a6xx_preempt_init(gpu); 2723 2724 return gpu; 2725 } 2726