1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */ 3 4 #ifndef _A6XX_GMU_H_ 5 #define _A6XX_GMU_H_ 6 7 #include <linux/completion.h> 8 #include <linux/iopoll.h> 9 #include <linux/interrupt.h> 10 #include <linux/notifier.h> 11 #include <linux/soc/qcom/qcom_aoss.h> 12 #include "msm_drv.h" 13 #include "a6xx_hfi.h" 14 15 struct a6xx_gmu_bo { 16 struct drm_gem_object *obj; 17 void *virt; 18 size_t size; 19 u64 iova; 20 }; 21 22 #define GMU_MAX_GX_FREQS 16 23 #define GMU_MAX_CX_FREQS 4 24 #define GMU_MAX_BCMS 3 25 26 struct a6xx_bcm { 27 char *name; 28 unsigned int buswidth; 29 bool fixed; 30 unsigned int perfmode; 31 unsigned int perfmode_bw; 32 }; 33 34 /* 35 * These define the different GMU wake up options - these define how both the 36 * CPU and the GMU bring up the hardware 37 */ 38 39 /* THe GMU has already been booted and the rentention registers are active */ 40 #define GMU_WARM_BOOT 0 41 42 /* the GMU is coming up for the first time or back from a power collapse */ 43 #define GMU_COLD_BOOT 1 44 45 /* 46 * These define the level of control that the GMU has - the higher the number 47 * the more things that the GMU hardware controls on its own. 48 */ 49 50 /* The GMU does not do any idle state management */ 51 #define GMU_IDLE_STATE_ACTIVE 0 52 53 /* Unknown power state. Not exposed by the firmware. For documentation purpose only */ 54 #define GMU_IDLE_STATE_RESERVED 1 55 56 /* The GMU manages SPTP power collapse */ 57 #define GMU_IDLE_STATE_SPTP 2 58 59 /* The GMU does automatic IFPC (intra-frame power collapse) */ 60 #define GMU_IDLE_STATE_IFPC 3 61 62 struct a6xx_gmu { 63 struct device *dev; 64 65 /* For serializing communication with the GMU: */ 66 struct mutex lock; 67 68 struct drm_gpuvm *vm; 69 70 void __iomem *mmio; 71 void __iomem *rscc; 72 73 int hfi_irq; 74 int gmu_irq; 75 76 struct device *gxpd; 77 struct device *cxpd; 78 79 int idle_level; 80 81 struct a6xx_gmu_bo hfi; 82 struct a6xx_gmu_bo debug; 83 struct a6xx_gmu_bo icache; 84 struct a6xx_gmu_bo dcache; 85 struct a6xx_gmu_bo dummy; 86 struct a6xx_gmu_bo log; 87 88 int nr_clocks; 89 struct clk_bulk_data *clocks; 90 struct clk *core_clk; 91 struct clk *hub_clk; 92 93 /* current performance index set externally */ 94 int current_perf_index; 95 96 int nr_gpu_freqs; 97 unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; 98 u32 gx_arc_votes[GMU_MAX_GX_FREQS]; 99 struct a6xx_hfi_acd_table acd_table; 100 101 int nr_gpu_bws; 102 unsigned long gpu_bw_table[GMU_MAX_GX_FREQS]; 103 u32 gpu_ib_votes[GMU_MAX_GX_FREQS][GMU_MAX_BCMS]; 104 105 int nr_gmu_freqs; 106 unsigned long gmu_freqs[GMU_MAX_CX_FREQS]; 107 u32 cx_arc_votes[GMU_MAX_CX_FREQS]; 108 109 unsigned long freq; 110 111 struct a6xx_hfi_queue queues[2]; 112 113 bool initialized; 114 bool hung; 115 bool legacy; /* a618 or a630 */ 116 117 /* For power domain callback */ 118 struct notifier_block pd_nb; 119 struct completion pd_gate; 120 121 struct qmp *qmp; 122 struct a6xx_hfi_msg_bw_table *bw_table; 123 124 /* To check if we can trigger sleep seq at PDC. Cleared in a6xx_rpmh_stop() */ 125 #define GMU_STATUS_FW_START 0 126 /* To track if PDC sleep seq was done */ 127 #define GMU_STATUS_PDC_SLEEP 1 128 /* To track Perfcounter OOB set status */ 129 #define GMU_STATUS_OOB_PERF_SET 2 130 unsigned long status; 131 }; 132 133 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) 134 { 135 return readl(gmu->mmio + (offset << 2)); 136 } 137 138 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) 139 { 140 writel(value, gmu->mmio + (offset << 2)); 141 } 142 143 static inline void 144 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) 145 { 146 memcpy_toio(gmu->mmio + (offset << 2), data, size); 147 wmb(); 148 } 149 150 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) 151 { 152 u32 val = gmu_read(gmu, reg); 153 154 val &= ~mask; 155 156 gmu_write(gmu, reg, val | or); 157 } 158 159 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) 160 { 161 u64 val; 162 163 val = (u64) readl(gmu->mmio + (lo << 2)); 164 val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32); 165 166 return val; 167 } 168 169 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ 170 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ 171 interval, timeout) 172 #define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \ 173 readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \ 174 interval, timeout) 175 176 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) 177 { 178 return readl(gmu->rscc + (offset << 2)); 179 } 180 181 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) 182 { 183 writel(value, gmu->rscc + (offset << 2)); 184 } 185 186 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \ 187 readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \ 188 interval, timeout) 189 190 /* 191 * These are the available OOB (out of band requests) to the GMU where "out of 192 * band" means that the CPU talks to the GMU directly and not through HFI. 193 * Normally this works by writing a ITCM/DTCM register and then triggering a 194 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack" 195 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt. 196 * 197 * These are used to force the GMU/GPU to stay on during a critical sequence or 198 * for hardware workarounds. 199 */ 200 201 enum a6xx_gmu_oob_state { 202 /* 203 * Let the GMU know that a boot or slumber operation has started. The value in 204 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are 205 * doing 206 */ 207 GMU_OOB_BOOT_SLUMBER = 0, 208 /* 209 * Let the GMU know to not turn off any GPU registers while the CPU is in a 210 * critical section 211 */ 212 GMU_OOB_GPU_SET, 213 /* 214 * Set a new power level for the GPU when the CPU is doing frequency scaling 215 */ 216 GMU_OOB_DCVS_SET, 217 /* 218 * Used to keep the GPU on for CPU-side reads of performance counters. 219 */ 220 GMU_OOB_PERFCOUNTER_SET, 221 }; 222 223 void a6xx_hfi_init(struct a6xx_gmu *gmu); 224 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); 225 void a6xx_hfi_stop(struct a6xx_gmu *gmu); 226 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); 227 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index); 228 229 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); 230 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); 231 void a6xx_sptprac_disable(struct a6xx_gmu *gmu); 232 int a6xx_sptprac_enable(struct a6xx_gmu *gmu); 233 234 #endif 235