1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/interconnect.h> 7 #include <linux/of_platform.h> 8 #include <linux/platform_device.h> 9 #include <linux/pm_domain.h> 10 #include <linux/pm_opp.h> 11 #include <soc/qcom/cmd-db.h> 12 #include <soc/qcom/tcs.h> 13 #include <drm/drm_gem.h> 14 15 #include "a6xx_gpu.h" 16 #include "a6xx_gmu.xml.h" 17 #include "msm_gem.h" 18 #include "msm_gpu_trace.h" 19 #include "msm_mmu.h" 20 21 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 22 { 23 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 24 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 25 struct msm_gpu *gpu = &adreno_gpu->base; 26 27 /* FIXME: add a banner here */ 28 gmu->hung = true; 29 30 /* Turn off the hangcheck timer while we are resetting */ 31 del_timer(&gpu->hangcheck_timer); 32 33 /* Queue the GPU handler because we need to treat this as a recovery */ 34 kthread_queue_work(gpu->worker, &gpu->recover_work); 35 } 36 37 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 38 { 39 struct a6xx_gmu *gmu = data; 40 u32 status; 41 42 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 43 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 44 45 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 46 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 47 48 a6xx_gmu_fault(gmu); 49 } 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 52 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 53 54 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 55 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 56 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 57 58 return IRQ_HANDLED; 59 } 60 61 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 62 { 63 struct a6xx_gmu *gmu = data; 64 u32 status; 65 66 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 67 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 68 69 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 70 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 71 72 a6xx_gmu_fault(gmu); 73 } 74 75 return IRQ_HANDLED; 76 } 77 78 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 79 { 80 u32 val; 81 82 /* This can be called from gpu state code so make sure GMU is valid */ 83 if (!gmu->initialized) 84 return false; 85 86 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 87 88 return !(val & 89 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 90 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 91 } 92 93 /* Check to see if the GX rail is still powered */ 94 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 95 { 96 u32 val; 97 98 /* This can be called from gpu state code so make sure GMU is valid */ 99 if (!gmu->initialized) 100 return false; 101 102 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 103 104 return !(val & 105 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 106 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 107 } 108 109 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 110 bool suspended) 111 { 112 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 113 const struct a6xx_info *info = adreno_gpu->info->a6xx; 114 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 115 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 116 u32 perf_index; 117 u32 bw_index = 0; 118 unsigned long gpu_freq; 119 int ret = 0; 120 121 gpu_freq = dev_pm_opp_get_freq(opp); 122 123 if (gpu_freq == gmu->freq) 124 return; 125 126 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 127 if (gpu_freq == gmu->gpu_freqs[perf_index]) 128 break; 129 130 /* If enabled, find the corresponding DDR bandwidth index */ 131 if (info->bcms && gmu->nr_gpu_bws > 1) { 132 unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); 133 134 for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { 135 if (bw == gmu->gpu_bw_table[bw_index]) 136 break; 137 } 138 139 /* Vote AB as a fraction of the max bandwidth, starting from A750 */ 140 if (bw && adreno_is_a750_family(adreno_gpu)) { 141 u64 tmp; 142 143 /* For now, vote for 25% of the bandwidth */ 144 tmp = bw * 25; 145 do_div(tmp, 100); 146 147 /* 148 * The AB vote consists of a 16 bit wide quantized level 149 * against the maximum supported bandwidth. 150 * Quantization can be calculated as below: 151 * vote = (bandwidth * 2^16) / max bandwidth 152 */ 153 tmp *= MAX_AB_VOTE; 154 do_div(tmp, gmu->gpu_bw_table[gmu->nr_gpu_bws - 1]); 155 156 bw_index |= AB_VOTE(clamp(tmp, 1, MAX_AB_VOTE)); 157 bw_index |= AB_VOTE_ENABLE; 158 } 159 } 160 161 gmu->current_perf_index = perf_index; 162 gmu->freq = gmu->gpu_freqs[perf_index]; 163 164 trace_msm_gmu_freq_change(gmu->freq, perf_index); 165 166 /* 167 * This can get called from devfreq while the hardware is idle. Don't 168 * bring up the power if it isn't already active. All we're doing here 169 * is updating the frequency so that when we come back online we're at 170 * the right rate. 171 */ 172 if (suspended) 173 return; 174 175 if (!gmu->legacy) { 176 a6xx_hfi_set_freq(gmu, perf_index, bw_index); 177 /* With Bandwidth voting, we now vote for all resources, so skip OPP set */ 178 if (!bw_index) 179 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 180 return; 181 } 182 183 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 184 185 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 186 ((3 & 0xf) << 28) | perf_index); 187 188 /* 189 * Send an invalid index as a vote for the bus bandwidth and let the 190 * firmware decide on the right vote 191 */ 192 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 193 194 /* Set and clear the OOB for DCVS to trigger the GMU */ 195 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 196 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 197 198 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 199 if (ret) 200 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 201 202 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 203 } 204 205 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 206 { 207 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 208 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 209 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 210 211 return gmu->freq; 212 } 213 214 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 215 { 216 u32 val; 217 int local = gmu->idle_level; 218 219 /* SPTP and IFPC both report as IFPC */ 220 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 221 local = GMU_IDLE_STATE_IFPC; 222 223 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 224 225 if (val == local) { 226 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 227 !a6xx_gmu_gx_is_on(gmu)) 228 return true; 229 } 230 231 return false; 232 } 233 234 /* Wait for the GMU to get to its most idle state */ 235 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 236 { 237 return spin_until(a6xx_gmu_check_idle_level(gmu)); 238 } 239 240 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 241 { 242 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 243 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 244 u32 mask, reset_val, val; 245 int ret; 246 247 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); 248 if (val <= 0x20010004) { 249 mask = 0xffffffff; 250 reset_val = 0xbabeface; 251 } else { 252 mask = 0x1ff; 253 reset_val = 0x100; 254 } 255 256 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 257 258 /* Set the log wptr index 259 * note: downstream saves the value in poweroff and restores it here 260 */ 261 if (adreno_is_a7xx(adreno_gpu)) 262 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); 263 else 264 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 265 266 267 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 268 269 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 270 (val & mask) == reset_val, 100, 10000); 271 272 if (ret) 273 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 274 275 return ret; 276 } 277 278 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 279 { 280 u32 val; 281 int ret; 282 283 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 284 285 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 286 val & 1, 100, 10000); 287 if (ret) 288 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 289 290 return ret; 291 } 292 293 struct a6xx_gmu_oob_bits { 294 int set, ack, set_new, ack_new, clear, clear_new; 295 const char *name; 296 }; 297 298 /* These are the interrupt / ack bits for each OOB request that are set 299 * in a6xx_gmu_set_oob and a6xx_clear_oob 300 */ 301 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { 302 [GMU_OOB_GPU_SET] = { 303 .name = "GPU_SET", 304 .set = 16, 305 .ack = 24, 306 .set_new = 30, 307 .ack_new = 31, 308 .clear = 24, 309 .clear_new = 31, 310 }, 311 312 [GMU_OOB_PERFCOUNTER_SET] = { 313 .name = "PERFCOUNTER", 314 .set = 17, 315 .ack = 25, 316 .set_new = 28, 317 .ack_new = 30, 318 .clear = 25, 319 .clear_new = 29, 320 }, 321 322 [GMU_OOB_BOOT_SLUMBER] = { 323 .name = "BOOT_SLUMBER", 324 .set = 22, 325 .ack = 30, 326 .clear = 30, 327 }, 328 329 [GMU_OOB_DCVS_SET] = { 330 .name = "GPU_DCVS", 331 .set = 23, 332 .ack = 31, 333 .clear = 31, 334 }, 335 }; 336 337 /* Trigger a OOB (out of band) request to the GMU */ 338 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 339 { 340 int ret; 341 u32 val; 342 int request, ack; 343 344 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); 345 346 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) 347 return -EINVAL; 348 349 if (gmu->legacy) { 350 request = a6xx_gmu_oob_bits[state].set; 351 ack = a6xx_gmu_oob_bits[state].ack; 352 } else { 353 request = a6xx_gmu_oob_bits[state].set_new; 354 ack = a6xx_gmu_oob_bits[state].ack_new; 355 if (!request || !ack) { 356 DRM_DEV_ERROR(gmu->dev, 357 "Invalid non-legacy GMU request %s\n", 358 a6xx_gmu_oob_bits[state].name); 359 return -EINVAL; 360 } 361 } 362 363 /* Trigger the equested OOB operation */ 364 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 365 366 /* Wait for the acknowledge interrupt */ 367 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 368 val & (1 << ack), 100, 10000); 369 370 if (ret) 371 DRM_DEV_ERROR(gmu->dev, 372 "Timeout waiting for GMU OOB set %s: 0x%x\n", 373 a6xx_gmu_oob_bits[state].name, 374 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 375 376 /* Clear the acknowledge interrupt */ 377 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 378 379 return ret; 380 } 381 382 /* Clear a pending OOB state in the GMU */ 383 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 384 { 385 int bit; 386 387 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); 388 389 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) 390 return; 391 392 if (gmu->legacy) 393 bit = a6xx_gmu_oob_bits[state].clear; 394 else 395 bit = a6xx_gmu_oob_bits[state].clear_new; 396 397 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); 398 } 399 400 /* Enable CPU control of SPTP power power collapse */ 401 int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 402 { 403 int ret; 404 u32 val; 405 406 if (!gmu->legacy) 407 return 0; 408 409 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 410 411 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 412 (val & 0x38) == 0x28, 1, 100); 413 414 if (ret) { 415 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 416 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 417 } 418 419 return 0; 420 } 421 422 /* Disable CPU control of SPTP power power collapse */ 423 void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 424 { 425 u32 val; 426 int ret; 427 428 if (!gmu->legacy) 429 return; 430 431 /* Make sure retention is on */ 432 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 433 434 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 435 436 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 437 (val & 0x04), 100, 10000); 438 439 if (ret) 440 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 441 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 442 } 443 444 /* Let the GMU know we are starting a boot sequence */ 445 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 446 { 447 u32 vote; 448 449 /* Let the GMU know we are getting ready for boot */ 450 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 451 452 /* Choose the "default" power level as the highest available */ 453 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 454 455 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 456 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 457 458 /* Let the GMU know the boot sequence has started */ 459 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 460 } 461 462 static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) 463 { 464 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 465 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 466 467 /* 468 * GEMNoC can power collapse whilst the GPU is being powered down, resulting 469 * in the power down sequence not being fully executed. That in turn can 470 * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. 471 */ 472 if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 473 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); 474 } 475 476 /* Let the GMU know that we are about to go into slumber */ 477 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 478 { 479 int ret; 480 481 /* Disable the power counter so the GMU isn't busy */ 482 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 483 484 /* Disable SPTP_PC if the CPU is responsible for it */ 485 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 486 a6xx_sptprac_disable(gmu); 487 488 if (!gmu->legacy) { 489 ret = a6xx_hfi_send_prep_slumber(gmu); 490 goto out; 491 } 492 493 /* Tell the GMU to get ready to slumber */ 494 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 495 496 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 497 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 498 499 if (!ret) { 500 /* Check to see if the GMU really did slumber */ 501 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 502 != 0x0f) { 503 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 504 ret = -ETIMEDOUT; 505 } 506 } 507 508 out: 509 a6xx_gemnoc_workaround(gmu); 510 511 /* Put fence into allow mode */ 512 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 513 return ret; 514 } 515 516 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 517 { 518 int ret; 519 u32 val; 520 521 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1)); 522 523 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 524 val & (1 << 1), 100, 10000); 525 if (ret) { 526 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 527 return ret; 528 } 529 530 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 531 !val, 100, 10000); 532 533 if (ret) { 534 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 535 return ret; 536 } 537 538 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 539 540 return 0; 541 } 542 543 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 544 { 545 int ret; 546 u32 val; 547 548 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 549 550 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 551 val, val & (1 << 16), 100, 10000); 552 if (ret) 553 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 554 555 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 556 } 557 558 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 559 { 560 writel(value, ptr + (offset << 2)); 561 } 562 563 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 564 const char *name); 565 566 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 567 { 568 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 569 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 570 struct platform_device *pdev = to_platform_device(gmu->dev); 571 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 572 u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0; 573 void __iomem *seqptr = NULL; 574 uint32_t pdc_address_offset; 575 bool pdc_in_aop = false; 576 577 if (IS_ERR(pdcptr)) 578 goto err; 579 580 if (adreno_is_a650_family(adreno_gpu) || 581 adreno_is_a7xx(adreno_gpu)) 582 pdc_in_aop = true; 583 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu)) 584 pdc_address_offset = 0x30090; 585 else if (adreno_is_a619(adreno_gpu)) 586 pdc_address_offset = 0x300a0; 587 else 588 pdc_address_offset = 0x30080; 589 590 if (!pdc_in_aop) { 591 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 592 if (IS_ERR(seqptr)) 593 goto err; 594 } 595 596 /* Disable SDE clock gating */ 597 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 598 599 /* Setup RSC PDC handshake for sleep and wakeup */ 600 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 601 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 602 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 603 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 604 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 605 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 606 adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000); 607 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 608 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 609 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 610 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 611 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 612 613 /* The second spin of A7xx GPUs messed with some register offsets.. */ 614 if (adreno_is_a740_family(adreno_gpu)) 615 seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740; 616 617 /* Load RSC sequencer uCode for sleep and wakeup */ 618 if (adreno_is_a650_family(adreno_gpu) || 619 adreno_is_a7xx(adreno_gpu)) { 620 gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0); 621 gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab); 622 gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581); 623 gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2); 624 gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad); 625 } else { 626 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 627 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 628 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 629 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 630 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 631 } 632 633 if (pdc_in_aop) 634 goto setup_pdc; 635 636 /* Load PDC sequencer uCode for power up and power down sequence */ 637 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 638 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 639 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 640 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 641 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 642 643 /* Set TCS commands used by PDC sequence for low power modes */ 644 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 645 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 646 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 647 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 648 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 649 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 650 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 651 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 652 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 653 654 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 655 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 656 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 657 658 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 659 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 660 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 661 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 662 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 663 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 664 665 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 666 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 667 if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) || 668 adreno_is_a650_family(adreno_gpu)) 669 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 670 else 671 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 672 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 673 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 674 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 675 676 /* Setup GPU PDC */ 677 setup_pdc: 678 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 679 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 680 681 /* ensure no writes happen before the uCode is fully written */ 682 wmb(); 683 684 a6xx_rpmh_stop(gmu); 685 686 err: 687 if (!IS_ERR_OR_NULL(pdcptr)) 688 iounmap(pdcptr); 689 if (!IS_ERR_OR_NULL(seqptr)) 690 iounmap(seqptr); 691 } 692 693 /* 694 * The lowest 16 bits of this value are the number of XO clock cycles for main 695 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 696 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 697 */ 698 699 #define GMU_PWR_COL_HYST 0x000a1680 700 701 /* Set up the idle state for the GMU */ 702 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 703 { 704 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 705 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 706 707 /* Disable GMU WB/RB buffer */ 708 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 709 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 710 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 711 712 /* A7xx knows better by default! */ 713 if (adreno_is_a7xx(adreno_gpu)) 714 return; 715 716 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 717 718 switch (gmu->idle_level) { 719 case GMU_IDLE_STATE_IFPC: 720 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 721 GMU_PWR_COL_HYST); 722 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 723 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 724 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 725 fallthrough; 726 case GMU_IDLE_STATE_SPTP: 727 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 728 GMU_PWR_COL_HYST); 729 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 730 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 731 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 732 } 733 734 /* Enable RPMh GPU client */ 735 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 736 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 737 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 738 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 739 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 740 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 741 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 742 } 743 744 struct block_header { 745 u32 addr; 746 u32 size; 747 u32 type; 748 u32 value; 749 u32 data[]; 750 }; 751 752 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 753 { 754 if (!in_range(blk->addr, bo->iova, bo->size)) 755 return false; 756 757 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 758 return true; 759 } 760 761 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 762 { 763 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 764 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 765 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 766 const struct block_header *blk; 767 u32 reg_offset; 768 u32 ver; 769 770 u32 itcm_base = 0x00000000; 771 u32 dtcm_base = 0x00040000; 772 773 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 774 dtcm_base = 0x10004000; 775 776 if (gmu->legacy) { 777 /* Sanity check the size of the firmware that was loaded */ 778 if (fw_image->size > 0x8000) { 779 DRM_DEV_ERROR(gmu->dev, 780 "GMU firmware is bigger than the available region\n"); 781 return -EINVAL; 782 } 783 784 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 785 (u32*) fw_image->data, fw_image->size); 786 return 0; 787 } 788 789 790 for (blk = (const struct block_header *) fw_image->data; 791 (const u8*) blk < fw_image->data + fw_image->size; 792 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 793 if (blk->size == 0) 794 continue; 795 796 if (in_range(blk->addr, itcm_base, SZ_16K)) { 797 reg_offset = (blk->addr - itcm_base) >> 2; 798 gmu_write_bulk(gmu, 799 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 800 blk->data, blk->size); 801 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 802 reg_offset = (blk->addr - dtcm_base) >> 2; 803 gmu_write_bulk(gmu, 804 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 805 blk->data, blk->size); 806 } else if (!fw_block_mem(&gmu->icache, blk) && 807 !fw_block_mem(&gmu->dcache, blk) && 808 !fw_block_mem(&gmu->dummy, blk)) { 809 DRM_DEV_ERROR(gmu->dev, 810 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 811 blk->addr, blk->size, blk->data[0]); 812 } 813 } 814 815 ver = gmu_read(gmu, REG_A6XX_GMU_CORE_FW_VERSION); 816 DRM_INFO("Loaded GMU firmware v%u.%u.%u\n", 817 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MAJOR__MASK, ver), 818 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MINOR__MASK, ver), 819 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_STEP__MASK, ver)); 820 821 return 0; 822 } 823 824 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 825 { 826 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 827 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 828 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; 829 u32 fence_range_lower, fence_range_upper; 830 u32 chipid = 0; 831 int ret; 832 833 /* Vote veto for FAL10 */ 834 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { 835 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); 836 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 837 } 838 839 /* Turn on TCM (Tightly Coupled Memory) retention */ 840 if (adreno_is_a7xx(adreno_gpu)) 841 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); 842 else 843 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 844 845 if (state == GMU_WARM_BOOT) { 846 ret = a6xx_rpmh_start(gmu); 847 if (ret) 848 return ret; 849 } else { 850 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 851 "GMU firmware is not loaded\n")) 852 return -ENOENT; 853 854 ret = a6xx_rpmh_start(gmu); 855 if (ret) 856 return ret; 857 858 ret = a6xx_gmu_fw_load(gmu); 859 if (ret) 860 return ret; 861 } 862 863 /* Clear init result to make sure we are getting a fresh value */ 864 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 865 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 866 867 /* Write the iova of the HFI table */ 868 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 869 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 870 871 if (adreno_is_a7xx(adreno_gpu)) { 872 fence_range_upper = 0x32; 873 fence_range_lower = 0x8a0; 874 } else { 875 fence_range_upper = 0xa; 876 fence_range_lower = 0xa0; 877 } 878 879 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 880 BIT(31) | 881 FIELD_PREP(GENMASK(30, 18), fence_range_upper) | 882 FIELD_PREP(GENMASK(17, 0), fence_range_lower)); 883 884 /* 885 * Snapshots toggle the NMI bit which will result in a jump to the NMI 886 * handler instead of __main. Set the M3 config value to avoid that. 887 */ 888 gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); 889 890 if (a6xx_info->gmu_chipid) { 891 chipid = a6xx_info->gmu_chipid; 892 } else { 893 /* 894 * Note that the GMU has a slightly different layout for 895 * chip_id, for whatever reason, so a bit of massaging 896 * is needed. The upper 16b are the same, but minor and 897 * patchid are packed in four bits each with the lower 898 * 8b unused: 899 */ 900 chipid = adreno_gpu->chip_id & 0xffff0000; 901 chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ 902 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ 903 } 904 905 if (adreno_is_a7xx(adreno_gpu)) { 906 gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid); 907 gmu_write(gmu, REG_A7XX_GMU_GENERAL_8, 908 (gmu->log.iova & GENMASK(31, 12)) | 909 ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); 910 } else { 911 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 912 913 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 914 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 915 } 916 917 /* Set up the lowest idle level on the GMU */ 918 a6xx_gmu_power_config(gmu); 919 920 ret = a6xx_gmu_start(gmu); 921 if (ret) 922 return ret; 923 924 if (gmu->legacy) { 925 ret = a6xx_gmu_gfx_rail_on(gmu); 926 if (ret) 927 return ret; 928 } 929 930 /* Enable SPTP_PC if the CPU is responsible for it */ 931 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 932 ret = a6xx_sptprac_enable(gmu); 933 if (ret) 934 return ret; 935 } 936 937 ret = a6xx_gmu_hfi_start(gmu); 938 if (ret) 939 return ret; 940 941 /* FIXME: Do we need this wmb() here? */ 942 wmb(); 943 944 return 0; 945 } 946 947 #define A6XX_HFI_IRQ_MASK \ 948 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 949 950 #define A6XX_GMU_IRQ_MASK \ 951 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 952 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 953 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 954 955 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 956 { 957 disable_irq(gmu->gmu_irq); 958 disable_irq(gmu->hfi_irq); 959 960 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 961 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 962 } 963 964 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 965 { 966 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 967 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 968 u32 val, seqmem_off = 0; 969 970 /* The second spin of A7xx GPUs messed with some register offsets.. */ 971 if (adreno_is_a740_family(adreno_gpu)) 972 seqmem_off = 4; 973 974 /* Make sure there are no outstanding RPMh votes */ 975 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS + seqmem_off, 976 val, (val & 1), 100, 10000); 977 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS + seqmem_off, 978 val, (val & 1), 100, 10000); 979 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS + seqmem_off, 980 val, (val & 1), 100, 10000); 981 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, 982 val, (val & 1), 100, 1000); 983 } 984 985 /* Force the GMU off in case it isn't responsive */ 986 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 987 { 988 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 989 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 990 struct msm_gpu *gpu = &adreno_gpu->base; 991 992 /* 993 * Turn off keep alive that might have been enabled by the hang 994 * interrupt 995 */ 996 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 997 998 /* Flush all the queues */ 999 a6xx_hfi_stop(gmu); 1000 1001 /* Stop the interrupts */ 1002 a6xx_gmu_irq_disable(gmu); 1003 1004 /* Force off SPTP in case the GMU is managing it */ 1005 a6xx_sptprac_disable(gmu); 1006 1007 a6xx_gemnoc_workaround(gmu); 1008 1009 /* Make sure there are no outstanding RPMh votes */ 1010 a6xx_gmu_rpmh_off(gmu); 1011 1012 /* Clear the WRITEDROPPED fields and put fence into allow mode */ 1013 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7); 1014 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 1015 1016 /* Make sure the above writes go through */ 1017 wmb(); 1018 1019 /* Halt the gmu cm3 core */ 1020 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 1021 1022 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1023 1024 /* Reset GPU core blocks */ 1025 a6xx_gpu_sw_reset(gpu, true); 1026 } 1027 1028 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 1029 { 1030 struct dev_pm_opp *gpu_opp; 1031 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 1032 1033 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 1034 if (IS_ERR(gpu_opp)) 1035 return; 1036 1037 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ 1038 a6xx_gmu_set_freq(gpu, gpu_opp, false); 1039 dev_pm_opp_put(gpu_opp); 1040 } 1041 1042 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 1043 { 1044 struct dev_pm_opp *gpu_opp; 1045 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 1046 1047 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 1048 if (IS_ERR(gpu_opp)) 1049 return; 1050 1051 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp); 1052 dev_pm_opp_put(gpu_opp); 1053 } 1054 1055 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 1056 { 1057 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1058 struct msm_gpu *gpu = &adreno_gpu->base; 1059 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1060 int status, ret; 1061 1062 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 1063 return -EINVAL; 1064 1065 gmu->hung = false; 1066 1067 /* Notify AOSS about the ACD state (unimplemented for now => disable it) */ 1068 if (!IS_ERR(gmu->qmp)) { 1069 ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", 1070 0 /* Hardcode ACD to be disabled for now */); 1071 if (ret) 1072 dev_err(gmu->dev, "failed to send GPU ACD state\n"); 1073 } 1074 1075 /* Turn on the resources */ 1076 pm_runtime_get_sync(gmu->dev); 1077 1078 /* 1079 * "enable" the GX power domain which won't actually do anything but it 1080 * will make sure that the refcounting is correct in case we need to 1081 * bring down the GX after a GMU failure 1082 */ 1083 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1084 pm_runtime_get_sync(gmu->gxpd); 1085 1086 /* Use a known rate to bring up the GMU */ 1087 clk_set_rate(gmu->core_clk, 200000000); 1088 clk_set_rate(gmu->hub_clk, adreno_is_a740_family(adreno_gpu) ? 1089 200000000 : 150000000); 1090 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 1091 if (ret) { 1092 pm_runtime_put(gmu->gxpd); 1093 pm_runtime_put(gmu->dev); 1094 return ret; 1095 } 1096 1097 /* Set the bus quota to a reasonable value for boot */ 1098 a6xx_gmu_set_initial_bw(gpu, gmu); 1099 1100 /* Enable the GMU interrupt */ 1101 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 1102 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 1103 enable_irq(gmu->gmu_irq); 1104 1105 /* Check to see if we are doing a cold or warm boot */ 1106 if (adreno_is_a7xx(adreno_gpu)) { 1107 status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ? 1108 GMU_WARM_BOOT : GMU_COLD_BOOT; 1109 } else if (gmu->legacy) { 1110 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 1111 GMU_WARM_BOOT : GMU_COLD_BOOT; 1112 } else { 1113 /* 1114 * Warm boot path does not work on newer A6xx GPUs 1115 * Presumably this is because icache/dcache regions must be restored 1116 */ 1117 status = GMU_COLD_BOOT; 1118 } 1119 1120 ret = a6xx_gmu_fw_start(gmu, status); 1121 if (ret) 1122 goto out; 1123 1124 ret = a6xx_hfi_start(gmu, status); 1125 if (ret) 1126 goto out; 1127 1128 /* 1129 * Turn on the GMU firmware fault interrupt after we know the boot 1130 * sequence is successful 1131 */ 1132 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 1133 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 1134 enable_irq(gmu->hfi_irq); 1135 1136 /* Set the GPU to the current freq */ 1137 a6xx_gmu_set_initial_freq(gpu, gmu); 1138 1139 out: 1140 /* On failure, shut down the GMU to leave it in a good state */ 1141 if (ret) { 1142 disable_irq(gmu->gmu_irq); 1143 a6xx_rpmh_stop(gmu); 1144 pm_runtime_put(gmu->gxpd); 1145 pm_runtime_put(gmu->dev); 1146 } 1147 1148 return ret; 1149 } 1150 1151 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 1152 { 1153 u32 reg; 1154 1155 if (!gmu->initialized) 1156 return true; 1157 1158 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 1159 1160 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 1161 return false; 1162 1163 return true; 1164 } 1165 1166 /* Gracefully try to shut down the GMU and by extension the GPU */ 1167 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 1168 { 1169 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1170 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1171 u32 val; 1172 1173 /* 1174 * The GMU may still be in slumber unless the GPU started so check and 1175 * skip putting it back into slumber if so 1176 */ 1177 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 1178 1179 if (val != 0xf) { 1180 int ret = a6xx_gmu_wait_for_idle(gmu); 1181 1182 /* If the GMU isn't responding assume it is hung */ 1183 if (ret) { 1184 a6xx_gmu_force_off(gmu); 1185 return; 1186 } 1187 1188 a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung); 1189 1190 /* tell the GMU we want to slumber */ 1191 ret = a6xx_gmu_notify_slumber(gmu); 1192 if (ret) { 1193 a6xx_gmu_force_off(gmu); 1194 return; 1195 } 1196 1197 ret = gmu_poll_timeout(gmu, 1198 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 1199 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1200 100, 10000); 1201 1202 /* 1203 * Let the user know we failed to slumber but don't worry too 1204 * much because we are powering down anyway 1205 */ 1206 1207 if (ret) 1208 DRM_DEV_ERROR(gmu->dev, 1209 "Unable to slumber GMU: status = 0%x/0%x\n", 1210 gmu_read(gmu, 1211 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1212 gmu_read(gmu, 1213 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1214 } 1215 1216 /* Turn off HFI */ 1217 a6xx_hfi_stop(gmu); 1218 1219 /* Stop the interrupts and mask the hardware */ 1220 a6xx_gmu_irq_disable(gmu); 1221 1222 /* Tell RPMh to power off the GPU */ 1223 a6xx_rpmh_stop(gmu); 1224 } 1225 1226 1227 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1228 { 1229 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1230 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1231 1232 if (!pm_runtime_active(gmu->dev)) 1233 return 0; 1234 1235 /* 1236 * Force the GMU off if we detected a hang, otherwise try to shut it 1237 * down gracefully 1238 */ 1239 if (gmu->hung) 1240 a6xx_gmu_force_off(gmu); 1241 else 1242 a6xx_gmu_shutdown(gmu); 1243 1244 /* Remove the bus vote */ 1245 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 1246 1247 /* 1248 * Make sure the GX domain is off before turning off the GMU (CX) 1249 * domain. Usually the GMU does this but only if the shutdown sequence 1250 * was successful 1251 */ 1252 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1253 pm_runtime_put_sync(gmu->gxpd); 1254 1255 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1256 1257 pm_runtime_put_sync(gmu->dev); 1258 1259 return 0; 1260 } 1261 1262 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1263 { 1264 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace); 1265 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace); 1266 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace); 1267 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace); 1268 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace); 1269 msm_gem_kernel_put(gmu->log.obj, gmu->aspace); 1270 1271 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1272 msm_gem_address_space_put(gmu->aspace); 1273 } 1274 1275 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1276 size_t size, u64 iova, const char *name) 1277 { 1278 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1279 struct drm_device *dev = a6xx_gpu->base.base.dev; 1280 uint32_t flags = MSM_BO_WC; 1281 u64 range_start, range_end; 1282 int ret; 1283 1284 size = PAGE_ALIGN(size); 1285 if (!iova) { 1286 /* no fixed address - use GMU's uncached range */ 1287 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1288 range_end = 0x80000000; 1289 } else { 1290 /* range for fixed address */ 1291 range_start = iova; 1292 range_end = iova + size; 1293 /* use IOMMU_PRIV for icache/dcache */ 1294 flags |= MSM_BO_MAP_PRIV; 1295 } 1296 1297 bo->obj = msm_gem_new(dev, size, flags); 1298 if (IS_ERR(bo->obj)) 1299 return PTR_ERR(bo->obj); 1300 1301 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1302 range_start, range_end); 1303 if (ret) { 1304 drm_gem_object_put(bo->obj); 1305 return ret; 1306 } 1307 1308 bo->virt = msm_gem_get_vaddr(bo->obj); 1309 bo->size = size; 1310 1311 msm_gem_object_set_name(bo->obj, "%s", name); 1312 1313 return 0; 1314 } 1315 1316 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1317 { 1318 struct msm_mmu *mmu; 1319 1320 mmu = msm_iommu_new(gmu->dev, 0); 1321 if (!mmu) 1322 return -ENODEV; 1323 if (IS_ERR(mmu)) 1324 return PTR_ERR(mmu); 1325 1326 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); 1327 if (IS_ERR(gmu->aspace)) 1328 return PTR_ERR(gmu->aspace); 1329 1330 return 0; 1331 } 1332 1333 /** 1334 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) 1335 * @unit: divisor used to convert bytes/sec bw value to an RPMh msg 1336 * @width: multiplier used to convert bytes/sec bw value to an RPMh msg 1337 * @vcd: virtual clock domain that this bcm belongs to 1338 * @reserved: reserved field 1339 */ 1340 struct bcm_db { 1341 __le32 unit; 1342 __le16 width; 1343 u8 vcd; 1344 u8 reserved; 1345 }; 1346 1347 static int a6xx_gmu_rpmh_bw_votes_init(struct adreno_gpu *adreno_gpu, 1348 const struct a6xx_info *info, 1349 struct a6xx_gmu *gmu) 1350 { 1351 const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 }; 1352 unsigned int bcm_index, bw_index, bcm_count = 0; 1353 1354 /* Retrieve BCM data from cmd-db */ 1355 for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { 1356 const struct a6xx_bcm *bcm = &info->bcms[bcm_index]; 1357 size_t count; 1358 1359 /* Stop at NULL terminated bcm entry */ 1360 if (!bcm->name) 1361 break; 1362 1363 bcm_data[bcm_index] = cmd_db_read_aux_data(bcm->name, &count); 1364 if (IS_ERR(bcm_data[bcm_index])) 1365 return PTR_ERR(bcm_data[bcm_index]); 1366 1367 if (!count) { 1368 dev_err(gmu->dev, "invalid BCM '%s' aux data size\n", 1369 bcm->name); 1370 return -EINVAL; 1371 } 1372 1373 bcm_count++; 1374 } 1375 1376 /* Generate BCM votes values for each bandwidth & BCM */ 1377 for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) { 1378 u32 *data = gmu->gpu_ib_votes[bw_index]; 1379 u32 bw = gmu->gpu_bw_table[bw_index]; 1380 1381 /* Calculations loosely copied from bcm_aggregate() & tcs_cmd_gen() */ 1382 for (bcm_index = 0; bcm_index < bcm_count; bcm_index++) { 1383 const struct a6xx_bcm *bcm = &info->bcms[bcm_index]; 1384 bool commit = false; 1385 u64 peak; 1386 u32 vote; 1387 1388 if (bcm_index == bcm_count - 1 || 1389 (bcm_data[bcm_index + 1] && 1390 bcm_data[bcm_index]->vcd != bcm_data[bcm_index + 1]->vcd)) 1391 commit = true; 1392 1393 if (!bw) { 1394 data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0); 1395 continue; 1396 } 1397 1398 if (bcm->fixed) { 1399 u32 perfmode = 0; 1400 1401 /* GMU on A6xx votes perfmode on all valid bandwidth */ 1402 if (!adreno_is_a7xx(adreno_gpu) || 1403 (bcm->perfmode_bw && bw >= bcm->perfmode_bw)) 1404 perfmode = bcm->perfmode; 1405 1406 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode); 1407 continue; 1408 } 1409 1410 /* Multiply the bandwidth by the width of the connection */ 1411 peak = (u64)bw * le16_to_cpu(bcm_data[bcm_index]->width); 1412 do_div(peak, bcm->buswidth); 1413 1414 /* Input bandwidth value is in KBps, scale the value to BCM unit */ 1415 peak *= 1000; 1416 do_div(peak, le32_to_cpu(bcm_data[bcm_index]->unit)); 1417 1418 vote = clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK); 1419 1420 /* GMUs on A7xx votes on both x & y */ 1421 if (adreno_is_a7xx(adreno_gpu)) 1422 data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote); 1423 else 1424 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote); 1425 } 1426 } 1427 1428 return 0; 1429 } 1430 1431 /* Return the 'arc-level' for the given frequency */ 1432 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1433 unsigned long freq) 1434 { 1435 struct dev_pm_opp *opp; 1436 unsigned int val; 1437 1438 if (!freq) 1439 return 0; 1440 1441 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1442 if (IS_ERR(opp)) 1443 return 0; 1444 1445 val = dev_pm_opp_get_level(opp); 1446 1447 dev_pm_opp_put(opp); 1448 1449 return val; 1450 } 1451 1452 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1453 unsigned long *freqs, int freqs_count, const char *id) 1454 { 1455 int i, j; 1456 const u16 *pri, *sec; 1457 size_t pri_count, sec_count; 1458 1459 pri = cmd_db_read_aux_data(id, &pri_count); 1460 if (IS_ERR(pri)) 1461 return PTR_ERR(pri); 1462 /* 1463 * The data comes back as an array of unsigned shorts so adjust the 1464 * count accordingly 1465 */ 1466 pri_count >>= 1; 1467 if (!pri_count) 1468 return -EINVAL; 1469 1470 /* 1471 * Some targets have a separate gfx mxc rail. So try to read that first and then fall back 1472 * to regular mx rail if it is missing 1473 */ 1474 sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); 1475 if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER)) 1476 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1477 if (IS_ERR(sec)) 1478 return PTR_ERR(sec); 1479 1480 sec_count >>= 1; 1481 if (!sec_count) 1482 return -EINVAL; 1483 1484 /* Construct a vote for each frequency */ 1485 for (i = 0; i < freqs_count; i++) { 1486 u8 pindex = 0, sindex = 0; 1487 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1488 1489 /* Get the primary index that matches the arc level */ 1490 for (j = 0; j < pri_count; j++) { 1491 if (pri[j] >= level) { 1492 pindex = j; 1493 break; 1494 } 1495 } 1496 1497 if (j == pri_count) { 1498 DRM_DEV_ERROR(dev, 1499 "Level %u not found in the RPMh list\n", 1500 level); 1501 DRM_DEV_ERROR(dev, "Available levels:\n"); 1502 for (j = 0; j < pri_count; j++) 1503 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1504 1505 return -EINVAL; 1506 } 1507 1508 /* 1509 * Look for a level in in the secondary list that matches. If 1510 * nothing fits, use the maximum non zero vote 1511 */ 1512 1513 for (j = 0; j < sec_count; j++) { 1514 if (sec[j] >= level) { 1515 sindex = j; 1516 break; 1517 } else if (sec[j]) { 1518 sindex = j; 1519 } 1520 } 1521 1522 /* Construct the vote */ 1523 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1524 (sindex << 8) | pindex; 1525 } 1526 1527 return 0; 1528 } 1529 1530 /* 1531 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1532 * to construct the list of votes on the CPU and send it over. Query the RPMh 1533 * voltage levels and build the votes 1534 * The GMU can also vote for DDR interconnects, use the OPP bandwidth entries 1535 * and BCM parameters to build the votes. 1536 */ 1537 1538 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1539 { 1540 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1541 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1542 const struct a6xx_info *info = adreno_gpu->info->a6xx; 1543 struct msm_gpu *gpu = &adreno_gpu->base; 1544 int ret; 1545 1546 /* Build the GX votes */ 1547 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1548 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1549 1550 /* Build the CX votes */ 1551 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1552 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1553 1554 /* Build the interconnect votes */ 1555 if (info->bcms && gmu->nr_gpu_bws > 1) 1556 ret |= a6xx_gmu_rpmh_bw_votes_init(adreno_gpu, info, gmu); 1557 1558 return ret; 1559 } 1560 1561 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1562 u32 size) 1563 { 1564 int count = dev_pm_opp_get_opp_count(dev); 1565 struct dev_pm_opp *opp; 1566 int i, index = 0; 1567 unsigned long freq = 1; 1568 1569 /* 1570 * The OPP table doesn't contain the "off" frequency level so we need to 1571 * add 1 to the table size to account for it 1572 */ 1573 1574 if (WARN(count + 1 > size, 1575 "The GMU frequency table is being truncated\n")) 1576 count = size - 1; 1577 1578 /* Set the "off" frequency */ 1579 freqs[index++] = 0; 1580 1581 for (i = 0; i < count; i++) { 1582 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1583 if (IS_ERR(opp)) 1584 break; 1585 1586 dev_pm_opp_put(opp); 1587 freqs[index++] = freq++; 1588 } 1589 1590 return index; 1591 } 1592 1593 static int a6xx_gmu_build_bw_table(struct device *dev, unsigned long *bandwidths, 1594 u32 size) 1595 { 1596 int count = dev_pm_opp_get_opp_count(dev); 1597 struct dev_pm_opp *opp; 1598 int i, index = 0; 1599 unsigned int bandwidth = 1; 1600 1601 /* 1602 * The OPP table doesn't contain the "off" bandwidth level so we need to 1603 * add 1 to the table size to account for it 1604 */ 1605 1606 if (WARN(count + 1 > size, 1607 "The GMU bandwidth table is being truncated\n")) 1608 count = size - 1; 1609 1610 /* Set the "off" bandwidth */ 1611 bandwidths[index++] = 0; 1612 1613 for (i = 0; i < count; i++) { 1614 opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0); 1615 if (IS_ERR(opp)) 1616 break; 1617 1618 dev_pm_opp_put(opp); 1619 bandwidths[index++] = bandwidth++; 1620 } 1621 1622 return index; 1623 } 1624 1625 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1626 { 1627 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1628 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1629 const struct a6xx_info *info = adreno_gpu->info->a6xx; 1630 struct msm_gpu *gpu = &adreno_gpu->base; 1631 1632 int ret = 0; 1633 1634 /* 1635 * The GMU handles its own frequency switching so build a list of 1636 * available frequencies to send during initialization 1637 */ 1638 ret = devm_pm_opp_of_add_table(gmu->dev); 1639 if (ret) { 1640 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1641 return ret; 1642 } 1643 1644 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1645 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1646 1647 /* 1648 * The GMU also handles GPU frequency switching so build a list 1649 * from the GPU OPP table 1650 */ 1651 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1652 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1653 1654 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1655 1656 /* 1657 * The GMU also handles GPU Interconnect Votes so build a list 1658 * of DDR bandwidths from the GPU OPP table 1659 */ 1660 if (info->bcms) 1661 gmu->nr_gpu_bws = a6xx_gmu_build_bw_table(&gpu->pdev->dev, 1662 gmu->gpu_bw_table, ARRAY_SIZE(gmu->gpu_bw_table)); 1663 1664 /* Build the list of RPMh votes that we'll send to the GMU */ 1665 return a6xx_gmu_rpmh_votes_init(gmu); 1666 } 1667 1668 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1669 { 1670 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1671 1672 if (ret < 1) 1673 return ret; 1674 1675 gmu->nr_clocks = ret; 1676 1677 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1678 gmu->nr_clocks, "gmu"); 1679 1680 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks, 1681 gmu->nr_clocks, "hub"); 1682 1683 return 0; 1684 } 1685 1686 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1687 const char *name) 1688 { 1689 void __iomem *ret; 1690 struct resource *res = platform_get_resource_byname(pdev, 1691 IORESOURCE_MEM, name); 1692 1693 if (!res) { 1694 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1695 return ERR_PTR(-EINVAL); 1696 } 1697 1698 ret = ioremap(res->start, resource_size(res)); 1699 if (!ret) { 1700 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1701 return ERR_PTR(-EINVAL); 1702 } 1703 1704 return ret; 1705 } 1706 1707 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1708 const char *name, irq_handler_t handler) 1709 { 1710 int irq, ret; 1711 1712 irq = platform_get_irq_byname(pdev, name); 1713 1714 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, name, gmu); 1715 if (ret) { 1716 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1717 name, ret); 1718 return ret; 1719 } 1720 1721 return irq; 1722 } 1723 1724 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1725 { 1726 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1727 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1728 struct platform_device *pdev = to_platform_device(gmu->dev); 1729 1730 mutex_lock(&gmu->lock); 1731 if (!gmu->initialized) { 1732 mutex_unlock(&gmu->lock); 1733 return; 1734 } 1735 1736 gmu->initialized = false; 1737 1738 mutex_unlock(&gmu->lock); 1739 1740 pm_runtime_force_suspend(gmu->dev); 1741 1742 /* 1743 * Since cxpd is a virt device, the devlink with gmu-dev will be removed 1744 * automatically when we do detach 1745 */ 1746 dev_pm_domain_detach(gmu->cxpd, false); 1747 1748 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1749 pm_runtime_disable(gmu->gxpd); 1750 dev_pm_domain_detach(gmu->gxpd, false); 1751 } 1752 1753 if (!IS_ERR_OR_NULL(gmu->qmp)) 1754 qmp_put(gmu->qmp); 1755 1756 iounmap(gmu->mmio); 1757 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1758 iounmap(gmu->rscc); 1759 gmu->mmio = NULL; 1760 gmu->rscc = NULL; 1761 1762 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1763 a6xx_gmu_memory_free(gmu); 1764 1765 free_irq(gmu->gmu_irq, gmu); 1766 free_irq(gmu->hfi_irq, gmu); 1767 } 1768 1769 /* Drop reference taken in of_find_device_by_node */ 1770 put_device(gmu->dev); 1771 } 1772 1773 static int cxpd_notifier_cb(struct notifier_block *nb, 1774 unsigned long action, void *data) 1775 { 1776 struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb); 1777 1778 if (action == GENPD_NOTIFY_OFF) 1779 complete_all(&gmu->pd_gate); 1780 1781 return 0; 1782 } 1783 1784 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1785 { 1786 struct platform_device *pdev = of_find_device_by_node(node); 1787 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1788 int ret; 1789 1790 if (!pdev) 1791 return -ENODEV; 1792 1793 gmu->dev = &pdev->dev; 1794 1795 ret = of_dma_configure(gmu->dev, node, true); 1796 if (ret) 1797 return ret; 1798 1799 pm_runtime_enable(gmu->dev); 1800 1801 /* Mark legacy for manual SPTPRAC control */ 1802 gmu->legacy = true; 1803 1804 /* Map the GMU registers */ 1805 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1806 if (IS_ERR(gmu->mmio)) { 1807 ret = PTR_ERR(gmu->mmio); 1808 goto err_mmio; 1809 } 1810 1811 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); 1812 if (IS_ERR(gmu->cxpd)) { 1813 ret = PTR_ERR(gmu->cxpd); 1814 goto err_mmio; 1815 } 1816 1817 if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { 1818 ret = -ENODEV; 1819 goto detach_cxpd; 1820 } 1821 1822 init_completion(&gmu->pd_gate); 1823 complete_all(&gmu->pd_gate); 1824 gmu->pd_nb.notifier_call = cxpd_notifier_cb; 1825 1826 /* Get a link to the GX power domain to reset the GPU */ 1827 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1828 if (IS_ERR(gmu->gxpd)) { 1829 ret = PTR_ERR(gmu->gxpd); 1830 goto err_mmio; 1831 } 1832 1833 gmu->initialized = true; 1834 1835 return 0; 1836 1837 detach_cxpd: 1838 dev_pm_domain_detach(gmu->cxpd, false); 1839 1840 err_mmio: 1841 iounmap(gmu->mmio); 1842 1843 /* Drop reference taken in of_find_device_by_node */ 1844 put_device(gmu->dev); 1845 1846 return ret; 1847 } 1848 1849 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1850 { 1851 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1852 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1853 struct platform_device *pdev = of_find_device_by_node(node); 1854 struct device_link *link; 1855 int ret; 1856 1857 if (!pdev) 1858 return -ENODEV; 1859 1860 gmu->dev = &pdev->dev; 1861 1862 ret = of_dma_configure(gmu->dev, node, true); 1863 if (ret) 1864 return ret; 1865 1866 /* Fow now, don't do anything fancy until we get our feet under us */ 1867 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1868 1869 pm_runtime_enable(gmu->dev); 1870 1871 /* Get the list of clocks */ 1872 ret = a6xx_gmu_clocks_probe(gmu); 1873 if (ret) 1874 goto err_put_device; 1875 1876 ret = a6xx_gmu_memory_probe(gmu); 1877 if (ret) 1878 goto err_put_device; 1879 1880 1881 /* A660 now requires handling "prealloc requests" in GMU firmware 1882 * For now just hardcode allocations based on the known firmware. 1883 * note: there is no indication that these correspond to "dummy" or 1884 * "debug" regions, but this "guess" allows reusing these BOs which 1885 * are otherwise unused by a660. 1886 */ 1887 gmu->dummy.size = SZ_4K; 1888 if (adreno_is_a660_family(adreno_gpu) || 1889 adreno_is_a7xx(adreno_gpu)) { 1890 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 1891 0x60400000, "debug"); 1892 if (ret) 1893 goto err_memory; 1894 1895 gmu->dummy.size = SZ_8K; 1896 } 1897 1898 /* Allocate memory for the GMU dummy page */ 1899 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 1900 0x60000000, "dummy"); 1901 if (ret) 1902 goto err_memory; 1903 1904 /* Note that a650 family also includes a660 family: */ 1905 if (adreno_is_a650_family(adreno_gpu) || 1906 adreno_is_a7xx(adreno_gpu)) { 1907 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1908 SZ_16M - SZ_16K, 0x04000, "icache"); 1909 if (ret) 1910 goto err_memory; 1911 /* 1912 * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition 1913 * to allocate icache/dcache here, as per downstream code flow, but it may not actually be 1914 * necessary. If you omit this step and you don't get random pagefaults, you are likely 1915 * good to go without this! 1916 */ 1917 } else if (adreno_is_a640_family(adreno_gpu)) { 1918 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1919 SZ_256K - SZ_16K, 0x04000, "icache"); 1920 if (ret) 1921 goto err_memory; 1922 1923 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1924 SZ_256K - SZ_16K, 0x44000, "dcache"); 1925 if (ret) 1926 goto err_memory; 1927 } else if (adreno_is_a630_family(adreno_gpu)) { 1928 /* HFI v1, has sptprac */ 1929 gmu->legacy = true; 1930 1931 /* Allocate memory for the GMU debug region */ 1932 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug"); 1933 if (ret) 1934 goto err_memory; 1935 } 1936 1937 /* Allocate memory for the GMU log region */ 1938 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log"); 1939 if (ret) 1940 goto err_memory; 1941 1942 /* Allocate memory for for the HFI queues */ 1943 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); 1944 if (ret) 1945 goto err_memory; 1946 1947 /* Map the GMU registers */ 1948 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1949 if (IS_ERR(gmu->mmio)) { 1950 ret = PTR_ERR(gmu->mmio); 1951 goto err_memory; 1952 } 1953 1954 if (adreno_is_a650_family(adreno_gpu) || 1955 adreno_is_a7xx(adreno_gpu)) { 1956 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 1957 if (IS_ERR(gmu->rscc)) { 1958 ret = -ENODEV; 1959 goto err_mmio; 1960 } 1961 } else { 1962 gmu->rscc = gmu->mmio + 0x23000; 1963 } 1964 1965 /* Get the HFI and GMU interrupts */ 1966 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1967 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1968 1969 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) { 1970 ret = -ENODEV; 1971 goto err_mmio; 1972 } 1973 1974 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); 1975 if (IS_ERR(gmu->cxpd)) { 1976 ret = PTR_ERR(gmu->cxpd); 1977 goto err_mmio; 1978 } 1979 1980 link = device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); 1981 if (!link) { 1982 ret = -ENODEV; 1983 goto detach_cxpd; 1984 } 1985 1986 gmu->qmp = qmp_get(gmu->dev); 1987 if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu)) { 1988 ret = PTR_ERR(gmu->qmp); 1989 goto remove_device_link; 1990 } 1991 1992 init_completion(&gmu->pd_gate); 1993 complete_all(&gmu->pd_gate); 1994 gmu->pd_nb.notifier_call = cxpd_notifier_cb; 1995 1996 /* 1997 * Get a link to the GX power domain to reset the GPU in case of GMU 1998 * crash 1999 */ 2000 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 2001 2002 /* Get the power levels for the GMU and GPU */ 2003 a6xx_gmu_pwrlevels_probe(gmu); 2004 2005 /* Set up the HFI queues */ 2006 a6xx_hfi_init(gmu); 2007 2008 /* Initialize RPMh */ 2009 a6xx_gmu_rpmh_init(gmu); 2010 2011 gmu->initialized = true; 2012 2013 return 0; 2014 2015 remove_device_link: 2016 device_link_del(link); 2017 2018 detach_cxpd: 2019 dev_pm_domain_detach(gmu->cxpd, false); 2020 2021 err_mmio: 2022 iounmap(gmu->mmio); 2023 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 2024 iounmap(gmu->rscc); 2025 free_irq(gmu->gmu_irq, gmu); 2026 free_irq(gmu->hfi_irq, gmu); 2027 2028 err_memory: 2029 a6xx_gmu_memory_free(gmu); 2030 err_put_device: 2031 /* Drop reference taken in of_find_device_by_node */ 2032 put_device(gmu->dev); 2033 2034 return ret; 2035 } 2036