1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/interconnect.h> 7 #include <linux/of_platform.h> 8 #include <linux/platform_device.h> 9 #include <linux/pm_domain.h> 10 #include <linux/pm_opp.h> 11 #include <soc/qcom/cmd-db.h> 12 #include <soc/qcom/tcs.h> 13 #include <drm/drm_gem.h> 14 15 #include "a6xx_gpu.h" 16 #include "a6xx_gmu.xml.h" 17 #include "msm_gem.h" 18 #include "msm_gpu_trace.h" 19 #include "msm_mmu.h" 20 21 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 22 { 23 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 24 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 25 struct msm_gpu *gpu = &adreno_gpu->base; 26 27 /* FIXME: add a banner here */ 28 gmu->hung = true; 29 30 /* Turn off the hangcheck timer while we are resetting */ 31 timer_delete(&gpu->hangcheck_timer); 32 33 /* Queue the GPU handler because we need to treat this as a recovery */ 34 kthread_queue_work(gpu->worker, &gpu->recover_work); 35 } 36 37 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 38 { 39 struct a6xx_gmu *gmu = data; 40 u32 status; 41 42 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 43 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 44 45 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 46 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 47 48 a6xx_gmu_fault(gmu); 49 } 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 52 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 53 54 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 55 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 56 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 57 58 return IRQ_HANDLED; 59 } 60 61 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 62 { 63 struct a6xx_gmu *gmu = data; 64 u32 status; 65 66 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 67 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 68 69 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 70 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 71 72 a6xx_gmu_fault(gmu); 73 } 74 75 return IRQ_HANDLED; 76 } 77 78 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 79 { 80 u32 val; 81 82 /* This can be called from gpu state code so make sure GMU is valid */ 83 if (!gmu->initialized) 84 return false; 85 86 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 87 88 return !(val & 89 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 90 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 91 } 92 93 /* Check to see if the GX rail is still powered */ 94 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 95 { 96 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 97 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 98 u32 val; 99 100 /* This can be called from gpu state code so make sure GMU is valid */ 101 if (!gmu->initialized) 102 return false; 103 104 /* If GMU is absent, then GX power domain is ON as long as GPU is in active state */ 105 if (adreno_has_gmu_wrapper(adreno_gpu)) 106 return true; 107 108 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 109 110 if (adreno_is_a7xx(adreno_gpu)) 111 return !(val & 112 (A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 113 A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 114 115 return !(val & 116 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 117 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 118 } 119 120 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 121 bool suspended) 122 { 123 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 124 const struct a6xx_info *info = adreno_gpu->info->a6xx; 125 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 126 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 127 u32 perf_index; 128 u32 bw_index = 0; 129 unsigned long gpu_freq; 130 int ret = 0; 131 132 gpu_freq = dev_pm_opp_get_freq(opp); 133 134 if (gpu_freq == gmu->freq) 135 return; 136 137 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 138 if (gpu_freq == gmu->gpu_freqs[perf_index]) 139 break; 140 141 /* If enabled, find the corresponding DDR bandwidth index */ 142 if (info->bcms && gmu->nr_gpu_bws > 1) { 143 unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); 144 145 for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { 146 if (bw == gmu->gpu_bw_table[bw_index]) 147 break; 148 } 149 150 /* Vote AB as a fraction of the max bandwidth, starting from A750 */ 151 if (bw && adreno_is_a750_family(adreno_gpu)) { 152 u64 tmp; 153 154 /* For now, vote for 25% of the bandwidth */ 155 tmp = bw * 25; 156 do_div(tmp, 100); 157 158 /* 159 * The AB vote consists of a 16 bit wide quantized level 160 * against the maximum supported bandwidth. 161 * Quantization can be calculated as below: 162 * vote = (bandwidth * 2^16) / max bandwidth 163 */ 164 tmp *= MAX_AB_VOTE; 165 do_div(tmp, gmu->gpu_bw_table[gmu->nr_gpu_bws - 1]); 166 167 bw_index |= AB_VOTE(clamp(tmp, 1, MAX_AB_VOTE)); 168 bw_index |= AB_VOTE_ENABLE; 169 } 170 } 171 172 gmu->current_perf_index = perf_index; 173 gmu->freq = gmu->gpu_freqs[perf_index]; 174 175 trace_msm_gmu_freq_change(gmu->freq, perf_index); 176 177 /* 178 * This can get called from devfreq while the hardware is idle. Don't 179 * bring up the power if it isn't already active. All we're doing here 180 * is updating the frequency so that when we come back online we're at 181 * the right rate. 182 */ 183 if (suspended) 184 return; 185 186 if (!gmu->legacy) { 187 a6xx_hfi_set_freq(gmu, perf_index, bw_index); 188 /* With Bandwidth voting, we now vote for all resources, so skip OPP set */ 189 if (!bw_index) 190 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 191 return; 192 } 193 194 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 195 196 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 197 ((3 & 0xf) << 28) | perf_index); 198 199 /* 200 * Send an invalid index as a vote for the bus bandwidth and let the 201 * firmware decide on the right vote 202 */ 203 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 204 205 /* Set and clear the OOB for DCVS to trigger the GMU */ 206 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 207 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 208 209 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 210 if (ret) 211 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 212 213 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 214 } 215 216 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 217 { 218 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 219 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 220 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 221 222 return gmu->freq; 223 } 224 225 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 226 { 227 u32 val; 228 int local = gmu->idle_level; 229 230 /* SPTP and IFPC both report as IFPC */ 231 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 232 local = GMU_IDLE_STATE_IFPC; 233 234 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 235 236 if (val == local) { 237 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 238 !a6xx_gmu_gx_is_on(gmu)) 239 return true; 240 } 241 242 return false; 243 } 244 245 /* Wait for the GMU to get to its most idle state */ 246 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 247 { 248 return spin_until(a6xx_gmu_check_idle_level(gmu)); 249 } 250 251 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 252 { 253 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 254 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 255 u32 mask, reset_val, val; 256 int ret; 257 258 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); 259 if (val <= 0x20010004) { 260 mask = 0xffffffff; 261 reset_val = 0xbabeface; 262 } else { 263 mask = 0x1ff; 264 reset_val = 0x100; 265 } 266 267 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 268 269 /* Set the log wptr index 270 * note: downstream saves the value in poweroff and restores it here 271 */ 272 if (adreno_is_a7xx(adreno_gpu)) 273 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); 274 else 275 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 276 277 278 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 279 280 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 281 (val & mask) == reset_val, 100, 10000); 282 283 if (ret) 284 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 285 286 set_bit(GMU_STATUS_FW_START, &gmu->status); 287 288 return ret; 289 } 290 291 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 292 { 293 u32 val; 294 int ret; 295 296 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 297 298 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 299 val & 1, 100, 10000); 300 if (ret) 301 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 302 303 return ret; 304 } 305 306 struct a6xx_gmu_oob_bits { 307 int set, ack, set_new, ack_new, clear, clear_new; 308 const char *name; 309 }; 310 311 /* These are the interrupt / ack bits for each OOB request that are set 312 * in a6xx_gmu_set_oob and a6xx_clear_oob 313 */ 314 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { 315 [GMU_OOB_GPU_SET] = { 316 .name = "GPU_SET", 317 .set = 16, 318 .ack = 24, 319 .set_new = 30, 320 .ack_new = 31, 321 .clear = 24, 322 .clear_new = 31, 323 }, 324 325 [GMU_OOB_PERFCOUNTER_SET] = { 326 .name = "PERFCOUNTER", 327 .set = 17, 328 .ack = 25, 329 .set_new = 28, 330 .ack_new = 30, 331 .clear = 25, 332 .clear_new = 29, 333 }, 334 335 [GMU_OOB_BOOT_SLUMBER] = { 336 .name = "BOOT_SLUMBER", 337 .set = 22, 338 .ack = 30, 339 .clear = 30, 340 }, 341 342 [GMU_OOB_DCVS_SET] = { 343 .name = "GPU_DCVS", 344 .set = 23, 345 .ack = 31, 346 .clear = 31, 347 }, 348 }; 349 350 /* Trigger a OOB (out of band) request to the GMU */ 351 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 352 { 353 int ret; 354 u32 val; 355 int request, ack; 356 357 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); 358 359 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) 360 return -EINVAL; 361 362 if (gmu->legacy) { 363 request = a6xx_gmu_oob_bits[state].set; 364 ack = a6xx_gmu_oob_bits[state].ack; 365 } else { 366 request = a6xx_gmu_oob_bits[state].set_new; 367 ack = a6xx_gmu_oob_bits[state].ack_new; 368 if (!request || !ack) { 369 DRM_DEV_ERROR(gmu->dev, 370 "Invalid non-legacy GMU request %s\n", 371 a6xx_gmu_oob_bits[state].name); 372 return -EINVAL; 373 } 374 } 375 376 /* Trigger the equested OOB operation */ 377 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 378 379 /* Wait for the acknowledge interrupt */ 380 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 381 val & (1 << ack), 100, 10000); 382 383 if (ret) 384 DRM_DEV_ERROR(gmu->dev, 385 "Timeout waiting for GMU OOB set %s: 0x%x\n", 386 a6xx_gmu_oob_bits[state].name, 387 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 388 389 /* Clear the acknowledge interrupt */ 390 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 391 392 return ret; 393 } 394 395 /* Clear a pending OOB state in the GMU */ 396 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 397 { 398 int bit; 399 400 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); 401 402 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) 403 return; 404 405 if (gmu->legacy) 406 bit = a6xx_gmu_oob_bits[state].clear; 407 else 408 bit = a6xx_gmu_oob_bits[state].clear_new; 409 410 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); 411 } 412 413 /* Enable CPU control of SPTP power power collapse */ 414 int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 415 { 416 int ret; 417 u32 val; 418 419 WARN_ON(!gmu->legacy); 420 421 /* Nothing to do if GMU does the power management */ 422 if (gmu->idle_level > GMU_IDLE_STATE_ACTIVE) 423 return 0; 424 425 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 426 427 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 428 (val & 0x38) == 0x28, 1, 100); 429 430 if (ret) { 431 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 432 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 433 } 434 435 return 0; 436 } 437 438 /* Disable CPU control of SPTP power power collapse */ 439 void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 440 { 441 u32 val; 442 int ret; 443 444 if (!gmu->legacy) 445 return; 446 447 /* Make sure retention is on */ 448 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 449 450 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 451 452 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 453 (val & 0x04), 100, 10000); 454 455 if (ret) 456 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 457 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 458 } 459 460 /* Let the GMU know we are starting a boot sequence */ 461 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 462 { 463 u32 vote; 464 465 /* Let the GMU know we are getting ready for boot */ 466 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 467 468 /* Choose the "default" power level as the highest available */ 469 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 470 471 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 472 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 473 474 /* Let the GMU know the boot sequence has started */ 475 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 476 } 477 478 static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) 479 { 480 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 481 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 482 483 /* 484 * GEMNoC can power collapse whilst the GPU is being powered down, resulting 485 * in the power down sequence not being fully executed. That in turn can 486 * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. 487 */ 488 if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 489 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); 490 } 491 492 /* Let the GMU know that we are about to go into slumber */ 493 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 494 { 495 int ret; 496 497 /* Disable the power counter so the GMU isn't busy */ 498 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 499 500 /* Disable SPTP_PC if the CPU is responsible for it */ 501 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 502 a6xx_sptprac_disable(gmu); 503 504 if (!gmu->legacy) { 505 ret = a6xx_hfi_send_prep_slumber(gmu); 506 goto out; 507 } 508 509 /* Tell the GMU to get ready to slumber */ 510 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 511 512 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 513 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 514 515 if (!ret) { 516 /* Check to see if the GMU really did slumber */ 517 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 518 != 0x0f) { 519 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 520 ret = -ETIMEDOUT; 521 } 522 } 523 524 out: 525 a6xx_gemnoc_workaround(gmu); 526 527 /* Put fence into allow mode */ 528 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 529 return ret; 530 } 531 532 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 533 { 534 int ret; 535 u32 val; 536 537 if (!test_and_clear_bit(GMU_STATUS_PDC_SLEEP, &gmu->status)) 538 return 0; 539 540 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1)); 541 542 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 543 val & (1 << 1), 100, 10000); 544 if (ret) { 545 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 546 return ret; 547 } 548 549 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 550 !val, 100, 10000); 551 552 if (ret) { 553 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 554 return ret; 555 } 556 557 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 558 559 return 0; 560 } 561 562 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 563 { 564 int ret; 565 u32 val; 566 567 if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) 568 return; 569 570 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 571 572 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 573 val, val & (1 << 16), 100, 10000); 574 if (ret) 575 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 576 577 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 578 579 set_bit(GMU_STATUS_PDC_SLEEP, &gmu->status); 580 } 581 582 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 583 { 584 writel(value, ptr + (offset << 2)); 585 } 586 587 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 588 const char *name); 589 590 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 591 { 592 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 593 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 594 struct platform_device *pdev = to_platform_device(gmu->dev); 595 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 596 u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0; 597 void __iomem *seqptr = NULL; 598 uint32_t pdc_address_offset; 599 bool pdc_in_aop = false; 600 601 if (IS_ERR(pdcptr)) 602 goto err; 603 604 if (adreno_is_a650_family(adreno_gpu) || 605 adreno_is_a7xx(adreno_gpu)) 606 pdc_in_aop = true; 607 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu)) 608 pdc_address_offset = 0x30090; 609 else if (adreno_is_a619(adreno_gpu)) 610 pdc_address_offset = 0x300a0; 611 else 612 pdc_address_offset = 0x30080; 613 614 if (!pdc_in_aop) { 615 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 616 if (IS_ERR(seqptr)) 617 goto err; 618 } 619 620 /* Disable SDE clock gating */ 621 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 622 623 /* Setup RSC PDC handshake for sleep and wakeup */ 624 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 625 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 626 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 627 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 628 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 629 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 630 adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000); 631 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 632 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 633 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 634 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 635 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 636 637 /* The second spin of A7xx GPUs messed with some register offsets.. */ 638 if (adreno_is_a740_family(adreno_gpu)) 639 seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740; 640 641 /* Load RSC sequencer uCode for sleep and wakeup */ 642 if (adreno_is_a650_family(adreno_gpu) || 643 adreno_is_a7xx(adreno_gpu)) { 644 gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0); 645 gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab); 646 gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581); 647 gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2); 648 gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad); 649 } else { 650 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 651 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 652 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 653 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 654 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 655 } 656 657 if (pdc_in_aop) 658 goto setup_pdc; 659 660 /* Load PDC sequencer uCode for power up and power down sequence */ 661 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 662 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 663 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 664 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 665 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 666 667 /* Set TCS commands used by PDC sequence for low power modes */ 668 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 669 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 670 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 671 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 672 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 673 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 674 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 675 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 676 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 677 678 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 679 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 680 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 681 682 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 683 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 684 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 685 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 686 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 687 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 688 689 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 690 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 691 if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) || 692 adreno_is_a650_family(adreno_gpu)) 693 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 694 else 695 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 696 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 697 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 698 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 699 700 /* Setup GPU PDC */ 701 setup_pdc: 702 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 703 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 704 705 /* ensure no writes happen before the uCode is fully written */ 706 wmb(); 707 708 err: 709 if (!IS_ERR_OR_NULL(pdcptr)) 710 iounmap(pdcptr); 711 if (!IS_ERR_OR_NULL(seqptr)) 712 iounmap(seqptr); 713 } 714 715 /* 716 * The lowest 16 bits of this value are the number of XO clock cycles for main 717 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 718 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 719 */ 720 721 #define GMU_PWR_COL_HYST 0x000a1680 722 723 /* Set up the idle state for the GMU */ 724 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 725 { 726 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 727 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 728 729 /* Disable GMU WB/RB buffer */ 730 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 731 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 732 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 733 734 /* A7xx knows better by default! */ 735 if (adreno_is_a7xx(adreno_gpu)) 736 return; 737 738 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 739 740 switch (gmu->idle_level) { 741 case GMU_IDLE_STATE_IFPC: 742 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 743 GMU_PWR_COL_HYST); 744 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 745 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 746 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 747 fallthrough; 748 case GMU_IDLE_STATE_SPTP: 749 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 750 GMU_PWR_COL_HYST); 751 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 752 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 753 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 754 } 755 756 /* Enable RPMh GPU client */ 757 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 758 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 759 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 760 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 761 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 762 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 763 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 764 } 765 766 struct block_header { 767 u32 addr; 768 u32 size; 769 u32 type; 770 u32 value; 771 u32 data[]; 772 }; 773 774 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 775 { 776 if (!in_range(blk->addr, bo->iova, bo->size)) 777 return false; 778 779 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 780 return true; 781 } 782 783 #define NEXT_BLK(blk) \ 784 ((const struct block_header *)((const char *)(blk) + sizeof(*(blk)) + (blk)->size)) 785 786 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 787 { 788 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 789 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 790 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 791 const struct block_header *blk; 792 u32 reg_offset; 793 u32 ver; 794 795 u32 itcm_base = 0x00000000; 796 u32 dtcm_base = 0x00040000; 797 798 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 799 dtcm_base = 0x10004000; 800 801 if (gmu->legacy) { 802 /* Sanity check the size of the firmware that was loaded */ 803 if (fw_image->size > 0x8000) { 804 DRM_DEV_ERROR(gmu->dev, 805 "GMU firmware is bigger than the available region\n"); 806 return -EINVAL; 807 } 808 809 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 810 (u32*) fw_image->data, fw_image->size); 811 return 0; 812 } 813 814 815 for (blk = (const struct block_header *) fw_image->data; 816 (const u8*) blk < fw_image->data + fw_image->size; 817 blk = NEXT_BLK(blk)) { 818 if (blk->size == 0) 819 continue; 820 821 if (in_range(blk->addr, itcm_base, SZ_16K)) { 822 reg_offset = (blk->addr - itcm_base) >> 2; 823 gmu_write_bulk(gmu, 824 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 825 blk->data, blk->size); 826 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 827 reg_offset = (blk->addr - dtcm_base) >> 2; 828 gmu_write_bulk(gmu, 829 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 830 blk->data, blk->size); 831 } else if (!fw_block_mem(&gmu->icache, blk) && 832 !fw_block_mem(&gmu->dcache, blk) && 833 !fw_block_mem(&gmu->dummy, blk)) { 834 DRM_DEV_ERROR(gmu->dev, 835 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 836 blk->addr, blk->size, blk->data[0]); 837 } 838 } 839 840 ver = gmu_read(gmu, REG_A6XX_GMU_CORE_FW_VERSION); 841 DRM_INFO_ONCE("Loaded GMU firmware v%u.%u.%u\n", 842 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MAJOR__MASK, ver), 843 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MINOR__MASK, ver), 844 FIELD_GET(A6XX_GMU_CORE_FW_VERSION_STEP__MASK, ver)); 845 846 return 0; 847 } 848 849 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 850 { 851 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 852 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 853 const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; 854 u32 fence_range_lower, fence_range_upper; 855 u32 chipid = 0; 856 int ret; 857 858 /* Vote veto for FAL10 */ 859 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { 860 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); 861 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 862 } 863 864 /* Turn on TCM (Tightly Coupled Memory) retention */ 865 if (adreno_is_a7xx(adreno_gpu)) 866 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); 867 else 868 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 869 870 ret = a6xx_rpmh_start(gmu); 871 if (ret) 872 return ret; 873 874 if (state == GMU_COLD_BOOT) { 875 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 876 "GMU firmware is not loaded\n")) 877 return -ENOENT; 878 879 ret = a6xx_gmu_fw_load(gmu); 880 if (ret) 881 return ret; 882 } 883 884 /* Clear init result to make sure we are getting a fresh value */ 885 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 886 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 887 888 /* Write the iova of the HFI table */ 889 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 890 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 891 892 if (adreno_is_a7xx(adreno_gpu)) { 893 fence_range_upper = 0x32; 894 fence_range_lower = 0x8a0; 895 } else { 896 fence_range_upper = 0xa; 897 fence_range_lower = 0xa0; 898 } 899 900 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 901 BIT(31) | 902 FIELD_PREP(GENMASK(30, 18), fence_range_upper) | 903 FIELD_PREP(GENMASK(17, 0), fence_range_lower)); 904 905 /* 906 * Snapshots toggle the NMI bit which will result in a jump to the NMI 907 * handler instead of __main. Set the M3 config value to avoid that. 908 */ 909 gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); 910 911 if (a6xx_info->gmu_chipid) { 912 chipid = a6xx_info->gmu_chipid; 913 } else { 914 /* 915 * Note that the GMU has a slightly different layout for 916 * chip_id, for whatever reason, so a bit of massaging 917 * is needed. The upper 16b are the same, but minor and 918 * patchid are packed in four bits each with the lower 919 * 8b unused: 920 */ 921 chipid = adreno_gpu->chip_id & 0xffff0000; 922 chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ 923 chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ 924 } 925 926 if (adreno_is_a7xx(adreno_gpu)) { 927 gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid); 928 gmu_write(gmu, REG_A7XX_GMU_GENERAL_8, 929 (gmu->log.iova & GENMASK(31, 12)) | 930 ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); 931 } else { 932 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 933 934 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 935 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 936 } 937 938 /* Set up the lowest idle level on the GMU */ 939 a6xx_gmu_power_config(gmu); 940 941 ret = a6xx_gmu_start(gmu); 942 if (ret) 943 return ret; 944 945 if (gmu->legacy) { 946 ret = a6xx_gmu_gfx_rail_on(gmu); 947 if (ret) 948 return ret; 949 950 ret = a6xx_sptprac_enable(gmu); 951 if (ret) 952 return ret; 953 } 954 955 ret = a6xx_gmu_hfi_start(gmu); 956 if (ret) 957 return ret; 958 959 /* FIXME: Do we need this wmb() here? */ 960 wmb(); 961 962 return 0; 963 } 964 965 #define A6XX_HFI_IRQ_MASK \ 966 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 967 968 #define A6XX_GMU_IRQ_MASK \ 969 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 970 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 971 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 972 973 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 974 { 975 disable_irq(gmu->gmu_irq); 976 disable_irq(gmu->hfi_irq); 977 978 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 979 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 980 } 981 982 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 983 { 984 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 985 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 986 u32 val, seqmem_off = 0; 987 988 /* The second spin of A7xx GPUs messed with some register offsets.. */ 989 if (adreno_is_a740_family(adreno_gpu)) 990 seqmem_off = 4; 991 992 /* Make sure there are no outstanding RPMh votes */ 993 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS + seqmem_off, 994 val, (val & 1), 100, 10000); 995 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS + seqmem_off, 996 val, (val & 1), 100, 10000); 997 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS + seqmem_off, 998 val, (val & 1), 100, 10000); 999 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, 1000 val, (val & 1), 100, 1000); 1001 1002 if (!adreno_is_a740_family(adreno_gpu)) 1003 return; 1004 1005 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, 1006 val, (val & 1), 100, 10000); 1007 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, 1008 val, (val & 1), 100, 10000); 1009 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, 1010 val, (val & 1), 100, 10000); 1011 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, 1012 val, (val & 1), 100, 1000); 1013 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, 1014 val, (val & 1), 100, 10000); 1015 gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, 1016 val, (val & 1), 100, 1000); 1017 } 1018 1019 /* Force the GMU off in case it isn't responsive */ 1020 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 1021 { 1022 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1023 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1024 struct msm_gpu *gpu = &adreno_gpu->base; 1025 1026 /* 1027 * Turn off keep alive that might have been enabled by the hang 1028 * interrupt 1029 */ 1030 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 1031 1032 /* Flush all the queues */ 1033 a6xx_hfi_stop(gmu); 1034 1035 /* Stop the interrupts */ 1036 a6xx_gmu_irq_disable(gmu); 1037 1038 /* Force off SPTP in case the GMU is managing it */ 1039 a6xx_sptprac_disable(gmu); 1040 1041 a6xx_gemnoc_workaround(gmu); 1042 1043 /* Make sure there are no outstanding RPMh votes */ 1044 a6xx_gmu_rpmh_off(gmu); 1045 1046 /* Clear the WRITEDROPPED fields and put fence into allow mode */ 1047 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7); 1048 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 1049 1050 /* Make sure the above writes go through */ 1051 wmb(); 1052 1053 /* Halt the gmu cm3 core */ 1054 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 1055 1056 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1057 1058 /* Reset GPU core blocks */ 1059 a6xx_gpu_sw_reset(gpu, true); 1060 1061 a6xx_rpmh_stop(gmu); 1062 } 1063 1064 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 1065 { 1066 struct dev_pm_opp *gpu_opp; 1067 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 1068 1069 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 1070 if (IS_ERR(gpu_opp)) 1071 return; 1072 1073 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ 1074 a6xx_gmu_set_freq(gpu, gpu_opp, false); 1075 dev_pm_opp_put(gpu_opp); 1076 } 1077 1078 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 1079 { 1080 struct dev_pm_opp *gpu_opp; 1081 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 1082 1083 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 1084 if (IS_ERR(gpu_opp)) 1085 return; 1086 1087 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp); 1088 dev_pm_opp_put(gpu_opp); 1089 } 1090 1091 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 1092 { 1093 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1094 struct msm_gpu *gpu = &adreno_gpu->base; 1095 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1096 int status, ret; 1097 1098 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 1099 return -EINVAL; 1100 1101 gmu->hung = false; 1102 1103 /* Turn on the resources */ 1104 pm_runtime_get_sync(gmu->dev); 1105 1106 /* 1107 * "enable" the GX power domain which won't actually do anything but it 1108 * will make sure that the refcounting is correct in case we need to 1109 * bring down the GX after a GMU failure 1110 */ 1111 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1112 pm_runtime_get_sync(gmu->gxpd); 1113 1114 /* Use a known rate to bring up the GMU */ 1115 clk_set_rate(gmu->core_clk, 200000000); 1116 clk_set_rate(gmu->hub_clk, adreno_is_a740_family(adreno_gpu) ? 1117 200000000 : 150000000); 1118 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 1119 if (ret) { 1120 pm_runtime_put(gmu->gxpd); 1121 pm_runtime_put(gmu->dev); 1122 return ret; 1123 } 1124 1125 /* Set the bus quota to a reasonable value for boot */ 1126 a6xx_gmu_set_initial_bw(gpu, gmu); 1127 1128 /* Enable the GMU interrupt */ 1129 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 1130 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 1131 enable_irq(gmu->gmu_irq); 1132 1133 /* Check to see if we are doing a cold or warm boot */ 1134 if (adreno_is_a7xx(adreno_gpu)) { 1135 status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ? 1136 GMU_WARM_BOOT : GMU_COLD_BOOT; 1137 } else if (gmu->legacy) { 1138 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 1139 GMU_WARM_BOOT : GMU_COLD_BOOT; 1140 } else { 1141 /* 1142 * Warm boot path does not work on newer A6xx GPUs 1143 * Presumably this is because icache/dcache regions must be restored 1144 */ 1145 status = GMU_COLD_BOOT; 1146 } 1147 1148 ret = a6xx_gmu_fw_start(gmu, status); 1149 if (ret) 1150 goto out; 1151 1152 ret = a6xx_hfi_start(gmu, status); 1153 if (ret) 1154 goto out; 1155 1156 /* 1157 * Turn on the GMU firmware fault interrupt after we know the boot 1158 * sequence is successful 1159 */ 1160 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 1161 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 1162 enable_irq(gmu->hfi_irq); 1163 1164 /* Set the GPU to the current freq */ 1165 a6xx_gmu_set_initial_freq(gpu, gmu); 1166 1167 if (refcount_read(&gpu->sysprof_active) > 1) { 1168 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1169 if (!ret) 1170 set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); 1171 } 1172 out: 1173 /* On failure, shut down the GMU to leave it in a good state */ 1174 if (ret) { 1175 disable_irq(gmu->gmu_irq); 1176 a6xx_rpmh_stop(gmu); 1177 pm_runtime_put(gmu->gxpd); 1178 pm_runtime_put(gmu->dev); 1179 } 1180 1181 return ret; 1182 } 1183 1184 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 1185 { 1186 u32 reg; 1187 1188 if (!gmu->initialized) 1189 return true; 1190 1191 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 1192 1193 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 1194 return false; 1195 1196 return true; 1197 } 1198 1199 /* Gracefully try to shut down the GMU and by extension the GPU */ 1200 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 1201 { 1202 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1203 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1204 u32 val; 1205 int ret; 1206 1207 /* 1208 * GMU firmware's internal power state gets messed up if we send "prepare_slumber" hfi when 1209 * oob_gpu handshake wasn't done after the last wake up. So do a dummy handshake here when 1210 * required 1211 */ 1212 if (adreno_gpu->base.needs_hw_init) { 1213 if (a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET)) 1214 goto force_off; 1215 1216 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1217 } 1218 1219 if (test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) 1220 a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1221 1222 ret = a6xx_gmu_wait_for_idle(gmu); 1223 1224 /* If the GMU isn't responding assume it is hung */ 1225 if (ret) 1226 goto force_off; 1227 1228 a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung); 1229 1230 /* tell the GMU we want to slumber */ 1231 ret = a6xx_gmu_notify_slumber(gmu); 1232 if (ret) 1233 goto force_off; 1234 1235 ret = gmu_poll_timeout(gmu, 1236 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 1237 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1238 100, 10000); 1239 1240 /* 1241 * Let the user know we failed to slumber but don't worry too 1242 * much because we are powering down anyway 1243 */ 1244 1245 if (ret) 1246 DRM_DEV_ERROR(gmu->dev, 1247 "Unable to slumber GMU: status = 0%x/0%x\n", 1248 gmu_read(gmu, 1249 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1250 gmu_read(gmu, 1251 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1252 1253 /* Turn off HFI */ 1254 a6xx_hfi_stop(gmu); 1255 1256 /* Stop the interrupts and mask the hardware */ 1257 a6xx_gmu_irq_disable(gmu); 1258 1259 /* Tell RPMh to power off the GPU */ 1260 a6xx_rpmh_stop(gmu); 1261 1262 return; 1263 1264 force_off: 1265 a6xx_gmu_force_off(gmu); 1266 } 1267 1268 1269 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1270 { 1271 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1272 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1273 1274 if (!pm_runtime_active(gmu->dev)) 1275 return 0; 1276 1277 /* 1278 * Force the GMU off if we detected a hang, otherwise try to shut it 1279 * down gracefully 1280 */ 1281 if (gmu->hung) 1282 a6xx_gmu_force_off(gmu); 1283 else 1284 a6xx_gmu_shutdown(gmu); 1285 1286 /* Remove the bus vote */ 1287 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 1288 1289 /* 1290 * Make sure the GX domain is off before turning off the GMU (CX) 1291 * domain. Usually the GMU does this but only if the shutdown sequence 1292 * was successful 1293 */ 1294 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1295 pm_runtime_put_sync(gmu->gxpd); 1296 1297 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1298 1299 pm_runtime_put_sync(gmu->dev); 1300 1301 return 0; 1302 } 1303 1304 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1305 { 1306 struct msm_mmu *mmu = to_msm_vm(gmu->vm)->mmu; 1307 1308 msm_gem_kernel_put(gmu->hfi.obj, gmu->vm); 1309 msm_gem_kernel_put(gmu->debug.obj, gmu->vm); 1310 msm_gem_kernel_put(gmu->icache.obj, gmu->vm); 1311 msm_gem_kernel_put(gmu->dcache.obj, gmu->vm); 1312 msm_gem_kernel_put(gmu->dummy.obj, gmu->vm); 1313 msm_gem_kernel_put(gmu->log.obj, gmu->vm); 1314 1315 mmu->funcs->detach(mmu); 1316 drm_gpuvm_put(gmu->vm); 1317 } 1318 1319 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1320 size_t size, u64 iova, const char *name) 1321 { 1322 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1323 struct drm_device *dev = a6xx_gpu->base.base.dev; 1324 uint32_t flags = MSM_BO_WC; 1325 u64 range_start, range_end; 1326 int ret; 1327 1328 size = PAGE_ALIGN(size); 1329 if (!iova) { 1330 /* no fixed address - use GMU's uncached range */ 1331 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1332 range_end = 0x80000000; 1333 } else { 1334 /* range for fixed address */ 1335 range_start = iova; 1336 range_end = iova + size; 1337 /* use IOMMU_PRIV for icache/dcache */ 1338 flags |= MSM_BO_MAP_PRIV; 1339 } 1340 1341 bo->obj = msm_gem_new(dev, size, flags); 1342 if (IS_ERR(bo->obj)) 1343 return PTR_ERR(bo->obj); 1344 1345 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->vm, &bo->iova, 1346 range_start, range_end); 1347 if (ret) { 1348 drm_gem_object_put(bo->obj); 1349 return ret; 1350 } 1351 1352 bo->virt = msm_gem_get_vaddr(bo->obj); 1353 bo->size = size; 1354 1355 msm_gem_object_set_name(bo->obj, "%s", name); 1356 1357 return 0; 1358 } 1359 1360 static int a6xx_gmu_memory_probe(struct drm_device *drm, struct a6xx_gmu *gmu) 1361 { 1362 struct msm_mmu *mmu; 1363 1364 mmu = msm_iommu_new(gmu->dev, 0); 1365 if (IS_ERR(mmu)) 1366 return PTR_ERR(mmu); 1367 1368 gmu->vm = msm_gem_vm_create(drm, mmu, "gmu", 0x0, 0x80000000, true); 1369 if (IS_ERR(gmu->vm)) 1370 return PTR_ERR(gmu->vm); 1371 1372 return 0; 1373 } 1374 1375 /** 1376 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) 1377 * @unit: divisor used to convert bytes/sec bw value to an RPMh msg 1378 * @width: multiplier used to convert bytes/sec bw value to an RPMh msg 1379 * @vcd: virtual clock domain that this bcm belongs to 1380 * @reserved: reserved field 1381 */ 1382 struct bcm_db { 1383 __le32 unit; 1384 __le16 width; 1385 u8 vcd; 1386 u8 reserved; 1387 }; 1388 1389 static int a6xx_gmu_rpmh_bw_votes_init(struct adreno_gpu *adreno_gpu, 1390 const struct a6xx_info *info, 1391 struct a6xx_gmu *gmu) 1392 { 1393 const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 }; 1394 unsigned int bcm_index, bw_index, bcm_count = 0; 1395 1396 /* Retrieve BCM data from cmd-db */ 1397 for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { 1398 const struct a6xx_bcm *bcm = &info->bcms[bcm_index]; 1399 size_t count; 1400 1401 /* Stop at NULL terminated bcm entry */ 1402 if (!bcm->name) 1403 break; 1404 1405 bcm_data[bcm_index] = cmd_db_read_aux_data(bcm->name, &count); 1406 if (IS_ERR(bcm_data[bcm_index])) 1407 return PTR_ERR(bcm_data[bcm_index]); 1408 1409 if (!count) { 1410 dev_err(gmu->dev, "invalid BCM '%s' aux data size\n", 1411 bcm->name); 1412 return -EINVAL; 1413 } 1414 1415 bcm_count++; 1416 } 1417 1418 /* Generate BCM votes values for each bandwidth & BCM */ 1419 for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) { 1420 u32 *data = gmu->gpu_ib_votes[bw_index]; 1421 u32 bw = gmu->gpu_bw_table[bw_index]; 1422 1423 /* Calculations loosely copied from bcm_aggregate() & tcs_cmd_gen() */ 1424 for (bcm_index = 0; bcm_index < bcm_count; bcm_index++) { 1425 const struct a6xx_bcm *bcm = &info->bcms[bcm_index]; 1426 bool commit = false; 1427 u64 peak; 1428 u32 vote; 1429 1430 if (bcm_index == bcm_count - 1 || 1431 (bcm_data[bcm_index + 1] && 1432 bcm_data[bcm_index]->vcd != bcm_data[bcm_index + 1]->vcd)) 1433 commit = true; 1434 1435 if (!bw) { 1436 data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0); 1437 continue; 1438 } 1439 1440 if (bcm->fixed) { 1441 u32 perfmode = 0; 1442 1443 /* GMU on A6xx votes perfmode on all valid bandwidth */ 1444 if (!adreno_is_a7xx(adreno_gpu) || 1445 (bcm->perfmode_bw && bw >= bcm->perfmode_bw)) 1446 perfmode = bcm->perfmode; 1447 1448 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode); 1449 continue; 1450 } 1451 1452 /* Multiply the bandwidth by the width of the connection */ 1453 peak = (u64)bw * le16_to_cpu(bcm_data[bcm_index]->width); 1454 do_div(peak, bcm->buswidth); 1455 1456 /* Input bandwidth value is in KBps, scale the value to BCM unit */ 1457 peak *= 1000; 1458 do_div(peak, le32_to_cpu(bcm_data[bcm_index]->unit)); 1459 1460 vote = clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK); 1461 1462 /* GMUs on A7xx votes on both x & y */ 1463 if (adreno_is_a7xx(adreno_gpu)) 1464 data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote); 1465 else 1466 data[bcm_index] = BCM_TCS_CMD(commit, true, 0, vote); 1467 } 1468 } 1469 1470 return 0; 1471 } 1472 1473 /* Return the 'arc-level' for the given frequency */ 1474 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1475 unsigned long freq) 1476 { 1477 struct dev_pm_opp *opp; 1478 unsigned int val; 1479 1480 if (!freq) 1481 return 0; 1482 1483 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1484 if (IS_ERR(opp)) 1485 return 0; 1486 1487 val = dev_pm_opp_get_level(opp); 1488 1489 dev_pm_opp_put(opp); 1490 1491 return val; 1492 } 1493 1494 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1495 unsigned long *freqs, int freqs_count, const char *id) 1496 { 1497 int i, j; 1498 const u16 *pri, *sec; 1499 size_t pri_count, sec_count; 1500 1501 pri = cmd_db_read_aux_data(id, &pri_count); 1502 if (IS_ERR(pri)) 1503 return PTR_ERR(pri); 1504 /* 1505 * The data comes back as an array of unsigned shorts so adjust the 1506 * count accordingly 1507 */ 1508 pri_count >>= 1; 1509 if (!pri_count) 1510 return -EINVAL; 1511 1512 /* 1513 * Some targets have a separate gfx mxc rail. So try to read that first and then fall back 1514 * to regular mx rail if it is missing 1515 */ 1516 sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); 1517 if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER)) 1518 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1519 if (IS_ERR(sec)) 1520 return PTR_ERR(sec); 1521 1522 sec_count >>= 1; 1523 if (!sec_count) 1524 return -EINVAL; 1525 1526 /* Construct a vote for each frequency */ 1527 for (i = 0; i < freqs_count; i++) { 1528 u8 pindex = 0, sindex = 0; 1529 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1530 1531 /* Get the primary index that matches the arc level */ 1532 for (j = 0; j < pri_count; j++) { 1533 if (pri[j] >= level) { 1534 pindex = j; 1535 break; 1536 } 1537 } 1538 1539 if (j == pri_count) { 1540 DRM_DEV_ERROR(dev, 1541 "Level %u not found in the RPMh list\n", 1542 level); 1543 DRM_DEV_ERROR(dev, "Available levels:\n"); 1544 for (j = 0; j < pri_count; j++) 1545 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1546 1547 return -EINVAL; 1548 } 1549 1550 /* 1551 * Look for a level in in the secondary list that matches. If 1552 * nothing fits, use the maximum non zero vote 1553 */ 1554 1555 for (j = 0; j < sec_count; j++) { 1556 if (sec[j] >= level) { 1557 sindex = j; 1558 break; 1559 } else if (sec[j]) { 1560 sindex = j; 1561 } 1562 } 1563 1564 /* Construct the vote */ 1565 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1566 (sindex << 8) | pindex; 1567 } 1568 1569 return 0; 1570 } 1571 1572 /* 1573 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1574 * to construct the list of votes on the CPU and send it over. Query the RPMh 1575 * voltage levels and build the votes 1576 * The GMU can also vote for DDR interconnects, use the OPP bandwidth entries 1577 * and BCM parameters to build the votes. 1578 */ 1579 1580 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1581 { 1582 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1583 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1584 const struct a6xx_info *info = adreno_gpu->info->a6xx; 1585 struct msm_gpu *gpu = &adreno_gpu->base; 1586 int ret; 1587 1588 /* Build the GX votes */ 1589 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1590 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1591 1592 /* Build the CX votes */ 1593 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1594 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1595 1596 /* Build the interconnect votes */ 1597 if (info->bcms && gmu->nr_gpu_bws > 1) 1598 ret |= a6xx_gmu_rpmh_bw_votes_init(adreno_gpu, info, gmu); 1599 1600 return ret; 1601 } 1602 1603 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1604 u32 size) 1605 { 1606 int count = dev_pm_opp_get_opp_count(dev); 1607 struct dev_pm_opp *opp; 1608 int i, index = 0; 1609 unsigned long freq = 1; 1610 1611 /* 1612 * The OPP table doesn't contain the "off" frequency level so we need to 1613 * add 1 to the table size to account for it 1614 */ 1615 1616 if (WARN(count + 1 > size, 1617 "The GMU frequency table is being truncated\n")) 1618 count = size - 1; 1619 1620 /* Set the "off" frequency */ 1621 freqs[index++] = 0; 1622 1623 for (i = 0; i < count; i++) { 1624 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1625 if (IS_ERR(opp)) 1626 break; 1627 1628 dev_pm_opp_put(opp); 1629 freqs[index++] = freq++; 1630 } 1631 1632 return index; 1633 } 1634 1635 static int a6xx_gmu_build_bw_table(struct device *dev, unsigned long *bandwidths, 1636 u32 size) 1637 { 1638 int count = dev_pm_opp_get_opp_count(dev); 1639 struct dev_pm_opp *opp; 1640 int i, index = 0; 1641 unsigned int bandwidth = 1; 1642 1643 /* 1644 * The OPP table doesn't contain the "off" bandwidth level so we need to 1645 * add 1 to the table size to account for it 1646 */ 1647 1648 if (WARN(count + 1 > size, 1649 "The GMU bandwidth table is being truncated\n")) 1650 count = size - 1; 1651 1652 /* Set the "off" bandwidth */ 1653 bandwidths[index++] = 0; 1654 1655 for (i = 0; i < count; i++) { 1656 opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0); 1657 if (IS_ERR(opp)) 1658 break; 1659 1660 dev_pm_opp_put(opp); 1661 bandwidths[index++] = bandwidth++; 1662 } 1663 1664 return index; 1665 } 1666 1667 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1668 { 1669 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1670 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1671 const struct a6xx_info *info = adreno_gpu->info->a6xx; 1672 struct msm_gpu *gpu = &adreno_gpu->base; 1673 1674 int ret = 0; 1675 1676 /* 1677 * The GMU handles its own frequency switching so build a list of 1678 * available frequencies to send during initialization 1679 */ 1680 ret = devm_pm_opp_of_add_table(gmu->dev); 1681 if (ret) { 1682 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1683 return ret; 1684 } 1685 1686 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1687 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1688 1689 /* 1690 * The GMU also handles GPU frequency switching so build a list 1691 * from the GPU OPP table 1692 */ 1693 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1694 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1695 1696 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1697 1698 /* 1699 * The GMU also handles GPU Interconnect Votes so build a list 1700 * of DDR bandwidths from the GPU OPP table 1701 */ 1702 if (info->bcms) 1703 gmu->nr_gpu_bws = a6xx_gmu_build_bw_table(&gpu->pdev->dev, 1704 gmu->gpu_bw_table, ARRAY_SIZE(gmu->gpu_bw_table)); 1705 1706 /* Build the list of RPMh votes that we'll send to the GMU */ 1707 return a6xx_gmu_rpmh_votes_init(gmu); 1708 } 1709 1710 static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) 1711 { 1712 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1713 struct a6xx_hfi_acd_table *cmd = &gmu->acd_table; 1714 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1715 struct msm_gpu *gpu = &adreno_gpu->base; 1716 int ret, i, cmd_idx = 0; 1717 extern bool disable_acd; 1718 1719 /* Skip ACD probe if requested via module param */ 1720 if (disable_acd) { 1721 DRM_DEV_ERROR(gmu->dev, "Skipping GPU ACD probe\n"); 1722 return 0; 1723 } 1724 1725 cmd->version = 1; 1726 cmd->stride = 1; 1727 cmd->enable_by_level = 0; 1728 1729 /* Skip freq = 0 and parse acd-level for rest of the OPPs */ 1730 for (i = 1; i < gmu->nr_gpu_freqs; i++) { 1731 struct dev_pm_opp *opp; 1732 struct device_node *np; 1733 unsigned long freq; 1734 u32 val; 1735 1736 freq = gmu->gpu_freqs[i]; 1737 /* This is unlikely to fail because we are passing back a known freq */ 1738 opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, freq, true); 1739 np = dev_pm_opp_get_of_node(opp); 1740 1741 ret = of_property_read_u32(np, "qcom,opp-acd-level", &val); 1742 of_node_put(np); 1743 dev_pm_opp_put(opp); 1744 if (ret == -EINVAL) 1745 continue; 1746 else if (ret) { 1747 DRM_DEV_ERROR(gmu->dev, "Unable to read acd level for freq %lu\n", freq); 1748 return ret; 1749 } 1750 1751 cmd->enable_by_level |= BIT(i); 1752 cmd->data[cmd_idx++] = val; 1753 } 1754 1755 cmd->num_levels = cmd_idx; 1756 1757 /* It is a problem if qmp node is unavailable when ACD is required */ 1758 if (cmd->enable_by_level && IS_ERR_OR_NULL(gmu->qmp)) { 1759 DRM_DEV_ERROR(gmu->dev, "Unable to send ACD state to AOSS\n"); 1760 return -EINVAL; 1761 } 1762 1763 /* Otherwise, nothing to do if qmp is unavailable */ 1764 if (IS_ERR_OR_NULL(gmu->qmp)) 1765 return 0; 1766 1767 /* 1768 * Notify AOSS about the ACD state. AOSS is supposed to assume that ACD is disabled on 1769 * system reset. So it is harmless if we couldn't notify 'OFF' state 1770 */ 1771 ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", !!cmd->enable_by_level); 1772 if (ret && cmd->enable_by_level) { 1773 DRM_DEV_ERROR(gmu->dev, "Failed to send ACD state to AOSS\n"); 1774 return ret; 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1781 { 1782 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1783 1784 if (ret < 1) 1785 return ret; 1786 1787 gmu->nr_clocks = ret; 1788 1789 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1790 gmu->nr_clocks, "gmu"); 1791 1792 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks, 1793 gmu->nr_clocks, "hub"); 1794 1795 return 0; 1796 } 1797 1798 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1799 const char *name) 1800 { 1801 void __iomem *ret; 1802 struct resource *res = platform_get_resource_byname(pdev, 1803 IORESOURCE_MEM, name); 1804 1805 if (!res) { 1806 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1807 return ERR_PTR(-EINVAL); 1808 } 1809 1810 ret = ioremap(res->start, resource_size(res)); 1811 if (!ret) { 1812 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1813 return ERR_PTR(-EINVAL); 1814 } 1815 1816 return ret; 1817 } 1818 1819 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1820 const char *name, irq_handler_t handler) 1821 { 1822 int irq, ret; 1823 1824 irq = platform_get_irq_byname(pdev, name); 1825 1826 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, name, gmu); 1827 if (ret) { 1828 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1829 name, ret); 1830 return ret; 1831 } 1832 1833 return irq; 1834 } 1835 1836 void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) 1837 { 1838 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1839 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1840 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1841 unsigned int sysprof_active; 1842 1843 /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ 1844 if (!pm_runtime_get_if_active(&gpu->pdev->dev)) 1845 return; 1846 1847 mutex_lock(&gmu->lock); 1848 1849 sysprof_active = refcount_read(&gpu->sysprof_active); 1850 1851 /* 1852 * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, 1853 * use the currently unused perfcounter oob vote to block IFPC when sysprof is active 1854 */ 1855 if ((sysprof_active > 1) && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) 1856 a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1857 else if ((sysprof_active == 1) && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) 1858 a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1859 1860 mutex_unlock(&gmu->lock); 1861 1862 pm_runtime_put(&gpu->pdev->dev); 1863 } 1864 1865 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1866 { 1867 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1868 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1869 struct platform_device *pdev = to_platform_device(gmu->dev); 1870 1871 mutex_lock(&gmu->lock); 1872 if (!gmu->initialized) { 1873 mutex_unlock(&gmu->lock); 1874 return; 1875 } 1876 1877 gmu->initialized = false; 1878 1879 mutex_unlock(&gmu->lock); 1880 1881 pm_runtime_force_suspend(gmu->dev); 1882 1883 /* 1884 * Since cxpd is a virt device, the devlink with gmu-dev will be removed 1885 * automatically when we do detach 1886 */ 1887 dev_pm_domain_detach(gmu->cxpd, false); 1888 1889 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1890 pm_runtime_disable(gmu->gxpd); 1891 dev_pm_domain_detach(gmu->gxpd, false); 1892 } 1893 1894 if (!IS_ERR_OR_NULL(gmu->qmp)) 1895 qmp_put(gmu->qmp); 1896 1897 iounmap(gmu->mmio); 1898 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1899 iounmap(gmu->rscc); 1900 gmu->mmio = NULL; 1901 gmu->rscc = NULL; 1902 1903 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1904 a6xx_gmu_memory_free(gmu); 1905 1906 free_irq(gmu->gmu_irq, gmu); 1907 free_irq(gmu->hfi_irq, gmu); 1908 } 1909 1910 /* Drop reference taken in of_find_device_by_node */ 1911 put_device(gmu->dev); 1912 } 1913 1914 static int cxpd_notifier_cb(struct notifier_block *nb, 1915 unsigned long action, void *data) 1916 { 1917 struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb); 1918 1919 if (action == GENPD_NOTIFY_OFF) 1920 complete_all(&gmu->pd_gate); 1921 1922 return 0; 1923 } 1924 1925 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1926 { 1927 struct platform_device *pdev = of_find_device_by_node(node); 1928 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1929 int ret; 1930 1931 if (!pdev) 1932 return -ENODEV; 1933 1934 gmu->dev = &pdev->dev; 1935 1936 ret = of_dma_configure(gmu->dev, node, true); 1937 if (ret) 1938 return ret; 1939 1940 pm_runtime_enable(gmu->dev); 1941 1942 /* Mark legacy for manual SPTPRAC control */ 1943 gmu->legacy = true; 1944 1945 /* Map the GMU registers */ 1946 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1947 if (IS_ERR(gmu->mmio)) { 1948 ret = PTR_ERR(gmu->mmio); 1949 goto err_mmio; 1950 } 1951 1952 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); 1953 if (IS_ERR(gmu->cxpd)) { 1954 ret = PTR_ERR(gmu->cxpd); 1955 goto err_mmio; 1956 } 1957 1958 if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { 1959 ret = -ENODEV; 1960 goto detach_cxpd; 1961 } 1962 1963 init_completion(&gmu->pd_gate); 1964 complete_all(&gmu->pd_gate); 1965 gmu->pd_nb.notifier_call = cxpd_notifier_cb; 1966 1967 /* Get a link to the GX power domain to reset the GPU */ 1968 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1969 if (IS_ERR(gmu->gxpd)) { 1970 ret = PTR_ERR(gmu->gxpd); 1971 goto err_mmio; 1972 } 1973 1974 gmu->initialized = true; 1975 1976 return 0; 1977 1978 detach_cxpd: 1979 dev_pm_domain_detach(gmu->cxpd, false); 1980 1981 err_mmio: 1982 iounmap(gmu->mmio); 1983 1984 /* Drop reference taken in of_find_device_by_node */ 1985 put_device(gmu->dev); 1986 1987 return ret; 1988 } 1989 1990 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1991 { 1992 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1993 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1994 struct platform_device *pdev = of_find_device_by_node(node); 1995 struct device_link *link; 1996 int ret; 1997 1998 if (!pdev) 1999 return -ENODEV; 2000 2001 gmu->dev = &pdev->dev; 2002 2003 ret = of_dma_configure(gmu->dev, node, true); 2004 if (ret) 2005 return ret; 2006 2007 /* Set GMU idle level */ 2008 gmu->idle_level = (adreno_gpu->info->quirks & ADRENO_QUIRK_IFPC) ? 2009 GMU_IDLE_STATE_IFPC : GMU_IDLE_STATE_ACTIVE; 2010 2011 pm_runtime_enable(gmu->dev); 2012 2013 /* Get the list of clocks */ 2014 ret = a6xx_gmu_clocks_probe(gmu); 2015 if (ret) 2016 goto err_put_device; 2017 2018 ret = a6xx_gmu_memory_probe(adreno_gpu->base.dev, gmu); 2019 if (ret) 2020 goto err_put_device; 2021 2022 2023 /* A660 now requires handling "prealloc requests" in GMU firmware 2024 * For now just hardcode allocations based on the known firmware. 2025 * note: there is no indication that these correspond to "dummy" or 2026 * "debug" regions, but this "guess" allows reusing these BOs which 2027 * are otherwise unused by a660. 2028 */ 2029 gmu->dummy.size = SZ_4K; 2030 if (adreno_is_a660_family(adreno_gpu) || 2031 adreno_is_a7xx(adreno_gpu)) { 2032 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 2033 0x60400000, "debug"); 2034 if (ret) 2035 goto err_memory; 2036 2037 gmu->dummy.size = SZ_8K; 2038 } 2039 2040 /* Allocate memory for the GMU dummy page */ 2041 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 2042 0x60000000, "dummy"); 2043 if (ret) 2044 goto err_memory; 2045 2046 /* Note that a650 family also includes a660 family: */ 2047 if (adreno_is_a650_family(adreno_gpu) || 2048 adreno_is_a7xx(adreno_gpu)) { 2049 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 2050 SZ_16M - SZ_16K, 0x04000, "icache"); 2051 if (ret) 2052 goto err_memory; 2053 /* 2054 * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition 2055 * to allocate icache/dcache here, as per downstream code flow, but it may not actually be 2056 * necessary. If you omit this step and you don't get random pagefaults, you are likely 2057 * good to go without this! 2058 */ 2059 } else if (adreno_is_a640_family(adreno_gpu)) { 2060 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 2061 SZ_256K - SZ_16K, 0x04000, "icache"); 2062 if (ret) 2063 goto err_memory; 2064 2065 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 2066 SZ_256K - SZ_16K, 0x44000, "dcache"); 2067 if (ret) 2068 goto err_memory; 2069 } else if (adreno_is_a630_family(adreno_gpu)) { 2070 /* HFI v1, has sptprac */ 2071 gmu->legacy = true; 2072 2073 /* Allocate memory for the GMU debug region */ 2074 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug"); 2075 if (ret) 2076 goto err_memory; 2077 } 2078 2079 /* Allocate memory for the GMU log region */ 2080 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log"); 2081 if (ret) 2082 goto err_memory; 2083 2084 /* Allocate memory for for the HFI queues */ 2085 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); 2086 if (ret) 2087 goto err_memory; 2088 2089 /* Map the GMU registers */ 2090 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 2091 if (IS_ERR(gmu->mmio)) { 2092 ret = PTR_ERR(gmu->mmio); 2093 goto err_memory; 2094 } 2095 2096 if (adreno_is_a650_family(adreno_gpu) || 2097 adreno_is_a7xx(adreno_gpu)) { 2098 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 2099 if (IS_ERR(gmu->rscc)) { 2100 ret = -ENODEV; 2101 goto err_mmio; 2102 } 2103 } else { 2104 gmu->rscc = gmu->mmio + 0x23000; 2105 } 2106 2107 /* Get the HFI and GMU interrupts */ 2108 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 2109 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 2110 2111 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) { 2112 ret = -ENODEV; 2113 goto err_mmio; 2114 } 2115 2116 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); 2117 if (IS_ERR(gmu->cxpd)) { 2118 ret = PTR_ERR(gmu->cxpd); 2119 goto err_mmio; 2120 } 2121 2122 link = device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME); 2123 if (!link) { 2124 ret = -ENODEV; 2125 goto detach_cxpd; 2126 } 2127 2128 /* Other errors are handled during GPU ACD probe */ 2129 gmu->qmp = qmp_get(gmu->dev); 2130 if (PTR_ERR_OR_ZERO(gmu->qmp) == -EPROBE_DEFER) { 2131 ret = -EPROBE_DEFER; 2132 goto detach_gxpd; 2133 } 2134 2135 init_completion(&gmu->pd_gate); 2136 complete_all(&gmu->pd_gate); 2137 gmu->pd_nb.notifier_call = cxpd_notifier_cb; 2138 2139 /* 2140 * Get a link to the GX power domain to reset the GPU in case of GMU 2141 * crash 2142 */ 2143 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 2144 2145 /* Get the power levels for the GMU and GPU */ 2146 a6xx_gmu_pwrlevels_probe(gmu); 2147 2148 ret = a6xx_gmu_acd_probe(gmu); 2149 if (ret) 2150 goto detach_gxpd; 2151 2152 /* Set up the HFI queues */ 2153 a6xx_hfi_init(gmu); 2154 2155 /* Initialize RPMh */ 2156 a6xx_gmu_rpmh_init(gmu); 2157 2158 gmu->initialized = true; 2159 2160 return 0; 2161 2162 detach_gxpd: 2163 if (!IS_ERR_OR_NULL(gmu->gxpd)) 2164 dev_pm_domain_detach(gmu->gxpd, false); 2165 2166 if (!IS_ERR_OR_NULL(gmu->qmp)) 2167 qmp_put(gmu->qmp); 2168 2169 device_link_del(link); 2170 2171 detach_cxpd: 2172 dev_pm_domain_detach(gmu->cxpd, false); 2173 2174 err_mmio: 2175 iounmap(gmu->mmio); 2176 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 2177 iounmap(gmu->rscc); 2178 free_irq(gmu->gmu_irq, gmu); 2179 free_irq(gmu->hfi_irq, gmu); 2180 2181 err_memory: 2182 a6xx_gmu_memory_free(gmu); 2183 err_put_device: 2184 /* Drop reference taken in of_find_device_by_node */ 2185 put_device(gmu->dev); 2186 2187 return ret; 2188 } 2189