1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 #include "a6xx_gpu.h" 11 #include "a6xx.xml.h" 12 #include "a6xx_gmu.xml.h" 13 14 static const struct adreno_reglist a612_hwcg[] = { 15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, 18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 25 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 26 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 27 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 28 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 29 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 30 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 31 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 32 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, 33 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 34 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 35 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, 36 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 37 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 38 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 39 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 40 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 41 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, 42 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 43 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 44 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 45 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 46 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 47 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 48 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 49 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 50 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 51 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 52 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 53 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 54 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 55 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 56 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 57 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 58 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 59 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 60 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 61 {}, 62 }; 63 64 /* For a615 family (a615, a616, a618 and a619) */ 65 static const struct adreno_reglist a615_hwcg[] = { 66 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 67 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 68 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 69 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 70 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 71 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 72 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 73 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 74 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 75 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 76 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 77 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 78 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 79 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 80 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 81 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 82 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 83 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 84 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 85 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 86 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 87 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 88 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 89 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 90 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 91 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 92 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 93 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 94 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 95 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 96 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 97 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 98 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 99 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 100 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 101 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 102 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020}, 103 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 104 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 105 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 106 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 107 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, 108 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, 109 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, 110 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 111 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 112 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 113 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 114 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 115 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 116 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 117 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 118 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 119 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 120 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 121 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 122 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 123 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 124 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 125 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 126 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 127 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 128 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 129 {}, 130 }; 131 132 static const struct adreno_reglist a630_hwcg[] = { 133 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 134 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 135 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 136 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 137 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 138 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 139 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 140 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 141 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 142 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 143 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 144 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 145 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 146 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 147 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 148 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 149 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 150 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 151 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 152 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 153 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 154 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 155 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 156 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 157 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 158 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 159 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 160 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 161 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 162 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 163 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 164 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 165 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 166 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 167 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 168 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 169 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 170 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 171 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 172 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 173 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 174 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 175 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 176 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 177 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 178 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 179 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 180 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 181 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 182 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 183 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 184 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 185 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 186 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 187 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 188 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 189 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 190 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 191 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 192 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 193 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 194 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 195 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 196 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 197 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 198 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 199 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 200 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 201 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 202 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 203 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 204 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 205 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 206 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 207 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 208 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 209 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 210 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 211 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 212 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 213 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 214 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 215 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 216 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 217 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 218 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 219 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 220 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 221 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 222 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 223 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 224 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 225 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 226 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 227 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 228 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 229 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 230 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 231 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 232 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 233 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 234 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 235 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 236 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 237 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 238 {}, 239 }; 240 241 static const struct adreno_reglist a640_hwcg[] = { 242 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 243 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 244 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 245 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 246 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 247 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 248 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 249 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 250 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 251 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 252 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 253 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 254 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 255 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 256 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 257 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 258 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 259 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 260 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 261 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 262 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 263 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 264 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 265 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 266 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 267 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 268 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 269 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 270 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 271 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 272 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 273 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 274 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 275 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 276 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 277 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 278 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 279 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 280 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 281 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 282 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 283 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 284 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 285 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 286 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 287 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 288 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 289 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 290 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 291 {}, 292 }; 293 294 static const struct adreno_reglist a650_hwcg[] = { 295 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 296 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 297 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 298 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 299 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 300 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 301 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 302 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 303 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 304 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 305 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 306 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 307 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 308 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 309 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 310 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 311 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 312 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 313 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 314 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 315 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 316 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 317 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 318 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 319 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 321 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 322 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 323 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 324 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 325 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 327 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 328 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 329 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 330 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 331 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 332 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 333 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 334 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 336 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 337 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 338 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 339 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 340 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 341 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 342 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 343 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 344 {}, 345 }; 346 347 static const struct adreno_reglist a660_hwcg[] = { 348 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 349 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 350 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 351 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 352 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 353 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 354 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 356 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 357 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 358 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 359 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 360 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 362 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 363 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 364 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 365 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 366 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 367 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 368 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 369 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 370 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 371 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 372 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 373 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 374 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 375 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 376 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 377 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 378 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 379 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 380 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 381 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 382 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 383 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 384 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 385 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 386 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 387 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 388 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 389 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 390 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 391 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 392 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 393 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 394 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 395 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 396 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 397 {}, 398 }; 399 400 static const struct adreno_reglist a690_hwcg[] = { 401 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 402 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 403 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 404 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 405 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 406 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 407 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 408 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 409 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 410 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 411 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 412 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 413 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 414 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 415 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 416 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 417 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 418 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 419 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 420 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 421 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 422 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 423 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 424 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 425 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 426 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 427 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 428 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 429 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 430 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 431 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 432 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 433 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 434 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 435 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 436 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 437 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 438 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 439 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 440 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 441 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 444 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82}, 445 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 446 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 447 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 448 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 449 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 450 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 451 {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200}, 452 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, 453 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, 454 {} 455 }; 456 457 /* For a615, a616, a618, a619, a630, a640 and a680 */ 458 static const u32 a630_protect_regs[] = { 459 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 460 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 461 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 462 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 463 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 464 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 465 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 466 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 467 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 468 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 469 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 470 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 471 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 472 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 473 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 474 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 475 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 476 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 477 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 478 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 479 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 480 A6XX_PROTECT_NORDWR(0x09e70, 0x0001), 481 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 482 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 483 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 484 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 485 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 486 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 487 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 488 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 489 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 490 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ 491 }; 492 DECLARE_ADRENO_PROTECT(a630_protect, 32); 493 494 /* These are for a620 and a650 */ 495 static const u32 a650_protect_regs[] = { 496 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 497 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 498 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 499 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 500 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 501 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 502 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 503 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 504 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 505 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 506 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 507 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 508 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 509 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 510 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 511 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 512 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 513 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 514 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 515 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 516 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 517 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 518 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 519 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 520 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 521 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 522 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 523 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 524 A6XX_PROTECT_NORDWR(0x0b608, 0x0007), 525 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 526 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 527 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 528 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 529 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 530 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), 531 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 532 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 533 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 534 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 535 }; 536 DECLARE_ADRENO_PROTECT(a650_protect, 48); 537 538 /* These are for a635 and a660 */ 539 static const u32 a660_protect_regs[] = { 540 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 541 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 542 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 543 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 544 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 545 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 546 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 547 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 548 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 549 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 550 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 551 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 552 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 553 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 554 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 555 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 556 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 557 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 558 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 559 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 560 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 561 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 562 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 563 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 564 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 565 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 566 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), 567 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 568 A6XX_PROTECT_NORDWR(0x0b608, 0x0006), 569 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 570 A6XX_PROTECT_NORDWR(0x0be20, 0x015f), 571 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), 572 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 573 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 574 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 575 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), 576 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 577 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 578 A6XX_PROTECT_NORDWR(0x1f860, 0x0000), 579 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 580 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 581 }; 582 DECLARE_ADRENO_PROTECT(a660_protect, 48); 583 584 /* These are for a690 */ 585 static const u32 a690_protect_regs[] = { 586 A6XX_PROTECT_RDONLY(0x00000, 0x004ff), 587 A6XX_PROTECT_RDONLY(0x00501, 0x00001), 588 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4), 589 A6XX_PROTECT_NORDWR(0x0050e, 0x00000), 590 A6XX_PROTECT_NORDWR(0x00510, 0x00000), 591 A6XX_PROTECT_NORDWR(0x00534, 0x00000), 592 A6XX_PROTECT_NORDWR(0x00800, 0x00082), 593 A6XX_PROTECT_NORDWR(0x008a0, 0x00008), 594 A6XX_PROTECT_NORDWR(0x008ab, 0x00024), 595 A6XX_PROTECT_RDONLY(0x008de, 0x000ae), 596 A6XX_PROTECT_NORDWR(0x00900, 0x0004d), 597 A6XX_PROTECT_NORDWR(0x0098d, 0x00272), 598 A6XX_PROTECT_NORDWR(0x00e00, 0x00001), 599 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c), 600 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3), 601 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff), 602 A6XX_PROTECT_NORDWR(0x08630, 0x001cf), 603 A6XX_PROTECT_NORDWR(0x08e00, 0x00000), 604 A6XX_PROTECT_NORDWR(0x08e08, 0x00007), 605 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f), 606 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f), 607 A6XX_PROTECT_NORDWR(0x09624, 0x001db), 608 A6XX_PROTECT_NORDWR(0x09e60, 0x00011), 609 A6XX_PROTECT_NORDWR(0x09e78, 0x00187), 610 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf), 611 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000), 612 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f), 613 A6XX_PROTECT_NORDWR(0x0b604, 0x00000), 614 A6XX_PROTECT_NORDWR(0x0b608, 0x00006), 615 A6XX_PROTECT_NORDWR(0x0be02, 0x00001), 616 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f), 617 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff), 618 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff), 619 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff), 620 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */ 621 }; 622 DECLARE_ADRENO_PROTECT(a690_protect, 48); 623 624 static const struct adreno_info a6xx_gpus[] = { 625 { 626 .chip_ids = ADRENO_CHIP_IDS(0x06010000), 627 .family = ADRENO_6XX_GEN1, 628 .revn = 610, 629 .fw = { 630 [ADRENO_FW_SQE] = "a630_sqe.fw", 631 }, 632 .gmem = (SZ_128K + SZ_4K), 633 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 634 .init = a6xx_gpu_init, 635 .zapfw = "a610_zap.mdt", 636 .a6xx = &(const struct a6xx_info) { 637 .hwcg = a612_hwcg, 638 .protect = &a630_protect, 639 }, 640 /* 641 * There are (at least) three SoCs implementing A610: SM6125 642 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does 643 * not have speedbinning, as only a single SKU exists and we 644 * don't support khaje upstream yet. Hence, this matching 645 * table is only valid for bengal. 646 */ 647 .speedbins = ADRENO_SPEEDBINS( 648 { 0, 0 }, 649 { 206, 1 }, 650 { 200, 2 }, 651 { 157, 3 }, 652 { 127, 4 }, 653 ), 654 }, { 655 .machine = "qcom,sm7150", 656 .chip_ids = ADRENO_CHIP_IDS(0x06010800), 657 .family = ADRENO_6XX_GEN1, 658 .fw = { 659 [ADRENO_FW_SQE] = "a630_sqe.fw", 660 [ADRENO_FW_GMU] = "a630_gmu.bin", 661 }, 662 .gmem = SZ_512K, 663 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 664 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 665 .init = a6xx_gpu_init, 666 .zapfw = "a615_zap.mbn", 667 .a6xx = &(const struct a6xx_info) { 668 .hwcg = a615_hwcg, 669 .protect = &a630_protect, 670 }, 671 .speedbins = ADRENO_SPEEDBINS( 672 { 0, 0 }, 673 { 128, 1 }, 674 { 146, 2 }, 675 { 167, 3 }, 676 { 172, 4 }, 677 ), 678 }, { 679 .chip_ids = ADRENO_CHIP_IDS(0x06010800), 680 .family = ADRENO_6XX_GEN1, 681 .revn = 618, 682 .fw = { 683 [ADRENO_FW_SQE] = "a630_sqe.fw", 684 [ADRENO_FW_GMU] = "a630_gmu.bin", 685 }, 686 .gmem = SZ_512K, 687 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 688 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 689 .init = a6xx_gpu_init, 690 .a6xx = &(const struct a6xx_info) { 691 .protect = &a630_protect, 692 }, 693 .speedbins = ADRENO_SPEEDBINS( 694 { 0, 0 }, 695 { 169, 1 }, 696 { 174, 2 }, 697 ), 698 }, { 699 .machine = "qcom,sm4350", 700 .chip_ids = ADRENO_CHIP_IDS(0x06010900), 701 .family = ADRENO_6XX_GEN1, 702 .revn = 619, 703 .fw = { 704 [ADRENO_FW_SQE] = "a630_sqe.fw", 705 [ADRENO_FW_GMU] = "a619_gmu.bin", 706 }, 707 .gmem = SZ_512K, 708 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 709 .init = a6xx_gpu_init, 710 .zapfw = "a615_zap.mdt", 711 .a6xx = &(const struct a6xx_info) { 712 .hwcg = a615_hwcg, 713 .protect = &a630_protect, 714 }, 715 .speedbins = ADRENO_SPEEDBINS( 716 { 0, 0 }, 717 { 138, 1 }, 718 { 92, 2 }, 719 ), 720 }, { 721 .machine = "qcom,sm6375", 722 .chip_ids = ADRENO_CHIP_IDS(0x06010901), 723 .family = ADRENO_6XX_GEN1, 724 .revn = 619, 725 .fw = { 726 [ADRENO_FW_SQE] = "a630_sqe.fw", 727 [ADRENO_FW_GMU] = "a619_gmu.bin", 728 }, 729 .gmem = SZ_512K, 730 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 731 .init = a6xx_gpu_init, 732 .zapfw = "a615_zap.mdt", 733 .a6xx = &(const struct a6xx_info) { 734 .hwcg = a615_hwcg, 735 .protect = &a630_protect, 736 }, 737 .speedbins = ADRENO_SPEEDBINS( 738 { 0, 0 }, 739 { 190, 1 }, 740 { 177, 2 }, 741 ), 742 }, { 743 .chip_ids = ADRENO_CHIP_IDS(0x06010900), 744 .family = ADRENO_6XX_GEN1, 745 .revn = 619, 746 .fw = { 747 [ADRENO_FW_SQE] = "a630_sqe.fw", 748 [ADRENO_FW_GMU] = "a619_gmu.bin", 749 }, 750 .gmem = SZ_512K, 751 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 752 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 753 .init = a6xx_gpu_init, 754 .zapfw = "a615_zap.mdt", 755 .a6xx = &(const struct a6xx_info) { 756 .hwcg = a615_hwcg, 757 .protect = &a630_protect, 758 }, 759 .speedbins = ADRENO_SPEEDBINS( 760 { 0, 0 }, 761 { 120, 4 }, 762 { 138, 3 }, 763 { 169, 2 }, 764 { 180, 1 }, 765 ), 766 }, { 767 .chip_ids = ADRENO_CHIP_IDS( 768 0x06030001, 769 0x06030002 770 ), 771 .family = ADRENO_6XX_GEN1, 772 .revn = 630, 773 .fw = { 774 [ADRENO_FW_SQE] = "a630_sqe.fw", 775 [ADRENO_FW_GMU] = "a630_gmu.bin", 776 }, 777 .gmem = SZ_1M, 778 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 779 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 780 .init = a6xx_gpu_init, 781 .zapfw = "a630_zap.mdt", 782 .a6xx = &(const struct a6xx_info) { 783 .hwcg = a630_hwcg, 784 .protect = &a630_protect, 785 }, 786 }, { 787 .chip_ids = ADRENO_CHIP_IDS(0x06040001), 788 .family = ADRENO_6XX_GEN2, 789 .revn = 640, 790 .fw = { 791 [ADRENO_FW_SQE] = "a630_sqe.fw", 792 [ADRENO_FW_GMU] = "a640_gmu.bin", 793 }, 794 .gmem = SZ_1M, 795 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 796 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 797 .init = a6xx_gpu_init, 798 .zapfw = "a640_zap.mdt", 799 .a6xx = &(const struct a6xx_info) { 800 .hwcg = a640_hwcg, 801 .protect = &a630_protect, 802 }, 803 .speedbins = ADRENO_SPEEDBINS( 804 { 0, 0 }, 805 { 1, 1 }, 806 ), 807 }, { 808 .chip_ids = ADRENO_CHIP_IDS(0x06050002), 809 .family = ADRENO_6XX_GEN3, 810 .revn = 650, 811 .fw = { 812 [ADRENO_FW_SQE] = "a650_sqe.fw", 813 [ADRENO_FW_GMU] = "a650_gmu.bin", 814 }, 815 .gmem = SZ_1M + SZ_128K, 816 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 817 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 818 ADRENO_QUIRK_HAS_HW_APRIV, 819 .init = a6xx_gpu_init, 820 .zapfw = "a650_zap.mdt", 821 .a6xx = &(const struct a6xx_info) { 822 .hwcg = a650_hwcg, 823 .protect = &a650_protect, 824 }, 825 .address_space_size = SZ_16G, 826 .speedbins = ADRENO_SPEEDBINS( 827 { 0, 0 }, 828 { 1, 1 }, 829 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ 830 { 3, 2 }, 831 ), 832 }, { 833 .chip_ids = ADRENO_CHIP_IDS(0x06060001), 834 .family = ADRENO_6XX_GEN4, 835 .revn = 660, 836 .fw = { 837 [ADRENO_FW_SQE] = "a660_sqe.fw", 838 [ADRENO_FW_GMU] = "a660_gmu.bin", 839 }, 840 .gmem = SZ_1M + SZ_512K, 841 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 842 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 843 ADRENO_QUIRK_HAS_HW_APRIV, 844 .init = a6xx_gpu_init, 845 .zapfw = "a660_zap.mdt", 846 .a6xx = &(const struct a6xx_info) { 847 .hwcg = a660_hwcg, 848 .protect = &a660_protect, 849 }, 850 .address_space_size = SZ_16G, 851 }, { 852 .chip_ids = ADRENO_CHIP_IDS(0x06030500), 853 .family = ADRENO_6XX_GEN4, 854 .fw = { 855 [ADRENO_FW_SQE] = "a660_sqe.fw", 856 [ADRENO_FW_GMU] = "a660_gmu.bin", 857 }, 858 .gmem = SZ_512K, 859 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 860 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 861 ADRENO_QUIRK_HAS_HW_APRIV, 862 .init = a6xx_gpu_init, 863 .zapfw = "a660_zap.mbn", 864 .a6xx = &(const struct a6xx_info) { 865 .hwcg = a660_hwcg, 866 .protect = &a660_protect, 867 }, 868 .address_space_size = SZ_16G, 869 .speedbins = ADRENO_SPEEDBINS( 870 { 0, 0 }, 871 { 117, 0 }, 872 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */ 873 { 190, 1 }, 874 ), 875 }, { 876 .chip_ids = ADRENO_CHIP_IDS(0x06080001), 877 .family = ADRENO_6XX_GEN2, 878 .revn = 680, 879 .fw = { 880 [ADRENO_FW_SQE] = "a630_sqe.fw", 881 [ADRENO_FW_GMU] = "a640_gmu.bin", 882 }, 883 .gmem = SZ_2M, 884 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 885 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, 886 .init = a6xx_gpu_init, 887 .zapfw = "a640_zap.mdt", 888 .a6xx = &(const struct a6xx_info) { 889 .hwcg = a640_hwcg, 890 .protect = &a630_protect, 891 }, 892 }, { 893 .chip_ids = ADRENO_CHIP_IDS(0x06090000), 894 .family = ADRENO_6XX_GEN4, 895 .fw = { 896 [ADRENO_FW_SQE] = "a660_sqe.fw", 897 [ADRENO_FW_GMU] = "a660_gmu.bin", 898 }, 899 .gmem = SZ_4M, 900 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 901 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 902 ADRENO_QUIRK_HAS_HW_APRIV, 903 .init = a6xx_gpu_init, 904 .zapfw = "a690_zap.mdt", 905 .a6xx = &(const struct a6xx_info) { 906 .hwcg = a690_hwcg, 907 .protect = &a690_protect, 908 }, 909 .address_space_size = SZ_16G, 910 } 911 }; 912 DECLARE_ADRENO_GPULIST(a6xx); 913 914 MODULE_FIRMWARE("qcom/a615_zap.mbn"); 915 MODULE_FIRMWARE("qcom/a619_gmu.bin"); 916 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 917 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 918 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 919 MODULE_FIRMWARE("qcom/a640_gmu.bin"); 920 MODULE_FIRMWARE("qcom/a650_gmu.bin"); 921 MODULE_FIRMWARE("qcom/a650_sqe.fw"); 922 MODULE_FIRMWARE("qcom/a660_gmu.bin"); 923 MODULE_FIRMWARE("qcom/a660_sqe.fw"); 924 925 static const struct adreno_reglist a702_hwcg[] = { 926 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, 927 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, 928 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, 929 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, 930 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, 931 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, 932 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, 933 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, 934 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, 935 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, 936 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, 937 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, 938 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, 939 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, 940 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, 941 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, 942 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, 943 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, 944 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, 945 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, 946 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, 947 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, 948 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, 949 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, 950 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, 951 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, 952 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, 953 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, 954 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, 955 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, 956 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, 957 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, 958 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, 959 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, 960 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, 961 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, 962 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, 963 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, 964 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, 965 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, 966 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, 967 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, 968 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, 969 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, 970 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, 971 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, 972 { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, 973 { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, 974 { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, 975 { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, 976 { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, 977 { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, 978 { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, 979 { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, 980 { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, 981 {} 982 }; 983 984 static const struct adreno_reglist a730_hwcg[] = { 985 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, 986 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, 987 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, 988 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, 989 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, 990 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, 991 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, 992 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, 993 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, 994 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, 995 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, 996 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, 997 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, 998 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, 999 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, 1000 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, 1001 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, 1002 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, 1003 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, 1004 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, 1005 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, 1006 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, 1007 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, 1008 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, 1009 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, 1010 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, 1011 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, 1012 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, 1013 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, 1014 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, 1015 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, 1016 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, 1017 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, 1018 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, 1019 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, 1020 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, 1021 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, 1022 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, 1023 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, 1024 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, 1025 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, 1026 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, 1027 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, 1028 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, 1029 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, 1030 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 }, 1031 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, 1032 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, 1033 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, 1034 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, 1035 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, 1036 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, 1037 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, 1038 {}, 1039 }; 1040 1041 static const struct adreno_reglist a740_hwcg[] = { 1042 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, 1043 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 }, 1044 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf }, 1045 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 }, 1046 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 }, 1047 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, 1048 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, 1049 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 }, 1050 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, 1051 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, 1052 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, 1053 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, 1054 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, 1055 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, 1056 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, 1057 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, 1058 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, 1059 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 }, 1060 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 }, 1061 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 }, 1062 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, 1063 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 }, 1064 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, 1065 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 }, 1066 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 }, 1067 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 }, 1068 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, 1069 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 }, 1070 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, 1071 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 }, 1072 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 }, 1073 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 }, 1074 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 }, 1075 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 }, 1076 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 }, 1077 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, 1078 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, 1079 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, 1080 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 }, 1081 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, 1082 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 }, 1083 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, 1084 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, 1085 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, 1086 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 }, 1087 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 }, 1088 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 }, 1089 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 }, 1090 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, 1091 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, 1092 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, 1093 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, 1094 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, 1095 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, 1096 {}, 1097 }; 1098 1099 static const u32 a730_protect_regs[] = { 1100 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 1101 A6XX_PROTECT_RDONLY(0x0050b, 0x0058), 1102 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 1103 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 1104 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 1105 A6XX_PROTECT_RDONLY(0x005fb, 0x009d), 1106 A6XX_PROTECT_NORDWR(0x00699, 0x01e9), 1107 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 1108 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 1109 /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */ 1110 A6XX_PROTECT_NORDWR(0x008de, 0x0001), 1111 A6XX_PROTECT_RDONLY(0x008e7, 0x014b), 1112 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 1113 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2), 1114 A6XX_PROTECT_NORDWR(0x00a41, 0x01be), 1115 A6XX_PROTECT_NORDWR(0x00df0, 0x0001), 1116 A6XX_PROTECT_NORDWR(0x00e01, 0x0000), 1117 A6XX_PROTECT_NORDWR(0x00e07, 0x0008), 1118 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 1119 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 1120 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 1121 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 1122 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 1123 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 1124 A6XX_PROTECT_NORDWR(0x08e80, 0x0280), 1125 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 1126 A6XX_PROTECT_NORDWR(0x09e40, 0x0000), 1127 A6XX_PROTECT_NORDWR(0x09e64, 0x000d), 1128 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 1129 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 1130 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 1131 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f), 1132 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003), 1133 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003), 1134 A6XX_PROTECT_NORDWR(0x0b604, 0x0003), 1135 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff), 1136 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 1137 A6XX_PROTECT_NORDWR(0x18400, 0x0053), 1138 A6XX_PROTECT_RDONLY(0x18454, 0x0004), 1139 A6XX_PROTECT_NORDWR(0x18459, 0x1fff), 1140 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff), 1141 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff), 1142 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 1143 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 1144 A6XX_PROTECT_NORDWR(0x1f860, 0x0000), 1145 A6XX_PROTECT_NORDWR(0x1f878, 0x002a), 1146 /* CP_PROTECT_REG[45, 46] are left untouched! */ 1147 0, 1148 0, 1149 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000), 1150 }; 1151 DECLARE_ADRENO_PROTECT(a730_protect, 48); 1152 1153 static const struct adreno_info a7xx_gpus[] = { 1154 { 1155 .chip_ids = ADRENO_CHIP_IDS(0x07000200), 1156 .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ 1157 .fw = { 1158 [ADRENO_FW_SQE] = "a702_sqe.fw", 1159 }, 1160 .gmem = SZ_128K, 1161 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1162 .quirks = ADRENO_QUIRK_HAS_HW_APRIV, 1163 .init = a6xx_gpu_init, 1164 .zapfw = "a702_zap.mbn", 1165 .a6xx = &(const struct a6xx_info) { 1166 .hwcg = a702_hwcg, 1167 .protect = &a650_protect, 1168 }, 1169 .speedbins = ADRENO_SPEEDBINS( 1170 { 0, 0 }, 1171 { 236, 1 }, 1172 { 178, 2 }, 1173 { 142, 3 }, 1174 ), 1175 }, { 1176 .chip_ids = ADRENO_CHIP_IDS(0x07030001), 1177 .family = ADRENO_7XX_GEN1, 1178 .fw = { 1179 [ADRENO_FW_SQE] = "a730_sqe.fw", 1180 [ADRENO_FW_GMU] = "gmu_gen70000.bin", 1181 }, 1182 .gmem = SZ_2M, 1183 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1184 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1185 ADRENO_QUIRK_HAS_HW_APRIV, 1186 .init = a6xx_gpu_init, 1187 .zapfw = "a730_zap.mdt", 1188 .a6xx = &(const struct a6xx_info) { 1189 .hwcg = a730_hwcg, 1190 .protect = &a730_protect, 1191 }, 1192 .address_space_size = SZ_16G, 1193 }, { 1194 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ 1195 .family = ADRENO_7XX_GEN2, 1196 .fw = { 1197 [ADRENO_FW_SQE] = "a740_sqe.fw", 1198 [ADRENO_FW_GMU] = "gmu_gen70200.bin", 1199 }, 1200 .gmem = 3 * SZ_1M, 1201 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1202 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1203 ADRENO_QUIRK_HAS_HW_APRIV, 1204 .init = a6xx_gpu_init, 1205 .zapfw = "a740_zap.mdt", 1206 .a6xx = &(const struct a6xx_info) { 1207 .hwcg = a740_hwcg, 1208 .protect = &a730_protect, 1209 .gmu_chipid = 0x7020100, 1210 }, 1211 .address_space_size = SZ_16G, 1212 }, { 1213 .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ 1214 .family = ADRENO_7XX_GEN2, 1215 .fw = { 1216 [ADRENO_FW_SQE] = "gen70500_sqe.fw", 1217 [ADRENO_FW_GMU] = "gen70500_gmu.bin", 1218 }, 1219 .gmem = 3 * SZ_1M, 1220 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1221 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1222 ADRENO_QUIRK_HAS_HW_APRIV, 1223 .init = a6xx_gpu_init, 1224 .a6xx = &(const struct a6xx_info) { 1225 .hwcg = a740_hwcg, 1226 .protect = &a730_protect, 1227 .gmu_chipid = 0x7050001, 1228 }, 1229 .address_space_size = SZ_256G, 1230 }, { 1231 .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ 1232 .family = ADRENO_7XX_GEN3, 1233 .fw = { 1234 [ADRENO_FW_SQE] = "gen70900_sqe.fw", 1235 [ADRENO_FW_GMU] = "gmu_gen70900.bin", 1236 }, 1237 .gmem = 3 * SZ_1M, 1238 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1239 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1240 ADRENO_QUIRK_HAS_HW_APRIV, 1241 .init = a6xx_gpu_init, 1242 .zapfw = "gen70900_zap.mbn", 1243 .a6xx = &(const struct a6xx_info) { 1244 .protect = &a730_protect, 1245 .gmu_chipid = 0x7090100, 1246 }, 1247 .address_space_size = SZ_16G, 1248 } 1249 }; 1250 DECLARE_ADRENO_GPULIST(a7xx); 1251 1252 static inline __always_unused void __build_asserts(void) 1253 { 1254 BUILD_BUG_ON(a630_protect.count > a630_protect.count_max); 1255 BUILD_BUG_ON(a650_protect.count > a650_protect.count_max); 1256 BUILD_BUG_ON(a660_protect.count > a660_protect.count_max); 1257 BUILD_BUG_ON(a690_protect.count > a690_protect.count_max); 1258 BUILD_BUG_ON(a730_protect.count > a730_protect.count_max); 1259 } 1260