1# SPDX-License-Identifier: GPL-2.0 2ccflags-y := -I $(src) 3ccflags-y += -I $(obj)/generated 4ccflags-y += -I $(src)/disp/dpu1 5ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(src)/dsi 6ccflags-$(CONFIG_DRM_MSM_DP) += -I $(src)/dp 7 8adreno-y := \ 9 adreno/adreno_device.o \ 10 adreno/adreno_gpu.o \ 11 adreno/a2xx_gpu.o \ 12 adreno/a2xx_gpummu.o \ 13 adreno/a3xx_gpu.o \ 14 adreno/a4xx_gpu.o \ 15 adreno/a5xx_gpu.o \ 16 adreno/a5xx_power.o \ 17 adreno/a5xx_preempt.o \ 18 adreno/a6xx_gpu.o \ 19 adreno/a6xx_gmu.o \ 20 adreno/a6xx_hfi.o \ 21 22adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \ 23 24adreno-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o 25 26msm-display-$(CONFIG_DRM_MSM_HDMI) += \ 27 hdmi/hdmi.o \ 28 hdmi/hdmi_audio.o \ 29 hdmi/hdmi_bridge.o \ 30 hdmi/hdmi_hpd.o \ 31 hdmi/hdmi_i2c.o \ 32 hdmi/hdmi_phy.o \ 33 hdmi/hdmi_phy_8960.o \ 34 hdmi/hdmi_phy_8996.o \ 35 hdmi/hdmi_phy_8x60.o \ 36 hdmi/hdmi_phy_8x74.o \ 37 hdmi/hdmi_pll_8960.o \ 38 39msm-display-$(CONFIG_DRM_MSM_MDP4) += \ 40 disp/mdp4/mdp4_crtc.o \ 41 disp/mdp4/mdp4_dsi_encoder.o \ 42 disp/mdp4/mdp4_dtv_encoder.o \ 43 disp/mdp4/mdp4_lcdc_encoder.o \ 44 disp/mdp4/mdp4_lvds_connector.o \ 45 disp/mdp4/mdp4_lvds_pll.o \ 46 disp/mdp4/mdp4_irq.o \ 47 disp/mdp4/mdp4_kms.o \ 48 disp/mdp4/mdp4_plane.o \ 49 50msm-display-$(CONFIG_DRM_MSM_MDP5) += \ 51 disp/mdp5/mdp5_cfg.o \ 52 disp/mdp5/mdp5_cmd_encoder.o \ 53 disp/mdp5/mdp5_ctl.o \ 54 disp/mdp5/mdp5_crtc.o \ 55 disp/mdp5/mdp5_encoder.o \ 56 disp/mdp5/mdp5_irq.o \ 57 disp/mdp5/mdp5_kms.o \ 58 disp/mdp5/mdp5_pipe.o \ 59 disp/mdp5/mdp5_mixer.o \ 60 disp/mdp5/mdp5_plane.o \ 61 disp/mdp5/mdp5_smp.o \ 62 63msm-display-$(CONFIG_DRM_MSM_DPU) += \ 64 disp/dpu1/dpu_core_perf.o \ 65 disp/dpu1/dpu_crtc.o \ 66 disp/dpu1/dpu_encoder.o \ 67 disp/dpu1/dpu_encoder_phys_cmd.o \ 68 disp/dpu1/dpu_encoder_phys_vid.o \ 69 disp/dpu1/dpu_encoder_phys_wb.o \ 70 disp/dpu1/dpu_formats.o \ 71 disp/dpu1/dpu_hw_catalog.o \ 72 disp/dpu1/dpu_hw_cdm.o \ 73 disp/dpu1/dpu_hw_ctl.o \ 74 disp/dpu1/dpu_hw_dsc.o \ 75 disp/dpu1/dpu_hw_dsc_1_2.o \ 76 disp/dpu1/dpu_hw_interrupts.o \ 77 disp/dpu1/dpu_hw_intf.o \ 78 disp/dpu1/dpu_hw_lm.o \ 79 disp/dpu1/dpu_hw_pingpong.o \ 80 disp/dpu1/dpu_hw_sspp.o \ 81 disp/dpu1/dpu_hw_dspp.o \ 82 disp/dpu1/dpu_hw_merge3d.o \ 83 disp/dpu1/dpu_hw_top.o \ 84 disp/dpu1/dpu_hw_util.o \ 85 disp/dpu1/dpu_hw_vbif.o \ 86 disp/dpu1/dpu_hw_wb.o \ 87 disp/dpu1/dpu_kms.o \ 88 disp/dpu1/dpu_plane.o \ 89 disp/dpu1/dpu_rm.o \ 90 disp/dpu1/dpu_vbif.o \ 91 disp/dpu1/dpu_writeback.o 92 93msm-display-$(CONFIG_DRM_MSM_MDSS) += \ 94 msm_mdss.o \ 95 96msm-display-y += \ 97 disp/mdp_format.o \ 98 disp/mdp_kms.o \ 99 disp/msm_disp_snapshot.o \ 100 disp/msm_disp_snapshot_util.o \ 101 102msm-y += \ 103 msm_atomic.o \ 104 msm_atomic_tracepoints.o \ 105 msm_debugfs.o \ 106 msm_drv.o \ 107 msm_fb.o \ 108 msm_fence.o \ 109 msm_gem.o \ 110 msm_gem_prime.o \ 111 msm_gem_shrinker.o \ 112 msm_gem_submit.o \ 113 msm_gem_vma.o \ 114 msm_gpu.o \ 115 msm_gpu_devfreq.o \ 116 msm_io_utils.o \ 117 msm_iommu.o \ 118 msm_kms.o \ 119 msm_perf.o \ 120 msm_rd.o \ 121 msm_ringbuffer.o \ 122 msm_submitqueue.o \ 123 msm_gpu_tracepoints.o \ 124 125msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o 126 127msm-display-$(CONFIG_DEBUG_FS) += \ 128 dp/dp_debug.o 129 130msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ 131 dp/dp_catalog.o \ 132 dp/dp_ctrl.o \ 133 dp/dp_display.o \ 134 dp/dp_drm.o \ 135 dp/dp_link.o \ 136 dp/dp_panel.o \ 137 dp/dp_audio.o \ 138 dp/dp_utils.o 139 140msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o 141 142msm-display-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ 143 dsi/dsi_cfg.o \ 144 dsi/dsi_host.o \ 145 dsi/dsi_manager.o \ 146 dsi/phy/dsi_phy.o 147 148msm-display-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o 149msm-display-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o 150msm-display-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o 151msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o 152msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o 153msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o 154 155msm-y += $(adreno-y) $(msm-display-y) 156 157obj-$(CONFIG_DRM_MSM) += msm.o 158 159ifeq (y,$(CONFIG_DRM_MSM_VALIDATE_XML)) 160 headergen-opts += --validate 161else 162 headergen-opts += --no-validate 163endif 164 165quiet_cmd_headergen = GENHDR $@ 166 cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \ 167 $(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@ 168 169$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \ 170 $(src)/registers/adreno/adreno_common.xml \ 171 $(src)/registers/adreno/adreno_pm4.xml \ 172 $(src)/registers/freedreno_copyright.xml \ 173 $(src)/registers/gen_header.py \ 174 $(src)/registers/rules-fd.xsd \ 175 FORCE 176 $(call if_changed,headergen) 177 178$(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \ 179 $(src)/registers/freedreno_copyright.xml \ 180 $(src)/registers/gen_header.py \ 181 $(src)/registers/rules-fd.xsd \ 182 FORCE 183 $(call if_changed,headergen) 184 185ADRENO_HEADERS = \ 186 generated/a2xx.xml.h \ 187 generated/a3xx.xml.h \ 188 generated/a4xx.xml.h \ 189 generated/a5xx.xml.h \ 190 generated/a6xx.xml.h \ 191 generated/a6xx_gmu.xml.h \ 192 generated/adreno_common.xml.h \ 193 generated/adreno_pm4.xml.h \ 194 195DISPLAY_HEADERS = \ 196 generated/dsi_phy_7nm.xml.h \ 197 generated/dsi_phy_10nm.xml.h \ 198 generated/dsi_phy_14nm.xml.h \ 199 generated/dsi_phy_20nm.xml.h \ 200 generated/dsi_phy_28nm_8960.xml.h \ 201 generated/dsi_phy_28nm.xml.h \ 202 generated/dsi.xml.h \ 203 generated/hdmi.xml.h \ 204 generated/mdp4.xml.h \ 205 generated/mdp5.xml.h \ 206 generated/mdp_common.xml.h \ 207 generated/sfpb.xml.h 208 209$(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS)) 210$(addprefix $(obj)/,$(msm-display-y)): $(addprefix $(obj)/,$(DISPLAY_HEADERS)) 211 212targets += $(ADRENO_HEADERS) $(DISPLAY_HEADERS) 213