1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_edid.h> 18 #include <drm/drm_format_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_framebuffer.h> 21 #include <drm/drm_gem_atomic_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_panic.h> 24 #include <drm/drm_print.h> 25 26 #include "mgag200_ddc.h" 27 #include "mgag200_drv.h" 28 29 /* 30 * This file contains setup code for the CRTC. 31 */ 32 33 void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, 34 const struct drm_format_info *format) 35 { 36 int i; 37 38 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 39 40 switch (format->format) { 41 case DRM_FORMAT_RGB565: 42 /* Use better interpolation, to take 32 values from 0 to 255 */ 43 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 44 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 45 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 46 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 47 } 48 /* Green has one more bit, so add padding with 0 for red and blue. */ 49 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 50 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 51 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 52 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 53 } 54 break; 55 case DRM_FORMAT_RGB888: 56 case DRM_FORMAT_XRGB8888: 57 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 58 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 59 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 60 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 61 } 62 break; 63 default: 64 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 65 &format->format); 66 break; 67 } 68 } 69 70 void mgag200_crtc_set_gamma(struct mga_device *mdev, 71 const struct drm_format_info *format, 72 struct drm_color_lut *lut) 73 { 74 int i; 75 76 WREG8(DAC_INDEX + MGA1064_INDEX, 0); 77 78 switch (format->format) { 79 case DRM_FORMAT_RGB565: 80 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 81 for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 82 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); 83 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 84 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8); 85 } 86 /* Green has one more bit, so add padding with 0 for red and blue. */ 87 for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 88 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 89 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 90 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 91 } 92 break; 93 case DRM_FORMAT_RGB888: 94 case DRM_FORMAT_XRGB8888: 95 for (i = 0; i < MGAG200_LUT_SIZE; i++) { 96 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8); 97 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8); 98 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8); 99 } 100 break; 101 default: 102 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 103 &format->format); 104 break; 105 } 106 } 107 108 static inline void mga_wait_vsync(struct mga_device *mdev) 109 { 110 unsigned long timeout = jiffies + HZ/10; 111 unsigned int status = 0; 112 113 do { 114 status = RREG32(MGAREG_STATUS); 115 } while ((status & 0x08) && time_before(jiffies, timeout)); 116 timeout = jiffies + HZ/10; 117 status = 0; 118 do { 119 status = RREG32(MGAREG_STATUS); 120 } while (!(status & 0x08) && time_before(jiffies, timeout)); 121 } 122 123 static inline void mga_wait_busy(struct mga_device *mdev) 124 { 125 unsigned long timeout = jiffies + HZ; 126 unsigned int status = 0; 127 do { 128 status = RREG8(MGAREG_STATUS + 2); 129 } while ((status & 0x01) && time_before(jiffies, timeout)); 130 } 131 132 /* 133 * This is how the framebuffer base address is stored in g200 cards: 134 * * Assume @offset is the gpu_addr variable of the framebuffer object 135 * * Then addr is the number of _pixels_ (not bytes) from the start of 136 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 137 * framebuffers) 138 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 139 * addr<20> -> CRTCEXT0<6> 140 * addr<19-16> -> CRTCEXT0<3-0> 141 * addr<15-8> -> CRTCC<7-0> 142 * addr<7-0> -> CRTCD<7-0> 143 * 144 * CRTCEXT0 has to be programmed last to trigger an update and make the 145 * new addr variable take effect. 146 */ 147 static void mgag200_set_startadd(struct mga_device *mdev, 148 unsigned long offset) 149 { 150 struct drm_device *dev = &mdev->base; 151 u32 startadd; 152 u8 crtcc, crtcd, crtcext0; 153 154 startadd = offset / 8; 155 156 if (startadd > 0) 157 drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd); 158 159 /* 160 * Can't store addresses any higher than that, but we also 161 * don't have more than 16 MiB of memory, so it should be fine. 162 */ 163 drm_WARN_ON(dev, startadd > 0x1fffff); 164 165 RREG_ECRT(0x00, crtcext0); 166 167 crtcc = (startadd >> 8) & 0xff; 168 crtcd = startadd & 0xff; 169 crtcext0 &= 0xb0; 170 crtcext0 |= ((startadd >> 14) & BIT(6)) | 171 ((startadd >> 16) & 0x0f); 172 173 WREG_CRT(0x0c, crtcc); 174 WREG_CRT(0x0d, crtcd); 175 WREG_ECRT(0x00, crtcext0); 176 } 177 178 void mgag200_init_registers(struct mga_device *mdev) 179 { 180 u8 crtc11, misc; 181 182 WREG_SEQ(2, 0x0f); 183 WREG_SEQ(3, 0x00); 184 WREG_SEQ(4, 0x0e); 185 186 WREG_CRT(10, 0); 187 WREG_CRT(11, 0); 188 WREG_CRT(12, 0); 189 WREG_CRT(13, 0); 190 WREG_CRT(14, 0); 191 WREG_CRT(15, 0); 192 193 RREG_CRT(0x11, crtc11); 194 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 195 MGAREG_CRTC11_VINTEN | 196 MGAREG_CRTC11_VINTCLR); 197 WREG_CRT(0x11, crtc11); 198 199 misc = RREG8(MGA_MISC_IN); 200 misc |= MGAREG_MISC_IOADSEL; 201 WREG8(MGA_MISC_OUT, misc); 202 } 203 204 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode) 205 { 206 const struct mgag200_device_info *info = mdev->info; 207 unsigned int hdisplay, hsyncstart, hsyncend, htotal; 208 unsigned int vdisplay, vsyncstart, vsyncend, vtotal; 209 u8 misc, crtcext1, crtcext2, crtcext5; 210 211 hdisplay = mode->hdisplay / 8 - 1; 212 hsyncstart = mode->hsync_start / 8 - 1; 213 hsyncend = mode->hsync_end / 8 - 1; 214 htotal = mode->htotal / 8 - 1; 215 216 /* Work around hardware quirk */ 217 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 218 htotal++; 219 220 vdisplay = mode->vdisplay - 1; 221 vsyncstart = mode->vsync_start - 1; 222 vsyncend = mode->vsync_end - 1; 223 vtotal = mode->vtotal - 2; 224 225 misc = RREG8(MGA_MISC_IN); 226 227 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 228 misc |= MGAREG_MISC_HSYNCPOL; 229 else 230 misc &= ~MGAREG_MISC_HSYNCPOL; 231 232 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 233 misc |= MGAREG_MISC_VSYNCPOL; 234 else 235 misc &= ~MGAREG_MISC_VSYNCPOL; 236 237 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 238 ((hdisplay & 0x100) >> 7) | 239 ((hsyncstart & 0x100) >> 6) | 240 (htotal & 0x40); 241 if (info->has_vidrst) 242 crtcext1 |= MGAREG_CRTCEXT1_VRSTEN | 243 MGAREG_CRTCEXT1_HRSTEN; 244 245 crtcext2 = ((vtotal & 0xc00) >> 10) | 246 ((vdisplay & 0x400) >> 8) | 247 ((vdisplay & 0xc00) >> 7) | 248 ((vsyncstart & 0xc00) >> 5) | 249 ((vdisplay & 0x400) >> 3); 250 crtcext5 = 0x00; 251 252 WREG_CRT(0, htotal - 4); 253 WREG_CRT(1, hdisplay); 254 WREG_CRT(2, hdisplay); 255 WREG_CRT(3, (htotal & 0x1F) | 0x80); 256 WREG_CRT(4, hsyncstart); 257 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 258 WREG_CRT(6, vtotal & 0xFF); 259 WREG_CRT(7, ((vtotal & 0x100) >> 8) | 260 ((vdisplay & 0x100) >> 7) | 261 ((vsyncstart & 0x100) >> 6) | 262 ((vdisplay & 0x100) >> 5) | 263 ((vdisplay & 0x100) >> 4) | /* linecomp */ 264 ((vtotal & 0x200) >> 4) | 265 ((vdisplay & 0x200) >> 3) | 266 ((vsyncstart & 0x200) >> 2)); 267 WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 268 ((vdisplay & 0x200) >> 3)); 269 WREG_CRT(16, vsyncstart & 0xFF); 270 WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 271 WREG_CRT(18, vdisplay & 0xFF); 272 WREG_CRT(20, 0); 273 WREG_CRT(21, vdisplay & 0xFF); 274 WREG_CRT(22, (vtotal + 1) & 0xFF); 275 WREG_CRT(23, 0xc3); 276 WREG_CRT(24, vdisplay & 0xFF); 277 278 WREG_ECRT(0x01, crtcext1); 279 WREG_ECRT(0x02, crtcext2); 280 WREG_ECRT(0x05, crtcext5); 281 282 WREG8(MGA_MISC_OUT, misc); 283 } 284 285 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 286 { 287 static const u8 bpp_shift[] = {0, 1, 0, 2}; 288 289 return bpp_shift[format->cpp[0] - 1]; 290 } 291 292 /* 293 * Calculates the HW offset value from the framebuffer's pitch. The 294 * offset is a multiple of the pixel size and depends on the display 295 * format. 296 */ 297 static u32 mgag200_calculate_offset(struct mga_device *mdev, 298 const struct drm_framebuffer *fb) 299 { 300 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 301 u8 bppshift = mgag200_get_bpp_shift(fb->format); 302 303 if (fb->format->cpp[0] * 8 == 24) 304 offset = (offset * 3) >> (4 - bppshift); 305 else 306 offset = offset >> (4 - bppshift); 307 308 return offset; 309 } 310 311 static void mgag200_set_offset(struct mga_device *mdev, 312 const struct drm_framebuffer *fb) 313 { 314 u8 crtc13, crtcext0; 315 u32 offset = mgag200_calculate_offset(mdev, fb); 316 317 RREG_ECRT(0, crtcext0); 318 319 crtc13 = offset & 0xff; 320 321 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 322 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 323 324 WREG_CRT(0x13, crtc13); 325 WREG_ECRT(0x00, crtcext0); 326 } 327 328 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format) 329 { 330 struct drm_device *dev = &mdev->base; 331 unsigned int bpp, bppshift, scale; 332 u8 crtcext3, xmulctrl; 333 334 bpp = format->cpp[0] * 8; 335 336 bppshift = mgag200_get_bpp_shift(format); 337 switch (bpp) { 338 case 24: 339 scale = ((1 << bppshift) * 3) - 1; 340 break; 341 default: 342 scale = (1 << bppshift) - 1; 343 break; 344 } 345 346 RREG_ECRT(3, crtcext3); 347 348 switch (bpp) { 349 case 8: 350 xmulctrl = MGA1064_MUL_CTL_8bits; 351 break; 352 case 16: 353 if (format->depth == 15) 354 xmulctrl = MGA1064_MUL_CTL_15bits; 355 else 356 xmulctrl = MGA1064_MUL_CTL_16bits; 357 break; 358 case 24: 359 xmulctrl = MGA1064_MUL_CTL_24bits; 360 break; 361 case 32: 362 xmulctrl = MGA1064_MUL_CTL_32_24bits; 363 break; 364 default: 365 /* BUG: We should have caught this problem already. */ 366 drm_WARN_ON(dev, "invalid format depth\n"); 367 return; 368 } 369 370 crtcext3 &= ~GENMASK(2, 0); 371 crtcext3 |= scale; 372 373 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 374 375 WREG_GFX(0, 0x00); 376 WREG_GFX(1, 0x00); 377 WREG_GFX(2, 0x00); 378 WREG_GFX(3, 0x00); 379 WREG_GFX(4, 0x00); 380 WREG_GFX(5, 0x40); 381 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 382 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 383 */ 384 WREG_GFX(6, 0x0d); 385 WREG_GFX(7, 0x0f); 386 WREG_GFX(8, 0x0f); 387 388 WREG_ECRT(3, crtcext3); 389 } 390 391 void mgag200_enable_display(struct mga_device *mdev) 392 { 393 u8 seq0, crtcext1; 394 395 RREG_SEQ(0x00, seq0); 396 seq0 |= MGAREG_SEQ0_SYNCRST | 397 MGAREG_SEQ0_ASYNCRST; 398 WREG_SEQ(0x00, seq0); 399 400 /* 401 * TODO: replace busy waiting with vblank IRQ; put 402 * msleep(50) before changing SCROFF 403 */ 404 mga_wait_vsync(mdev); 405 mga_wait_busy(mdev); 406 407 RREG_ECRT(0x01, crtcext1); 408 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 409 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 410 WREG_ECRT(0x01, crtcext1); 411 } 412 413 static void mgag200_disable_display(struct mga_device *mdev) 414 { 415 u8 seq0, crtcext1; 416 417 RREG_SEQ(0x00, seq0); 418 seq0 &= ~MGAREG_SEQ0_SYNCRST; 419 WREG_SEQ(0x00, seq0); 420 421 /* 422 * TODO: replace busy waiting with vblank IRQ; put 423 * msleep(50) before changing SCROFF 424 */ 425 mga_wait_vsync(mdev); 426 mga_wait_busy(mdev); 427 428 RREG_ECRT(0x01, crtcext1); 429 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 430 MGAREG_CRTCEXT1_HSYNCOFF; 431 WREG_ECRT(0x01, crtcext1); 432 } 433 434 static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap, 435 struct drm_framebuffer *fb, struct drm_rect *clip) 436 { 437 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 438 439 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip)); 440 drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip); 441 } 442 443 /* 444 * Primary plane 445 */ 446 447 const uint32_t mgag200_primary_plane_formats[] = { 448 DRM_FORMAT_XRGB8888, 449 DRM_FORMAT_RGB565, 450 DRM_FORMAT_RGB888, 451 }; 452 453 const size_t mgag200_primary_plane_formats_size = ARRAY_SIZE(mgag200_primary_plane_formats); 454 455 const uint64_t mgag200_primary_plane_fmtmods[] = { 456 DRM_FORMAT_MOD_LINEAR, 457 DRM_FORMAT_MOD_INVALID 458 }; 459 460 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 461 struct drm_atomic_state *new_state) 462 { 463 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); 464 struct drm_framebuffer *new_fb = new_plane_state->fb; 465 struct drm_framebuffer *fb = NULL; 466 struct drm_crtc *new_crtc = new_plane_state->crtc; 467 struct drm_crtc_state *new_crtc_state = NULL; 468 struct mgag200_crtc_state *new_mgag200_crtc_state; 469 int ret; 470 471 if (new_crtc) 472 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_crtc); 473 474 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 475 DRM_PLANE_NO_SCALING, 476 DRM_PLANE_NO_SCALING, 477 false, true); 478 if (ret) 479 return ret; 480 else if (!new_plane_state->visible) 481 return 0; 482 483 if (plane->state) 484 fb = plane->state->fb; 485 486 if (!fb || (fb->format != new_fb->format)) 487 new_crtc_state->mode_changed = true; /* update PLL settings */ 488 489 new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state); 490 new_mgag200_crtc_state->format = new_fb->format; 491 492 return 0; 493 } 494 495 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 496 struct drm_atomic_state *old_state) 497 { 498 struct drm_device *dev = plane->dev; 499 struct mga_device *mdev = to_mga_device(dev); 500 struct drm_plane_state *plane_state = plane->state; 501 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane); 502 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 503 struct drm_framebuffer *fb = plane_state->fb; 504 struct drm_atomic_helper_damage_iter iter; 505 struct drm_rect damage; 506 507 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 508 drm_atomic_for_each_plane_damage(&iter, &damage) { 509 mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage); 510 } 511 512 /* Always scanout image at VRAM offset 0 */ 513 mgag200_set_startadd(mdev, (u32)0); 514 mgag200_set_offset(mdev, fb); 515 } 516 517 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, 518 struct drm_atomic_state *state) 519 { 520 struct drm_device *dev = plane->dev; 521 struct mga_device *mdev = to_mga_device(dev); 522 u8 seq1; 523 524 RREG_SEQ(0x01, seq1); 525 seq1 &= ~MGAREG_SEQ1_SCROFF; 526 WREG_SEQ(0x01, seq1); 527 msleep(20); 528 } 529 530 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 531 struct drm_atomic_state *old_state) 532 { 533 struct drm_device *dev = plane->dev; 534 struct mga_device *mdev = to_mga_device(dev); 535 u8 seq1; 536 537 RREG_SEQ(0x01, seq1); 538 seq1 |= MGAREG_SEQ1_SCROFF; 539 WREG_SEQ(0x01, seq1); 540 msleep(20); 541 } 542 543 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 544 struct drm_scanout_buffer *sb) 545 { 546 struct mga_device *mdev = to_mga_device(plane->dev); 547 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 548 549 if (plane->state && plane->state->fb) { 550 sb->format = plane->state->fb->format; 551 sb->width = plane->state->fb->width; 552 sb->height = plane->state->fb->height; 553 sb->pitch[0] = plane->state->fb->pitches[0]; 554 sb->map[0] = map; 555 return 0; 556 } 557 return -ENODEV; 558 } 559 560 /* 561 * CRTC 562 */ 563 564 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 565 const struct drm_display_mode *mode) 566 { 567 struct mga_device *mdev = to_mga_device(crtc->dev); 568 const struct mgag200_device_info *info = mdev->info; 569 570 /* 571 * Some devices have additional limits on the size of the 572 * display mode. 573 */ 574 if (mode->hdisplay > info->max_hdisplay) 575 return MODE_VIRTUAL_X; 576 if (mode->vdisplay > info->max_vdisplay) 577 return MODE_VIRTUAL_Y; 578 579 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 580 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 581 return MODE_H_ILLEGAL; 582 } 583 584 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 585 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 586 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 587 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 588 return MODE_BAD; 589 } 590 591 return MODE_OK; 592 } 593 594 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state) 595 { 596 struct drm_device *dev = crtc->dev; 597 struct mga_device *mdev = to_mga_device(dev); 598 const struct mgag200_device_funcs *funcs = mdev->funcs; 599 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 600 struct drm_property_blob *new_gamma_lut = new_crtc_state->gamma_lut; 601 int ret; 602 603 if (!new_crtc_state->enable) 604 return 0; 605 606 ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state); 607 if (ret) 608 return ret; 609 610 if (new_crtc_state->mode_changed) { 611 if (funcs->pixpllc_atomic_check) { 612 ret = funcs->pixpllc_atomic_check(crtc, new_state); 613 if (ret) 614 return ret; 615 } 616 } 617 618 if (new_crtc_state->color_mgmt_changed && new_gamma_lut) { 619 if (new_gamma_lut->length != MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 620 drm_dbg(dev, "Wrong size for gamma_lut %zu\n", new_gamma_lut->length); 621 return -EINVAL; 622 } 623 } 624 625 return 0; 626 } 627 628 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 629 { 630 struct drm_crtc_state *crtc_state = crtc->state; 631 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 632 struct drm_device *dev = crtc->dev; 633 struct mga_device *mdev = to_mga_device(dev); 634 635 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 636 const struct drm_format_info *format = mgag200_crtc_state->format; 637 638 if (crtc_state->gamma_lut) 639 mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data); 640 else 641 mgag200_crtc_set_gamma_linear(mdev, format); 642 } 643 } 644 645 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 646 { 647 struct drm_device *dev = crtc->dev; 648 struct mga_device *mdev = to_mga_device(dev); 649 const struct mgag200_device_funcs *funcs = mdev->funcs; 650 struct drm_crtc_state *crtc_state = crtc->state; 651 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 652 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 653 const struct drm_format_info *format = mgag200_crtc_state->format; 654 655 if (funcs->disable_vidrst) 656 funcs->disable_vidrst(mdev); 657 658 mgag200_set_format_regs(mdev, format); 659 mgag200_set_mode_regs(mdev, adjusted_mode); 660 661 if (funcs->pixpllc_atomic_update) 662 funcs->pixpllc_atomic_update(crtc, old_state); 663 664 if (crtc_state->gamma_lut) 665 mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data); 666 else 667 mgag200_crtc_set_gamma_linear(mdev, format); 668 669 mgag200_enable_display(mdev); 670 671 if (funcs->enable_vidrst) 672 funcs->enable_vidrst(mdev); 673 } 674 675 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 676 { 677 struct mga_device *mdev = to_mga_device(crtc->dev); 678 const struct mgag200_device_funcs *funcs = mdev->funcs; 679 680 if (funcs->disable_vidrst) 681 funcs->disable_vidrst(mdev); 682 683 mgag200_disable_display(mdev); 684 685 if (funcs->enable_vidrst) 686 funcs->enable_vidrst(mdev); 687 } 688 689 void mgag200_crtc_reset(struct drm_crtc *crtc) 690 { 691 struct mgag200_crtc_state *mgag200_crtc_state; 692 693 if (crtc->state) 694 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 695 696 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 697 if (mgag200_crtc_state) 698 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 699 else 700 __drm_atomic_helper_crtc_reset(crtc, NULL); 701 } 702 703 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 704 { 705 struct drm_crtc_state *crtc_state = crtc->state; 706 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 707 struct mgag200_crtc_state *new_mgag200_crtc_state; 708 709 if (!crtc_state) 710 return NULL; 711 712 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 713 if (!new_mgag200_crtc_state) 714 return NULL; 715 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 716 717 new_mgag200_crtc_state->format = mgag200_crtc_state->format; 718 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 719 sizeof(new_mgag200_crtc_state->pixpllc)); 720 721 return &new_mgag200_crtc_state->base; 722 } 723 724 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 725 { 726 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 727 728 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 729 kfree(mgag200_crtc_state); 730 } 731 732 /* 733 * Mode config 734 */ 735 736 static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state) 737 { 738 struct mga_device *mdev = to_mga_device(state->dev); 739 740 /* 741 * Concurrent operations could possibly trigger a call to 742 * drm_connector_helper_funcs.get_modes by trying to read the 743 * display modes. Protect access to I/O registers by acquiring 744 * the I/O-register lock. 745 */ 746 mutex_lock(&mdev->rmmio_lock); 747 drm_atomic_helper_commit_tail(state); 748 mutex_unlock(&mdev->rmmio_lock); 749 } 750 751 static const struct drm_mode_config_helper_funcs mgag200_mode_config_helper_funcs = { 752 .atomic_commit_tail = mgag200_mode_config_helper_atomic_commit_tail, 753 }; 754 755 /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 756 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 757 unsigned int bits_per_pixel) 758 { 759 uint32_t total_area, divisor; 760 uint64_t active_area, pixels_per_second, bandwidth; 761 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 762 763 divisor = 1024; 764 765 if (!mode->htotal || !mode->vtotal || !mode->clock) 766 return 0; 767 768 active_area = mode->hdisplay * mode->vdisplay; 769 total_area = mode->htotal * mode->vtotal; 770 771 pixels_per_second = active_area * mode->clock * 1000; 772 do_div(pixels_per_second, total_area); 773 774 bandwidth = pixels_per_second * bytes_per_pixel * 100; 775 do_div(bandwidth, divisor); 776 777 return (uint32_t)bandwidth; 778 } 779 780 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 781 const struct drm_display_mode *mode) 782 { 783 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 784 struct mga_device *mdev = to_mga_device(dev); 785 unsigned long fbsize, fbpages, max_fbpages; 786 const struct mgag200_device_info *info = mdev->info; 787 788 max_fbpages = mdev->vram_available >> PAGE_SHIFT; 789 790 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 791 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 792 793 if (fbpages > max_fbpages) 794 return MODE_MEM; 795 796 /* 797 * Test the mode's required memory bandwidth if the device 798 * specifies a maximum. Not all devices do though. 799 */ 800 if (info->max_mem_bandwidth) { 801 uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8); 802 803 if (mode_bandwidth > (info->max_mem_bandwidth * 1024)) 804 return MODE_BAD; 805 } 806 807 return MODE_OK; 808 } 809 810 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 811 .fb_create = drm_gem_fb_create_with_dirty, 812 .mode_valid = mgag200_mode_config_mode_valid, 813 .atomic_check = drm_atomic_helper_check, 814 .atomic_commit = drm_atomic_helper_commit, 815 }; 816 817 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available) 818 { 819 struct drm_device *dev = &mdev->base; 820 int ret; 821 822 mdev->vram_available = vram_available; 823 824 ret = drmm_mode_config_init(dev); 825 if (ret) { 826 drm_err(dev, "drmm_mode_config_init() failed: %d\n", ret); 827 return ret; 828 } 829 830 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 831 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 832 dev->mode_config.preferred_depth = 24; 833 dev->mode_config.funcs = &mgag200_mode_config_funcs; 834 dev->mode_config.helper_private = &mgag200_mode_config_helper_funcs; 835 836 return 0; 837 } 838