1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_color_mgmt.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_format_helper.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_framebuffer.h> 22 #include <drm/drm_gem_atomic_helper.h> 23 #include <drm/drm_gem_framebuffer_helper.h> 24 #include <drm/drm_panic.h> 25 #include <drm/drm_print.h> 26 27 #include "mgag200_ddc.h" 28 #include "mgag200_drv.h" 29 30 /* 31 * This file contains setup code for the CRTC. 32 */ 33 34 static void mgag200_set_gamma_lut(struct drm_crtc *crtc, unsigned int index, 35 u16 red, u16 green, u16 blue) 36 { 37 struct drm_device *dev = crtc->dev; 38 struct mga_device *mdev = to_mga_device(dev); 39 u8 i8 = index & 0xff; 40 u8 r8 = red >> 8; 41 u8 g8 = green >> 8; 42 u8 b8 = blue >> 8; 43 44 if (drm_WARN_ON_ONCE(dev, index != i8)) 45 return; /* driver bug */ 46 47 WREG8(DAC_INDEX + MGA1064_INDEX, i8); 48 WREG8(DAC_INDEX + MGA1064_COL_PAL, r8); 49 WREG8(DAC_INDEX + MGA1064_COL_PAL, g8); 50 WREG8(DAC_INDEX + MGA1064_COL_PAL, b8); 51 } 52 53 void mgag200_crtc_fill_gamma(struct mga_device *mdev, 54 const struct drm_format_info *format) 55 { 56 struct drm_crtc *crtc = &mdev->crtc; 57 58 switch (format->format) { 59 case DRM_FORMAT_RGB565: 60 drm_crtc_fill_gamma_565(crtc, mgag200_set_gamma_lut); 61 break; 62 case DRM_FORMAT_RGB888: 63 case DRM_FORMAT_XRGB8888: 64 drm_crtc_fill_gamma_888(crtc, mgag200_set_gamma_lut); 65 break; 66 default: 67 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 68 &format->format); 69 break; 70 } 71 } 72 73 void mgag200_crtc_load_gamma(struct mga_device *mdev, 74 const struct drm_format_info *format, 75 struct drm_color_lut *lut) 76 { 77 struct drm_crtc *crtc = &mdev->crtc; 78 79 switch (format->format) { 80 case DRM_FORMAT_RGB565: 81 drm_crtc_load_gamma_565_from_888(crtc, lut, mgag200_set_gamma_lut); 82 break; 83 case DRM_FORMAT_RGB888: 84 case DRM_FORMAT_XRGB8888: 85 drm_crtc_load_gamma_888(crtc, lut, mgag200_set_gamma_lut); 86 break; 87 default: 88 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 89 &format->format); 90 break; 91 } 92 } 93 94 static inline void mga_wait_vsync(struct mga_device *mdev) 95 { 96 unsigned long timeout = jiffies + HZ/10; 97 unsigned int status = 0; 98 99 do { 100 status = RREG32(MGAREG_STATUS); 101 } while ((status & 0x08) && time_before(jiffies, timeout)); 102 timeout = jiffies + HZ/10; 103 status = 0; 104 do { 105 status = RREG32(MGAREG_STATUS); 106 } while (!(status & 0x08) && time_before(jiffies, timeout)); 107 } 108 109 static inline void mga_wait_busy(struct mga_device *mdev) 110 { 111 unsigned long timeout = jiffies + HZ; 112 unsigned int status = 0; 113 do { 114 status = RREG8(MGAREG_STATUS + 2); 115 } while ((status & 0x01) && time_before(jiffies, timeout)); 116 } 117 118 /* 119 * This is how the framebuffer base address is stored in g200 cards: 120 * * Assume @offset is the gpu_addr variable of the framebuffer object 121 * * Then addr is the number of _pixels_ (not bytes) from the start of 122 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 123 * framebuffers) 124 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 125 * addr<20> -> CRTCEXT0<6> 126 * addr<19-16> -> CRTCEXT0<3-0> 127 * addr<15-8> -> CRTCC<7-0> 128 * addr<7-0> -> CRTCD<7-0> 129 * 130 * CRTCEXT0 has to be programmed last to trigger an update and make the 131 * new addr variable take effect. 132 */ 133 static void mgag200_set_startadd(struct mga_device *mdev, 134 unsigned long offset) 135 { 136 struct drm_device *dev = &mdev->base; 137 u32 startadd; 138 u8 crtcc, crtcd, crtcext0; 139 140 startadd = offset / 8; 141 142 if (startadd > 0) 143 drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd); 144 145 /* 146 * Can't store addresses any higher than that, but we also 147 * don't have more than 16 MiB of memory, so it should be fine. 148 */ 149 drm_WARN_ON(dev, startadd > 0x1fffff); 150 151 RREG_ECRT(0x00, crtcext0); 152 153 crtcc = (startadd >> 8) & 0xff; 154 crtcd = startadd & 0xff; 155 crtcext0 &= 0xb0; 156 crtcext0 |= ((startadd >> 14) & BIT(6)) | 157 ((startadd >> 16) & 0x0f); 158 159 WREG_CRT(0x0c, crtcc); 160 WREG_CRT(0x0d, crtcd); 161 WREG_ECRT(0x00, crtcext0); 162 } 163 164 /* 165 * Set the opmode for the hardware swapper for Big-Endian processor 166 * support for the frame buffer aperture and DMAWIN space. 167 */ 168 static void mgag200_set_datasiz(struct mga_device *mdev, u32 format) 169 { 170 #if defined(__BIG_ENDIAN) 171 u32 opmode = RREG32(MGAREG_OPMODE); 172 173 opmode &= ~(GENMASK(17, 16) | GENMASK(9, 8) | GENMASK(3, 2)); 174 175 /* Big-endian byte-swapping */ 176 switch (format) { 177 case DRM_FORMAT_RGB565: 178 opmode |= 0x10100; 179 break; 180 case DRM_FORMAT_XRGB8888: 181 opmode |= 0x20200; 182 break; 183 } 184 WREG32(MGAREG_OPMODE, opmode); 185 #endif 186 } 187 188 void mgag200_init_registers(struct mga_device *mdev) 189 { 190 u8 crtc11, misc; 191 192 WREG_SEQ(2, 0x0f); 193 WREG_SEQ(3, 0x00); 194 WREG_SEQ(4, 0x0e); 195 196 WREG_CRT(10, 0); 197 WREG_CRT(11, 0); 198 WREG_CRT(12, 0); 199 WREG_CRT(13, 0); 200 WREG_CRT(14, 0); 201 WREG_CRT(15, 0); 202 203 RREG_CRT(0x11, crtc11); 204 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 205 MGAREG_CRTC11_VINTEN | 206 MGAREG_CRTC11_VINTCLR); 207 WREG_CRT(0x11, crtc11); 208 209 misc = RREG8(MGA_MISC_IN); 210 misc |= MGAREG_MISC_IOADSEL; 211 WREG8(MGA_MISC_OUT, misc); 212 } 213 214 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode, 215 bool set_vidrst) 216 { 217 unsigned int hdispend, hsyncstr, hsyncend, htotal, hblkstr, hblkend; 218 unsigned int vdispend, vsyncstr, vsyncend, vtotal, vblkstr, vblkend; 219 unsigned int linecomp; 220 u8 misc, crtcext1, crtcext2, crtcext5; 221 222 hdispend = mode->crtc_hdisplay / 8 - 1; 223 hsyncstr = mode->crtc_hsync_start / 8 - 1; 224 hsyncend = mode->crtc_hsync_end / 8 - 1; 225 htotal = mode->crtc_htotal / 8 - 1; 226 /* Work around hardware quirk */ 227 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 228 htotal++; 229 hblkstr = mode->crtc_hblank_start / 8 - 1; 230 hblkend = htotal; 231 232 vdispend = mode->crtc_vdisplay - 1; 233 vsyncstr = mode->crtc_vsync_start - 1; 234 vsyncend = mode->crtc_vsync_end - 1; 235 vtotal = mode->crtc_vtotal - 2; 236 vblkstr = mode->crtc_vblank_start - 1; 237 vblkend = vtotal + 1; 238 239 linecomp = vdispend; 240 241 misc = RREG8(MGA_MISC_IN); 242 243 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 244 misc |= MGAREG_MISC_HSYNCPOL; 245 else 246 misc &= ~MGAREG_MISC_HSYNCPOL; 247 248 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 249 misc |= MGAREG_MISC_VSYNCPOL; 250 else 251 misc &= ~MGAREG_MISC_VSYNCPOL; 252 253 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 254 ((hblkstr & 0x100) >> 7) | 255 ((hsyncstr & 0x100) >> 6) | 256 (hblkend & 0x40); 257 if (set_vidrst) 258 crtcext1 |= MGAREG_CRTCEXT1_VRSTEN | 259 MGAREG_CRTCEXT1_HRSTEN; 260 261 crtcext2 = ((vtotal & 0xc00) >> 10) | 262 ((vdispend & 0x400) >> 8) | 263 ((vblkstr & 0xc00) >> 7) | 264 ((vsyncstr & 0xc00) >> 5) | 265 ((linecomp & 0x400) >> 3); 266 crtcext5 = 0x00; 267 268 WREG_CRT(0x00, htotal - 4); 269 WREG_CRT(0x01, hdispend); 270 WREG_CRT(0x02, hblkstr); 271 WREG_CRT(0x03, (hblkend & 0x1f) | 0x80); 272 WREG_CRT(0x04, hsyncstr); 273 WREG_CRT(0x05, ((hblkend & 0x20) << 2) | (hsyncend & 0x1f)); 274 WREG_CRT(0x06, vtotal & 0xff); 275 WREG_CRT(0x07, ((vtotal & 0x100) >> 8) | 276 ((vdispend & 0x100) >> 7) | 277 ((vsyncstr & 0x100) >> 6) | 278 ((vblkstr & 0x100) >> 5) | 279 ((linecomp & 0x100) >> 4) | 280 ((vtotal & 0x200) >> 4) | 281 ((vdispend & 0x200) >> 3) | 282 ((vsyncstr & 0x200) >> 2)); 283 WREG_CRT(0x09, ((vblkstr & 0x200) >> 4) | 284 ((linecomp & 0x200) >> 3)); 285 WREG_CRT(0x10, vsyncstr & 0xff); 286 WREG_CRT(0x11, (vsyncend & 0x0f) | 0x20); 287 WREG_CRT(0x12, vdispend & 0xff); 288 WREG_CRT(0x14, 0); 289 WREG_CRT(0x15, vblkstr & 0xff); 290 WREG_CRT(0x16, vblkend & 0xff); 291 WREG_CRT(0x17, 0xc3); 292 WREG_CRT(0x18, linecomp & 0xff); 293 294 WREG_ECRT(0x01, crtcext1); 295 WREG_ECRT(0x02, crtcext2); 296 WREG_ECRT(0x05, crtcext5); 297 298 WREG8(MGA_MISC_OUT, misc); 299 } 300 301 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 302 { 303 static const u8 bpp_shift[] = {0, 1, 0, 2}; 304 305 return bpp_shift[format->cpp[0] - 1]; 306 } 307 308 /* 309 * Calculates the HW offset value from the framebuffer's pitch. The 310 * offset is a multiple of the pixel size and depends on the display 311 * format. 312 */ 313 static u32 mgag200_calculate_offset(struct mga_device *mdev, 314 const struct drm_framebuffer *fb) 315 { 316 u32 offset = fb->pitches[0] / fb->format->cpp[0]; 317 u8 bppshift = mgag200_get_bpp_shift(fb->format); 318 319 if (fb->format->cpp[0] * 8 == 24) 320 offset = (offset * 3) >> (4 - bppshift); 321 else 322 offset = offset >> (4 - bppshift); 323 324 return offset; 325 } 326 327 static void mgag200_set_offset(struct mga_device *mdev, 328 const struct drm_framebuffer *fb) 329 { 330 u8 crtc13, crtcext0; 331 u32 offset = mgag200_calculate_offset(mdev, fb); 332 333 RREG_ECRT(0, crtcext0); 334 335 crtc13 = offset & 0xff; 336 337 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 338 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 339 340 WREG_CRT(0x13, crtc13); 341 WREG_ECRT(0x00, crtcext0); 342 } 343 344 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format) 345 { 346 struct drm_device *dev = &mdev->base; 347 unsigned int bpp, bppshift, scale; 348 u8 crtcext3, xmulctrl; 349 350 bpp = format->cpp[0] * 8; 351 352 bppshift = mgag200_get_bpp_shift(format); 353 switch (bpp) { 354 case 24: 355 scale = ((1 << bppshift) * 3) - 1; 356 break; 357 default: 358 scale = (1 << bppshift) - 1; 359 break; 360 } 361 362 RREG_ECRT(3, crtcext3); 363 364 switch (bpp) { 365 case 8: 366 xmulctrl = MGA1064_MUL_CTL_8bits; 367 break; 368 case 16: 369 if (format->depth == 15) 370 xmulctrl = MGA1064_MUL_CTL_15bits; 371 else 372 xmulctrl = MGA1064_MUL_CTL_16bits; 373 break; 374 case 24: 375 xmulctrl = MGA1064_MUL_CTL_24bits; 376 break; 377 case 32: 378 xmulctrl = MGA1064_MUL_CTL_32_24bits; 379 break; 380 default: 381 /* BUG: We should have caught this problem already. */ 382 drm_WARN_ON(dev, "invalid format depth\n"); 383 return; 384 } 385 386 crtcext3 &= ~GENMASK(2, 0); 387 crtcext3 |= scale; 388 389 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 390 391 WREG_GFX(0, 0x00); 392 WREG_GFX(1, 0x00); 393 WREG_GFX(2, 0x00); 394 WREG_GFX(3, 0x00); 395 WREG_GFX(4, 0x00); 396 WREG_GFX(5, 0x40); 397 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 398 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 399 */ 400 WREG_GFX(6, 0x0d); 401 WREG_GFX(7, 0x0f); 402 WREG_GFX(8, 0x0f); 403 404 WREG_ECRT(3, crtcext3); 405 } 406 407 void mgag200_enable_display(struct mga_device *mdev) 408 { 409 u8 seq0, crtcext1; 410 411 RREG_SEQ(0x00, seq0); 412 seq0 |= MGAREG_SEQ0_SYNCRST | 413 MGAREG_SEQ0_ASYNCRST; 414 WREG_SEQ(0x00, seq0); 415 416 /* 417 * TODO: replace busy waiting with vblank IRQ; put 418 * msleep(50) before changing SCROFF 419 */ 420 mga_wait_vsync(mdev); 421 mga_wait_busy(mdev); 422 423 RREG_ECRT(0x01, crtcext1); 424 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 425 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 426 WREG_ECRT(0x01, crtcext1); 427 } 428 429 static void mgag200_disable_display(struct mga_device *mdev) 430 { 431 u8 seq0, crtcext1; 432 433 RREG_SEQ(0x00, seq0); 434 seq0 &= ~MGAREG_SEQ0_SYNCRST; 435 WREG_SEQ(0x00, seq0); 436 437 /* 438 * TODO: replace busy waiting with vblank IRQ; put 439 * msleep(50) before changing SCROFF 440 */ 441 mga_wait_vsync(mdev); 442 mga_wait_busy(mdev); 443 444 RREG_ECRT(0x01, crtcext1); 445 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 446 MGAREG_CRTCEXT1_HSYNCOFF; 447 WREG_ECRT(0x01, crtcext1); 448 } 449 450 static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap, 451 struct drm_framebuffer *fb, struct drm_rect *clip) 452 { 453 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 454 455 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip)); 456 drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip); 457 } 458 459 /* 460 * Primary plane 461 */ 462 463 const uint32_t mgag200_primary_plane_formats[] = { 464 DRM_FORMAT_XRGB8888, 465 DRM_FORMAT_RGB565, 466 DRM_FORMAT_RGB888, 467 }; 468 469 const size_t mgag200_primary_plane_formats_size = ARRAY_SIZE(mgag200_primary_plane_formats); 470 471 const uint64_t mgag200_primary_plane_fmtmods[] = { 472 DRM_FORMAT_MOD_LINEAR, 473 DRM_FORMAT_MOD_INVALID 474 }; 475 476 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 477 struct drm_atomic_state *new_state) 478 { 479 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); 480 struct drm_framebuffer *new_fb = new_plane_state->fb; 481 struct drm_framebuffer *fb = NULL; 482 struct drm_crtc *new_crtc = new_plane_state->crtc; 483 struct drm_crtc_state *new_crtc_state = NULL; 484 struct mgag200_crtc_state *new_mgag200_crtc_state; 485 int ret; 486 487 if (new_crtc) 488 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_crtc); 489 490 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 491 DRM_PLANE_NO_SCALING, 492 DRM_PLANE_NO_SCALING, 493 false, true); 494 if (ret) 495 return ret; 496 else if (!new_plane_state->visible) 497 return 0; 498 499 if (plane->state) 500 fb = plane->state->fb; 501 502 if (!fb || (fb->format != new_fb->format)) 503 new_crtc_state->mode_changed = true; /* update PLL settings */ 504 505 new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state); 506 new_mgag200_crtc_state->format = new_fb->format; 507 508 return 0; 509 } 510 511 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 512 struct drm_atomic_state *old_state) 513 { 514 struct drm_device *dev = plane->dev; 515 struct mga_device *mdev = to_mga_device(dev); 516 struct drm_plane_state *plane_state = plane->state; 517 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane); 518 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 519 struct drm_framebuffer *fb = plane_state->fb; 520 struct drm_atomic_helper_damage_iter iter; 521 struct drm_rect damage; 522 523 mgag200_set_datasiz(mdev, fb->format->format); 524 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 525 drm_atomic_for_each_plane_damage(&iter, &damage) { 526 mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage); 527 } 528 529 /* Always scanout image at VRAM offset 0 */ 530 mgag200_set_startadd(mdev, (u32)0); 531 mgag200_set_offset(mdev, fb); 532 } 533 534 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, 535 struct drm_atomic_state *state) 536 { 537 struct drm_device *dev = plane->dev; 538 struct mga_device *mdev = to_mga_device(dev); 539 u8 seq1; 540 541 RREG_SEQ(0x01, seq1); 542 seq1 &= ~MGAREG_SEQ1_SCROFF; 543 WREG_SEQ(0x01, seq1); 544 msleep(20); 545 } 546 547 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 548 struct drm_atomic_state *old_state) 549 { 550 struct drm_device *dev = plane->dev; 551 struct mga_device *mdev = to_mga_device(dev); 552 u8 seq1; 553 554 RREG_SEQ(0x01, seq1); 555 seq1 |= MGAREG_SEQ1_SCROFF; 556 WREG_SEQ(0x01, seq1); 557 msleep(20); 558 } 559 560 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 561 struct drm_scanout_buffer *sb) 562 { 563 struct mga_device *mdev = to_mga_device(plane->dev); 564 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 565 566 if (plane->state && plane->state->fb) { 567 sb->format = plane->state->fb->format; 568 sb->width = plane->state->fb->width; 569 sb->height = plane->state->fb->height; 570 sb->pitch[0] = plane->state->fb->pitches[0]; 571 sb->map[0] = map; 572 return 0; 573 } 574 return -ENODEV; 575 } 576 577 /* 578 * CRTC 579 */ 580 581 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 582 const struct drm_display_mode *mode) 583 { 584 struct mga_device *mdev = to_mga_device(crtc->dev); 585 const struct mgag200_device_info *info = mdev->info; 586 587 /* 588 * Some devices have additional limits on the size of the 589 * display mode. 590 */ 591 if (mode->hdisplay > info->max_hdisplay) 592 return MODE_VIRTUAL_X; 593 if (mode->vdisplay > info->max_vdisplay) 594 return MODE_VIRTUAL_Y; 595 596 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 597 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 598 return MODE_H_ILLEGAL; 599 } 600 601 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 602 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 603 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 604 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 605 return MODE_BAD; 606 } 607 608 return MODE_OK; 609 } 610 611 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state) 612 { 613 struct drm_device *dev = crtc->dev; 614 struct mga_device *mdev = to_mga_device(dev); 615 const struct mgag200_device_funcs *funcs = mdev->funcs; 616 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 617 struct drm_property_blob *new_gamma_lut = new_crtc_state->gamma_lut; 618 int ret; 619 620 if (!new_crtc_state->enable) 621 return 0; 622 623 ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state); 624 if (ret) 625 return ret; 626 627 if (new_crtc_state->mode_changed) { 628 if (funcs->pixpllc_atomic_check) { 629 ret = funcs->pixpllc_atomic_check(crtc, new_state); 630 if (ret) 631 return ret; 632 } 633 } 634 635 if (new_crtc_state->color_mgmt_changed && new_gamma_lut) { 636 if (new_gamma_lut->length != MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 637 drm_dbg(dev, "Wrong size for gamma_lut %zu\n", new_gamma_lut->length); 638 return -EINVAL; 639 } 640 } 641 642 return 0; 643 } 644 645 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 646 { 647 struct drm_crtc_state *crtc_state = crtc->state; 648 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 649 struct drm_device *dev = crtc->dev; 650 struct mga_device *mdev = to_mga_device(dev); 651 652 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 653 const struct drm_format_info *format = mgag200_crtc_state->format; 654 655 if (crtc_state->gamma_lut) 656 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data); 657 else 658 mgag200_crtc_fill_gamma(mdev, format); 659 } 660 } 661 662 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 663 { 664 struct drm_device *dev = crtc->dev; 665 struct mga_device *mdev = to_mga_device(dev); 666 const struct mgag200_device_funcs *funcs = mdev->funcs; 667 struct drm_crtc_state *crtc_state = crtc->state; 668 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 669 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 670 const struct drm_format_info *format = mgag200_crtc_state->format; 671 672 mgag200_set_format_regs(mdev, format); 673 mgag200_set_mode_regs(mdev, adjusted_mode, mgag200_crtc_state->set_vidrst); 674 675 if (funcs->pixpllc_atomic_update) 676 funcs->pixpllc_atomic_update(crtc, old_state); 677 678 if (crtc_state->gamma_lut) 679 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data); 680 else 681 mgag200_crtc_fill_gamma(mdev, format); 682 683 mgag200_enable_display(mdev); 684 } 685 686 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 687 { 688 struct mga_device *mdev = to_mga_device(crtc->dev); 689 690 mgag200_disable_display(mdev); 691 } 692 693 void mgag200_crtc_reset(struct drm_crtc *crtc) 694 { 695 struct mgag200_crtc_state *mgag200_crtc_state; 696 697 if (crtc->state) 698 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 699 700 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 701 if (mgag200_crtc_state) 702 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 703 else 704 __drm_atomic_helper_crtc_reset(crtc, NULL); 705 } 706 707 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 708 { 709 struct drm_crtc_state *crtc_state = crtc->state; 710 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 711 struct mgag200_crtc_state *new_mgag200_crtc_state; 712 713 if (!crtc_state) 714 return NULL; 715 716 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 717 if (!new_mgag200_crtc_state) 718 return NULL; 719 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 720 721 new_mgag200_crtc_state->format = mgag200_crtc_state->format; 722 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 723 sizeof(new_mgag200_crtc_state->pixpllc)); 724 new_mgag200_crtc_state->set_vidrst = mgag200_crtc_state->set_vidrst; 725 726 return &new_mgag200_crtc_state->base; 727 } 728 729 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 730 { 731 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 732 733 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 734 kfree(mgag200_crtc_state); 735 } 736 737 /* 738 * Mode config 739 */ 740 741 static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state) 742 { 743 struct mga_device *mdev = to_mga_device(state->dev); 744 745 /* 746 * Concurrent operations could possibly trigger a call to 747 * drm_connector_helper_funcs.get_modes by trying to read the 748 * display modes. Protect access to I/O registers by acquiring 749 * the I/O-register lock. 750 */ 751 mutex_lock(&mdev->rmmio_lock); 752 drm_atomic_helper_commit_tail(state); 753 mutex_unlock(&mdev->rmmio_lock); 754 } 755 756 static const struct drm_mode_config_helper_funcs mgag200_mode_config_helper_funcs = { 757 .atomic_commit_tail = mgag200_mode_config_helper_atomic_commit_tail, 758 }; 759 760 /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 761 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 762 unsigned int bits_per_pixel) 763 { 764 uint32_t total_area, divisor; 765 uint64_t active_area, pixels_per_second, bandwidth; 766 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 767 768 divisor = 1024; 769 770 if (!mode->htotal || !mode->vtotal || !mode->clock) 771 return 0; 772 773 active_area = mode->hdisplay * mode->vdisplay; 774 total_area = mode->htotal * mode->vtotal; 775 776 pixels_per_second = active_area * mode->clock * 1000; 777 do_div(pixels_per_second, total_area); 778 779 bandwidth = pixels_per_second * bytes_per_pixel * 100; 780 do_div(bandwidth, divisor); 781 782 return (uint32_t)bandwidth; 783 } 784 785 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 786 const struct drm_display_mode *mode) 787 { 788 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 789 struct mga_device *mdev = to_mga_device(dev); 790 unsigned long fbsize, fbpages, max_fbpages; 791 const struct mgag200_device_info *info = mdev->info; 792 793 max_fbpages = mdev->vram_available >> PAGE_SHIFT; 794 795 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 796 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 797 798 if (fbpages > max_fbpages) 799 return MODE_MEM; 800 801 /* 802 * Test the mode's required memory bandwidth if the device 803 * specifies a maximum. Not all devices do though. 804 */ 805 if (info->max_mem_bandwidth) { 806 uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8); 807 808 if (mode_bandwidth > (info->max_mem_bandwidth * 1024)) 809 return MODE_BAD; 810 } 811 812 return MODE_OK; 813 } 814 815 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 816 .fb_create = drm_gem_fb_create_with_dirty, 817 .mode_valid = mgag200_mode_config_mode_valid, 818 .atomic_check = drm_atomic_helper_check, 819 .atomic_commit = drm_atomic_helper_commit, 820 }; 821 822 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available) 823 { 824 struct drm_device *dev = &mdev->base; 825 int ret; 826 827 mdev->vram_available = vram_available; 828 829 ret = drmm_mode_config_init(dev); 830 if (ret) { 831 drm_err(dev, "drmm_mode_config_init() failed: %d\n", ret); 832 return ret; 833 } 834 835 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 836 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 837 dev->mode_config.preferred_depth = 24; 838 dev->mode_config.funcs = &mgag200_mode_config_funcs; 839 dev->mode_config.helper_private = &mgag200_mode_config_helper_funcs; 840 841 return 0; 842 } 843