1414c4531SDave Airlie /* 2414c4531SDave Airlie * Copyright 2010 Matt Turner. 3414c4531SDave Airlie * Copyright 2012 Red Hat 4414c4531SDave Airlie * 5414c4531SDave Airlie * This file is subject to the terms and conditions of the GNU General 6414c4531SDave Airlie * Public License version 2. See the file COPYING in the main 7414c4531SDave Airlie * directory of this archive for more details. 8414c4531SDave Airlie * 9414c4531SDave Airlie * Authors: Matthew Garrett 10414c4531SDave Airlie * Matt Turner 11414c4531SDave Airlie * Dave Airlie 12414c4531SDave Airlie */ 13414c4531SDave Airlie 14414c4531SDave Airlie #include <linux/delay.h> 15414c4531SDave Airlie 16760285e7SDavid Howells #include <drm/drmP.h> 17760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 183cb9ae4fSDaniel Vetter #include <drm/drm_plane_helper.h> 19414c4531SDave Airlie 20414c4531SDave Airlie #include "mgag200_drv.h" 21414c4531SDave Airlie 22414c4531SDave Airlie #define MGAG200_LUT_SIZE 256 23414c4531SDave Airlie 24414c4531SDave Airlie /* 25414c4531SDave Airlie * This file contains setup code for the CRTC. 26414c4531SDave Airlie */ 27414c4531SDave Airlie 28414c4531SDave Airlie static void mga_crtc_load_lut(struct drm_crtc *crtc) 29414c4531SDave Airlie { 30414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 31414c4531SDave Airlie struct drm_device *dev = crtc->dev; 32414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 33f4510a27SMatt Roper struct drm_framebuffer *fb = crtc->primary->fb; 34414c4531SDave Airlie int i; 35414c4531SDave Airlie 36414c4531SDave Airlie if (!crtc->enabled) 37414c4531SDave Airlie return; 38414c4531SDave Airlie 39414c4531SDave Airlie WREG8(DAC_INDEX + MGA1064_INDEX, 0); 40414c4531SDave Airlie 41de7500eaSEgbert Eich if (fb && fb->bits_per_pixel == 16) { 42de7500eaSEgbert Eich int inc = (fb->depth == 15) ? 8 : 4; 43de7500eaSEgbert Eich u8 r, b; 44de7500eaSEgbert Eich for (i = 0; i < MGAG200_LUT_SIZE; i += inc) { 45de7500eaSEgbert Eich if (fb->depth == 16) { 46de7500eaSEgbert Eich if (i > (MGAG200_LUT_SIZE >> 1)) { 47de7500eaSEgbert Eich r = b = 0; 48de7500eaSEgbert Eich } else { 49de7500eaSEgbert Eich r = mga_crtc->lut_r[i << 1]; 50de7500eaSEgbert Eich b = mga_crtc->lut_b[i << 1]; 51de7500eaSEgbert Eich } 52de7500eaSEgbert Eich } else { 53de7500eaSEgbert Eich r = mga_crtc->lut_r[i]; 54de7500eaSEgbert Eich b = mga_crtc->lut_b[i]; 55de7500eaSEgbert Eich } 56de7500eaSEgbert Eich /* VGA registers */ 57de7500eaSEgbert Eich WREG8(DAC_INDEX + MGA1064_COL_PAL, r); 58de7500eaSEgbert Eich WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); 59de7500eaSEgbert Eich WREG8(DAC_INDEX + MGA1064_COL_PAL, b); 60de7500eaSEgbert Eich } 61de7500eaSEgbert Eich return; 62de7500eaSEgbert Eich } 63414c4531SDave Airlie for (i = 0; i < MGAG200_LUT_SIZE; i++) { 64414c4531SDave Airlie /* VGA registers */ 65414c4531SDave Airlie WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]); 66414c4531SDave Airlie WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); 67414c4531SDave Airlie WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]); 68414c4531SDave Airlie } 69414c4531SDave Airlie } 70414c4531SDave Airlie 71414c4531SDave Airlie static inline void mga_wait_vsync(struct mga_device *mdev) 72414c4531SDave Airlie { 733cdc0e8dSChristopher Harvey unsigned long timeout = jiffies + HZ/10; 74414c4531SDave Airlie unsigned int status = 0; 75414c4531SDave Airlie 76414c4531SDave Airlie do { 77414c4531SDave Airlie status = RREG32(MGAREG_Status); 783cdc0e8dSChristopher Harvey } while ((status & 0x08) && time_before(jiffies, timeout)); 793cdc0e8dSChristopher Harvey timeout = jiffies + HZ/10; 80414c4531SDave Airlie status = 0; 81414c4531SDave Airlie do { 82414c4531SDave Airlie status = RREG32(MGAREG_Status); 833cdc0e8dSChristopher Harvey } while (!(status & 0x08) && time_before(jiffies, timeout)); 84414c4531SDave Airlie } 85414c4531SDave Airlie 86414c4531SDave Airlie static inline void mga_wait_busy(struct mga_device *mdev) 87414c4531SDave Airlie { 883cdc0e8dSChristopher Harvey unsigned long timeout = jiffies + HZ; 89414c4531SDave Airlie unsigned int status = 0; 90414c4531SDave Airlie do { 91414c4531SDave Airlie status = RREG8(MGAREG_Status + 2); 923cdc0e8dSChristopher Harvey } while ((status & 0x01) && time_before(jiffies, timeout)); 93414c4531SDave Airlie } 94414c4531SDave Airlie 95414c4531SDave Airlie /* 96414c4531SDave Airlie * The core passes the desired mode to the CRTC code to see whether any 97414c4531SDave Airlie * CRTC-specific modifications need to be made to it. We're in a position 98414c4531SDave Airlie * to just pass that straight through, so this does nothing 99414c4531SDave Airlie */ 100414c4531SDave Airlie static bool mga_crtc_mode_fixup(struct drm_crtc *crtc, 101e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 102414c4531SDave Airlie struct drm_display_mode *adjusted_mode) 103414c4531SDave Airlie { 104414c4531SDave Airlie return true; 105414c4531SDave Airlie } 106414c4531SDave Airlie 107414c4531SDave Airlie static int mga_g200se_set_plls(struct mga_device *mdev, long clock) 108414c4531SDave Airlie { 109414c4531SDave Airlie unsigned int vcomax, vcomin, pllreffreq; 110414c4531SDave Airlie unsigned int delta, tmpdelta, permitteddelta; 111414c4531SDave Airlie unsigned int testp, testm, testn; 112414c4531SDave Airlie unsigned int p, m, n; 113414c4531SDave Airlie unsigned int computed; 114414c4531SDave Airlie 115414c4531SDave Airlie m = n = p = 0; 116414c4531SDave Airlie vcomax = 320000; 117414c4531SDave Airlie vcomin = 160000; 118414c4531SDave Airlie pllreffreq = 25000; 119414c4531SDave Airlie 120414c4531SDave Airlie delta = 0xffffffff; 121414c4531SDave Airlie permitteddelta = clock * 5 / 1000; 122414c4531SDave Airlie 123414c4531SDave Airlie for (testp = 8; testp > 0; testp /= 2) { 124414c4531SDave Airlie if (clock * testp > vcomax) 125414c4531SDave Airlie continue; 126414c4531SDave Airlie if (clock * testp < vcomin) 127414c4531SDave Airlie continue; 128414c4531SDave Airlie 129414c4531SDave Airlie for (testn = 17; testn < 256; testn++) { 130414c4531SDave Airlie for (testm = 1; testm < 32; testm++) { 131414c4531SDave Airlie computed = (pllreffreq * testn) / 132414c4531SDave Airlie (testm * testp); 133414c4531SDave Airlie if (computed > clock) 134414c4531SDave Airlie tmpdelta = computed - clock; 135414c4531SDave Airlie else 136414c4531SDave Airlie tmpdelta = clock - computed; 137414c4531SDave Airlie if (tmpdelta < delta) { 138414c4531SDave Airlie delta = tmpdelta; 139414c4531SDave Airlie m = testm - 1; 140414c4531SDave Airlie n = testn - 1; 141414c4531SDave Airlie p = testp - 1; 142414c4531SDave Airlie } 143414c4531SDave Airlie } 144414c4531SDave Airlie } 145414c4531SDave Airlie } 146414c4531SDave Airlie 147414c4531SDave Airlie if (delta > permitteddelta) { 148414c4531SDave Airlie printk(KERN_WARNING "PLL delta too large\n"); 149414c4531SDave Airlie return 1; 150414c4531SDave Airlie } 151414c4531SDave Airlie 152414c4531SDave Airlie WREG_DAC(MGA1064_PIX_PLLC_M, m); 153414c4531SDave Airlie WREG_DAC(MGA1064_PIX_PLLC_N, n); 154414c4531SDave Airlie WREG_DAC(MGA1064_PIX_PLLC_P, p); 155414c4531SDave Airlie return 0; 156414c4531SDave Airlie } 157414c4531SDave Airlie 158414c4531SDave Airlie static int mga_g200wb_set_plls(struct mga_device *mdev, long clock) 159414c4531SDave Airlie { 160414c4531SDave Airlie unsigned int vcomax, vcomin, pllreffreq; 161414c4531SDave Airlie unsigned int delta, tmpdelta, permitteddelta; 162414c4531SDave Airlie unsigned int testp, testm, testn; 163414c4531SDave Airlie unsigned int p, m, n; 164414c4531SDave Airlie unsigned int computed; 165414c4531SDave Airlie int i, j, tmpcount, vcount; 166414c4531SDave Airlie bool pll_locked = false; 167414c4531SDave Airlie u8 tmp; 168414c4531SDave Airlie 169414c4531SDave Airlie m = n = p = 0; 170414c4531SDave Airlie vcomax = 550000; 171414c4531SDave Airlie vcomin = 150000; 172414c4531SDave Airlie pllreffreq = 48000; 173414c4531SDave Airlie 174414c4531SDave Airlie delta = 0xffffffff; 175414c4531SDave Airlie permitteddelta = clock * 5 / 1000; 176414c4531SDave Airlie 177414c4531SDave Airlie for (testp = 1; testp < 9; testp++) { 178414c4531SDave Airlie if (clock * testp > vcomax) 179414c4531SDave Airlie continue; 180414c4531SDave Airlie if (clock * testp < vcomin) 181414c4531SDave Airlie continue; 182414c4531SDave Airlie 183414c4531SDave Airlie for (testm = 1; testm < 17; testm++) { 184414c4531SDave Airlie for (testn = 1; testn < 151; testn++) { 185414c4531SDave Airlie computed = (pllreffreq * testn) / 186414c4531SDave Airlie (testm * testp); 187414c4531SDave Airlie if (computed > clock) 188414c4531SDave Airlie tmpdelta = computed - clock; 189414c4531SDave Airlie else 190414c4531SDave Airlie tmpdelta = clock - computed; 191414c4531SDave Airlie if (tmpdelta < delta) { 192414c4531SDave Airlie delta = tmpdelta; 193414c4531SDave Airlie n = testn - 1; 194414c4531SDave Airlie m = (testm - 1) | ((n >> 1) & 0x80); 195414c4531SDave Airlie p = testp - 1; 196414c4531SDave Airlie } 197414c4531SDave Airlie } 198414c4531SDave Airlie } 199414c4531SDave Airlie } 200414c4531SDave Airlie 201414c4531SDave Airlie for (i = 0; i <= 32 && pll_locked == false; i++) { 202414c4531SDave Airlie if (i > 0) { 203414c4531SDave Airlie WREG8(MGAREG_CRTC_INDEX, 0x1e); 204414c4531SDave Airlie tmp = RREG8(MGAREG_CRTC_DATA); 205414c4531SDave Airlie if (tmp < 0xff) 206414c4531SDave Airlie WREG8(MGAREG_CRTC_DATA, tmp+1); 207414c4531SDave Airlie } 208414c4531SDave Airlie 209414c4531SDave Airlie /* set pixclkdis to 1 */ 210414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 211414c4531SDave Airlie tmp = RREG8(DAC_DATA); 212414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 213fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 214414c4531SDave Airlie 215414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 216414c4531SDave Airlie tmp = RREG8(DAC_DATA); 217414c4531SDave Airlie tmp |= MGA1064_REMHEADCTL_CLKDIS; 218fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 219414c4531SDave Airlie 220414c4531SDave Airlie /* select PLL Set C */ 221414c4531SDave Airlie tmp = RREG8(MGAREG_MEM_MISC_READ); 222414c4531SDave Airlie tmp |= 0x3 << 2; 223414c4531SDave Airlie WREG8(MGAREG_MEM_MISC_WRITE, tmp); 224414c4531SDave Airlie 225414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 226414c4531SDave Airlie tmp = RREG8(DAC_DATA); 227414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; 228fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 229414c4531SDave Airlie 230414c4531SDave Airlie udelay(500); 231414c4531SDave Airlie 232414c4531SDave Airlie /* reset the PLL */ 233414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_VREF_CTL); 234414c4531SDave Airlie tmp = RREG8(DAC_DATA); 235414c4531SDave Airlie tmp &= ~0x04; 236fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 237414c4531SDave Airlie 238414c4531SDave Airlie udelay(50); 239414c4531SDave Airlie 240414c4531SDave Airlie /* program pixel pll register */ 241414c4531SDave Airlie WREG_DAC(MGA1064_WB_PIX_PLLC_N, n); 242414c4531SDave Airlie WREG_DAC(MGA1064_WB_PIX_PLLC_M, m); 243414c4531SDave Airlie WREG_DAC(MGA1064_WB_PIX_PLLC_P, p); 244414c4531SDave Airlie 245414c4531SDave Airlie udelay(50); 246414c4531SDave Airlie 247414c4531SDave Airlie /* turn pll on */ 248414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_VREF_CTL); 249414c4531SDave Airlie tmp = RREG8(DAC_DATA); 250414c4531SDave Airlie tmp |= 0x04; 251414c4531SDave Airlie WREG_DAC(MGA1064_VREF_CTL, tmp); 252414c4531SDave Airlie 253414c4531SDave Airlie udelay(500); 254414c4531SDave Airlie 255414c4531SDave Airlie /* select the pixel pll */ 256414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 257414c4531SDave Airlie tmp = RREG8(DAC_DATA); 258414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 259414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 260fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 261414c4531SDave Airlie 262414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 263414c4531SDave Airlie tmp = RREG8(DAC_DATA); 264414c4531SDave Airlie tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; 265414c4531SDave Airlie tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; 266fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 267414c4531SDave Airlie 268414c4531SDave Airlie /* reset dotclock rate bit */ 269414c4531SDave Airlie WREG8(MGAREG_SEQ_INDEX, 1); 270414c4531SDave Airlie tmp = RREG8(MGAREG_SEQ_DATA); 271414c4531SDave Airlie tmp &= ~0x8; 272414c4531SDave Airlie WREG8(MGAREG_SEQ_DATA, tmp); 273414c4531SDave Airlie 274414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 275414c4531SDave Airlie tmp = RREG8(DAC_DATA); 276414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 277fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 278414c4531SDave Airlie 279414c4531SDave Airlie vcount = RREG8(MGAREG_VCOUNT); 280414c4531SDave Airlie 281414c4531SDave Airlie for (j = 0; j < 30 && pll_locked == false; j++) { 282414c4531SDave Airlie tmpcount = RREG8(MGAREG_VCOUNT); 283414c4531SDave Airlie if (tmpcount < vcount) 284414c4531SDave Airlie vcount = 0; 285414c4531SDave Airlie if ((tmpcount - vcount) > 2) 286414c4531SDave Airlie pll_locked = true; 287414c4531SDave Airlie else 288414c4531SDave Airlie udelay(5); 289414c4531SDave Airlie } 290414c4531SDave Airlie } 291414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 292414c4531SDave Airlie tmp = RREG8(DAC_DATA); 293414c4531SDave Airlie tmp &= ~MGA1064_REMHEADCTL_CLKDIS; 294414c4531SDave Airlie WREG_DAC(MGA1064_REMHEADCTL, tmp); 295414c4531SDave Airlie return 0; 296414c4531SDave Airlie } 297414c4531SDave Airlie 298414c4531SDave Airlie static int mga_g200ev_set_plls(struct mga_device *mdev, long clock) 299414c4531SDave Airlie { 300414c4531SDave Airlie unsigned int vcomax, vcomin, pllreffreq; 301414c4531SDave Airlie unsigned int delta, tmpdelta, permitteddelta; 302414c4531SDave Airlie unsigned int testp, testm, testn; 303414c4531SDave Airlie unsigned int p, m, n; 304414c4531SDave Airlie unsigned int computed; 305414c4531SDave Airlie u8 tmp; 306414c4531SDave Airlie 307414c4531SDave Airlie m = n = p = 0; 308414c4531SDave Airlie vcomax = 550000; 309414c4531SDave Airlie vcomin = 150000; 310414c4531SDave Airlie pllreffreq = 50000; 311414c4531SDave Airlie 312414c4531SDave Airlie delta = 0xffffffff; 313414c4531SDave Airlie permitteddelta = clock * 5 / 1000; 314414c4531SDave Airlie 315414c4531SDave Airlie for (testp = 16; testp > 0; testp--) { 316414c4531SDave Airlie if (clock * testp > vcomax) 317414c4531SDave Airlie continue; 318414c4531SDave Airlie if (clock * testp < vcomin) 319414c4531SDave Airlie continue; 320414c4531SDave Airlie 321414c4531SDave Airlie for (testn = 1; testn < 257; testn++) { 322414c4531SDave Airlie for (testm = 1; testm < 17; testm++) { 323414c4531SDave Airlie computed = (pllreffreq * testn) / 324414c4531SDave Airlie (testm * testp); 325414c4531SDave Airlie if (computed > clock) 326414c4531SDave Airlie tmpdelta = computed - clock; 327414c4531SDave Airlie else 328414c4531SDave Airlie tmpdelta = clock - computed; 329414c4531SDave Airlie if (tmpdelta < delta) { 330414c4531SDave Airlie delta = tmpdelta; 331414c4531SDave Airlie n = testn - 1; 332414c4531SDave Airlie m = testm - 1; 333414c4531SDave Airlie p = testp - 1; 334414c4531SDave Airlie } 335414c4531SDave Airlie } 336414c4531SDave Airlie } 337414c4531SDave Airlie } 338414c4531SDave Airlie 339414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 340414c4531SDave Airlie tmp = RREG8(DAC_DATA); 341414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 342fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 343414c4531SDave Airlie 344414c4531SDave Airlie tmp = RREG8(MGAREG_MEM_MISC_READ); 345414c4531SDave Airlie tmp |= 0x3 << 2; 346414c4531SDave Airlie WREG8(MGAREG_MEM_MISC_WRITE, tmp); 347414c4531SDave Airlie 348414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 349414c4531SDave Airlie tmp = RREG8(DAC_DATA); 350fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp & ~0x40); 351414c4531SDave Airlie 352414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 353414c4531SDave Airlie tmp = RREG8(DAC_DATA); 354414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 355fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 356414c4531SDave Airlie 357414c4531SDave Airlie WREG_DAC(MGA1064_EV_PIX_PLLC_M, m); 358414c4531SDave Airlie WREG_DAC(MGA1064_EV_PIX_PLLC_N, n); 359414c4531SDave Airlie WREG_DAC(MGA1064_EV_PIX_PLLC_P, p); 360414c4531SDave Airlie 361414c4531SDave Airlie udelay(50); 362414c4531SDave Airlie 363414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 364414c4531SDave Airlie tmp = RREG8(DAC_DATA); 365414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 366fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 367414c4531SDave Airlie 368414c4531SDave Airlie udelay(500); 369414c4531SDave Airlie 370414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 371414c4531SDave Airlie tmp = RREG8(DAC_DATA); 372414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 373414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 374fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 375414c4531SDave Airlie 376414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 377414c4531SDave Airlie tmp = RREG8(DAC_DATA); 378fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp | 0x40); 379414c4531SDave Airlie 380414c4531SDave Airlie tmp = RREG8(MGAREG_MEM_MISC_READ); 381414c4531SDave Airlie tmp |= (0x3 << 2); 382414c4531SDave Airlie WREG8(MGAREG_MEM_MISC_WRITE, tmp); 383414c4531SDave Airlie 384414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 385414c4531SDave Airlie tmp = RREG8(DAC_DATA); 386414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 387fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 388414c4531SDave Airlie 389414c4531SDave Airlie return 0; 390414c4531SDave Airlie } 391414c4531SDave Airlie 392414c4531SDave Airlie static int mga_g200eh_set_plls(struct mga_device *mdev, long clock) 393414c4531SDave Airlie { 394414c4531SDave Airlie unsigned int vcomax, vcomin, pllreffreq; 395414c4531SDave Airlie unsigned int delta, tmpdelta, permitteddelta; 396414c4531SDave Airlie unsigned int testp, testm, testn; 397414c4531SDave Airlie unsigned int p, m, n; 398414c4531SDave Airlie unsigned int computed; 399414c4531SDave Airlie int i, j, tmpcount, vcount; 400414c4531SDave Airlie u8 tmp; 401414c4531SDave Airlie bool pll_locked = false; 402414c4531SDave Airlie 403414c4531SDave Airlie m = n = p = 0; 404414c4531SDave Airlie vcomax = 800000; 405414c4531SDave Airlie vcomin = 400000; 406260b3f12SJulia Lemire pllreffreq = 33333; 407414c4531SDave Airlie 408414c4531SDave Airlie delta = 0xffffffff; 409414c4531SDave Airlie permitteddelta = clock * 5 / 1000; 410414c4531SDave Airlie 411260b3f12SJulia Lemire for (testp = 16; testp > 0; testp >>= 1) { 412414c4531SDave Airlie if (clock * testp > vcomax) 413414c4531SDave Airlie continue; 414414c4531SDave Airlie if (clock * testp < vcomin) 415414c4531SDave Airlie continue; 416414c4531SDave Airlie 417414c4531SDave Airlie for (testm = 1; testm < 33; testm++) { 418260b3f12SJulia Lemire for (testn = 17; testn < 257; testn++) { 419414c4531SDave Airlie computed = (pllreffreq * testn) / 420414c4531SDave Airlie (testm * testp); 421414c4531SDave Airlie if (computed > clock) 422414c4531SDave Airlie tmpdelta = computed - clock; 423414c4531SDave Airlie else 424414c4531SDave Airlie tmpdelta = clock - computed; 425414c4531SDave Airlie if (tmpdelta < delta) { 426414c4531SDave Airlie delta = tmpdelta; 427414c4531SDave Airlie n = testn - 1; 428260b3f12SJulia Lemire m = (testm - 1); 429414c4531SDave Airlie p = testp - 1; 430414c4531SDave Airlie } 431414c4531SDave Airlie if ((clock * testp) >= 600000) 432260b3f12SJulia Lemire p |= 0x80; 433414c4531SDave Airlie } 434414c4531SDave Airlie } 435414c4531SDave Airlie } 436414c4531SDave Airlie for (i = 0; i <= 32 && pll_locked == false; i++) { 437414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 438414c4531SDave Airlie tmp = RREG8(DAC_DATA); 439414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 440fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 441414c4531SDave Airlie 442414c4531SDave Airlie tmp = RREG8(MGAREG_MEM_MISC_READ); 443414c4531SDave Airlie tmp |= 0x3 << 2; 444414c4531SDave Airlie WREG8(MGAREG_MEM_MISC_WRITE, tmp); 445414c4531SDave Airlie 446414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 447414c4531SDave Airlie tmp = RREG8(DAC_DATA); 448414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 449fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 450414c4531SDave Airlie 451414c4531SDave Airlie udelay(500); 452414c4531SDave Airlie 453414c4531SDave Airlie WREG_DAC(MGA1064_EH_PIX_PLLC_M, m); 454414c4531SDave Airlie WREG_DAC(MGA1064_EH_PIX_PLLC_N, n); 455414c4531SDave Airlie WREG_DAC(MGA1064_EH_PIX_PLLC_P, p); 456414c4531SDave Airlie 457414c4531SDave Airlie udelay(500); 458414c4531SDave Airlie 459414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 460414c4531SDave Airlie tmp = RREG8(DAC_DATA); 461414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 462414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 463fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 464414c4531SDave Airlie 465414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 466414c4531SDave Airlie tmp = RREG8(DAC_DATA); 467414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 468414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 469fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 470414c4531SDave Airlie 471414c4531SDave Airlie vcount = RREG8(MGAREG_VCOUNT); 472414c4531SDave Airlie 473414c4531SDave Airlie for (j = 0; j < 30 && pll_locked == false; j++) { 474414c4531SDave Airlie tmpcount = RREG8(MGAREG_VCOUNT); 475414c4531SDave Airlie if (tmpcount < vcount) 476414c4531SDave Airlie vcount = 0; 477414c4531SDave Airlie if ((tmpcount - vcount) > 2) 478414c4531SDave Airlie pll_locked = true; 479414c4531SDave Airlie else 480414c4531SDave Airlie udelay(5); 481414c4531SDave Airlie } 482414c4531SDave Airlie } 483414c4531SDave Airlie 484414c4531SDave Airlie return 0; 485414c4531SDave Airlie } 486414c4531SDave Airlie 487414c4531SDave Airlie static int mga_g200er_set_plls(struct mga_device *mdev, long clock) 488414c4531SDave Airlie { 489414c4531SDave Airlie unsigned int vcomax, vcomin, pllreffreq; 490414c4531SDave Airlie unsigned int delta, tmpdelta; 4919830605dSDave Airlie int testr, testn, testm, testo; 492414c4531SDave Airlie unsigned int p, m, n; 4939830605dSDave Airlie unsigned int computed, vco; 494414c4531SDave Airlie int tmp; 4959830605dSDave Airlie const unsigned int m_div_val[] = { 1, 2, 4, 8 }; 496414c4531SDave Airlie 497414c4531SDave Airlie m = n = p = 0; 498414c4531SDave Airlie vcomax = 1488000; 499414c4531SDave Airlie vcomin = 1056000; 500414c4531SDave Airlie pllreffreq = 48000; 501414c4531SDave Airlie 502414c4531SDave Airlie delta = 0xffffffff; 503414c4531SDave Airlie 504414c4531SDave Airlie for (testr = 0; testr < 4; testr++) { 505414c4531SDave Airlie if (delta == 0) 506414c4531SDave Airlie break; 507414c4531SDave Airlie for (testn = 5; testn < 129; testn++) { 508414c4531SDave Airlie if (delta == 0) 509414c4531SDave Airlie break; 510414c4531SDave Airlie for (testm = 3; testm >= 0; testm--) { 511414c4531SDave Airlie if (delta == 0) 512414c4531SDave Airlie break; 513414c4531SDave Airlie for (testo = 5; testo < 33; testo++) { 5149830605dSDave Airlie vco = pllreffreq * (testn + 1) / 515414c4531SDave Airlie (testr + 1); 5169830605dSDave Airlie if (vco < vcomin) 517414c4531SDave Airlie continue; 5189830605dSDave Airlie if (vco > vcomax) 519414c4531SDave Airlie continue; 5209830605dSDave Airlie computed = vco / (m_div_val[testm] * (testo + 1)); 521414c4531SDave Airlie if (computed > clock) 522414c4531SDave Airlie tmpdelta = computed - clock; 523414c4531SDave Airlie else 524414c4531SDave Airlie tmpdelta = clock - computed; 525414c4531SDave Airlie if (tmpdelta < delta) { 526414c4531SDave Airlie delta = tmpdelta; 527414c4531SDave Airlie m = testm | (testo << 3); 528414c4531SDave Airlie n = testn; 529414c4531SDave Airlie p = testr | (testr << 3); 530414c4531SDave Airlie } 531414c4531SDave Airlie } 532414c4531SDave Airlie } 533414c4531SDave Airlie } 534414c4531SDave Airlie } 535414c4531SDave Airlie 536414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 537414c4531SDave Airlie tmp = RREG8(DAC_DATA); 538414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 539fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 540414c4531SDave Airlie 541414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_REMHEADCTL); 542414c4531SDave Airlie tmp = RREG8(DAC_DATA); 543414c4531SDave Airlie tmp |= MGA1064_REMHEADCTL_CLKDIS; 544fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 545414c4531SDave Airlie 546414c4531SDave Airlie tmp = RREG8(MGAREG_MEM_MISC_READ); 547414c4531SDave Airlie tmp |= (0x3<<2) | 0xc0; 548414c4531SDave Airlie WREG8(MGAREG_MEM_MISC_WRITE, tmp); 549414c4531SDave Airlie 550414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 551414c4531SDave Airlie tmp = RREG8(DAC_DATA); 552414c4531SDave Airlie tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 553414c4531SDave Airlie tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 554fb70a669SChristopher Harvey WREG8(DAC_DATA, tmp); 555414c4531SDave Airlie 556414c4531SDave Airlie udelay(500); 557414c4531SDave Airlie 558414c4531SDave Airlie WREG_DAC(MGA1064_ER_PIX_PLLC_N, n); 559414c4531SDave Airlie WREG_DAC(MGA1064_ER_PIX_PLLC_M, m); 560414c4531SDave Airlie WREG_DAC(MGA1064_ER_PIX_PLLC_P, p); 561414c4531SDave Airlie 562414c4531SDave Airlie udelay(50); 563414c4531SDave Airlie 564414c4531SDave Airlie return 0; 565414c4531SDave Airlie } 566414c4531SDave Airlie 567414c4531SDave Airlie static int mga_crtc_set_plls(struct mga_device *mdev, long clock) 568414c4531SDave Airlie { 569414c4531SDave Airlie switch(mdev->type) { 570414c4531SDave Airlie case G200_SE_A: 571414c4531SDave Airlie case G200_SE_B: 572414c4531SDave Airlie return mga_g200se_set_plls(mdev, clock); 573414c4531SDave Airlie break; 574414c4531SDave Airlie case G200_WB: 575414c4531SDave Airlie return mga_g200wb_set_plls(mdev, clock); 576414c4531SDave Airlie break; 577414c4531SDave Airlie case G200_EV: 578414c4531SDave Airlie return mga_g200ev_set_plls(mdev, clock); 579414c4531SDave Airlie break; 580414c4531SDave Airlie case G200_EH: 581414c4531SDave Airlie return mga_g200eh_set_plls(mdev, clock); 582414c4531SDave Airlie break; 583414c4531SDave Airlie case G200_ER: 584414c4531SDave Airlie return mga_g200er_set_plls(mdev, clock); 585414c4531SDave Airlie break; 586414c4531SDave Airlie } 587414c4531SDave Airlie return 0; 588414c4531SDave Airlie } 589414c4531SDave Airlie 590414c4531SDave Airlie static void mga_g200wb_prepare(struct drm_crtc *crtc) 591414c4531SDave Airlie { 592414c4531SDave Airlie struct mga_device *mdev = crtc->dev->dev_private; 593414c4531SDave Airlie u8 tmp; 594414c4531SDave Airlie int iter_max; 595414c4531SDave Airlie 596414c4531SDave Airlie /* 1- The first step is to warn the BMC of an upcoming mode change. 597414c4531SDave Airlie * We are putting the misc<0> to output.*/ 598414c4531SDave Airlie 599414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); 600414c4531SDave Airlie tmp = RREG8(DAC_DATA); 601414c4531SDave Airlie tmp |= 0x10; 602414c4531SDave Airlie WREG_DAC(MGA1064_GEN_IO_CTL, tmp); 603414c4531SDave Airlie 604414c4531SDave Airlie /* we are putting a 1 on the misc<0> line */ 605414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 606414c4531SDave Airlie tmp = RREG8(DAC_DATA); 607414c4531SDave Airlie tmp |= 0x10; 608414c4531SDave Airlie WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 609414c4531SDave Airlie 610414c4531SDave Airlie /* 2- Second step to mask and further scan request 611414c4531SDave Airlie * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) 612414c4531SDave Airlie */ 613414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_SPAREREG); 614414c4531SDave Airlie tmp = RREG8(DAC_DATA); 615414c4531SDave Airlie tmp |= 0x80; 616414c4531SDave Airlie WREG_DAC(MGA1064_SPAREREG, tmp); 617414c4531SDave Airlie 618414c4531SDave Airlie /* 3a- the third step is to verifu if there is an active scan 619414c4531SDave Airlie * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) 620414c4531SDave Airlie */ 621414c4531SDave Airlie iter_max = 300; 622414c4531SDave Airlie while (!(tmp & 0x1) && iter_max) { 623414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_SPAREREG); 624414c4531SDave Airlie tmp = RREG8(DAC_DATA); 625414c4531SDave Airlie udelay(1000); 626414c4531SDave Airlie iter_max--; 627414c4531SDave Airlie } 628414c4531SDave Airlie 629414c4531SDave Airlie /* 3b- this step occurs only if the remove is actually scanning 630414c4531SDave Airlie * we are waiting for the end of the frame which is a 1 on 631414c4531SDave Airlie * remvsyncsts (XSPAREREG<1>) 632414c4531SDave Airlie */ 633414c4531SDave Airlie if (iter_max) { 634414c4531SDave Airlie iter_max = 300; 635414c4531SDave Airlie while ((tmp & 0x2) && iter_max) { 636414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_SPAREREG); 637414c4531SDave Airlie tmp = RREG8(DAC_DATA); 638414c4531SDave Airlie udelay(1000); 639414c4531SDave Airlie iter_max--; 640414c4531SDave Airlie } 641414c4531SDave Airlie } 642414c4531SDave Airlie } 643414c4531SDave Airlie 644414c4531SDave Airlie static void mga_g200wb_commit(struct drm_crtc *crtc) 645414c4531SDave Airlie { 646414c4531SDave Airlie u8 tmp; 647414c4531SDave Airlie struct mga_device *mdev = crtc->dev->dev_private; 648414c4531SDave Airlie 649414c4531SDave Airlie /* 1- The first step is to ensure that the vrsten and hrsten are set */ 650414c4531SDave Airlie WREG8(MGAREG_CRTCEXT_INDEX, 1); 651414c4531SDave Airlie tmp = RREG8(MGAREG_CRTCEXT_DATA); 652414c4531SDave Airlie WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); 653414c4531SDave Airlie 654414c4531SDave Airlie /* 2- second step is to assert the rstlvl2 */ 655414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 656414c4531SDave Airlie tmp = RREG8(DAC_DATA); 657414c4531SDave Airlie tmp |= 0x8; 658414c4531SDave Airlie WREG8(DAC_DATA, tmp); 659414c4531SDave Airlie 660414c4531SDave Airlie /* wait 10 us */ 661414c4531SDave Airlie udelay(10); 662414c4531SDave Airlie 663414c4531SDave Airlie /* 3- deassert rstlvl2 */ 664414c4531SDave Airlie tmp &= ~0x08; 665414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); 666414c4531SDave Airlie WREG8(DAC_DATA, tmp); 667414c4531SDave Airlie 668414c4531SDave Airlie /* 4- remove mask of scan request */ 669414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_SPAREREG); 670414c4531SDave Airlie tmp = RREG8(DAC_DATA); 671414c4531SDave Airlie tmp &= ~0x80; 672414c4531SDave Airlie WREG8(DAC_DATA, tmp); 673414c4531SDave Airlie 674414c4531SDave Airlie /* 5- put back a 0 on the misc<0> line */ 675414c4531SDave Airlie WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); 676414c4531SDave Airlie tmp = RREG8(DAC_DATA); 677414c4531SDave Airlie tmp &= ~0x10; 678414c4531SDave Airlie WREG_DAC(MGA1064_GEN_IO_DATA, tmp); 679414c4531SDave Airlie } 680414c4531SDave Airlie 6819f1d0366SChristopher Harvey /* 6829f1d0366SChristopher Harvey This is how the framebuffer base address is stored in g200 cards: 6839f1d0366SChristopher Harvey * Assume @offset is the gpu_addr variable of the framebuffer object 6849f1d0366SChristopher Harvey * Then addr is the number of _pixels_ (not bytes) from the start of 6859f1d0366SChristopher Harvey VRAM to the first pixel we want to display. (divided by 2 for 32bit 6869f1d0366SChristopher Harvey framebuffers) 6879f1d0366SChristopher Harvey * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 6889f1d0366SChristopher Harvey addr<20> -> CRTCEXT0<6> 6899f1d0366SChristopher Harvey addr<19-16> -> CRTCEXT0<3-0> 6909f1d0366SChristopher Harvey addr<15-8> -> CRTCC<7-0> 6919f1d0366SChristopher Harvey addr<7-0> -> CRTCD<7-0> 6929f1d0366SChristopher Harvey CRTCEXT0 has to be programmed last to trigger an update and make the 6939f1d0366SChristopher Harvey new addr variable take effect. 6949f1d0366SChristopher Harvey */ 695080fd6b5SRashika static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset) 696414c4531SDave Airlie { 697414c4531SDave Airlie struct mga_device *mdev = crtc->dev->dev_private; 698414c4531SDave Airlie u32 addr; 699414c4531SDave Airlie int count; 7009f1d0366SChristopher Harvey u8 crtcext0; 701414c4531SDave Airlie 702414c4531SDave Airlie while (RREG8(0x1fda) & 0x08); 703414c4531SDave Airlie while (!(RREG8(0x1fda) & 0x08)); 704414c4531SDave Airlie 705414c4531SDave Airlie count = RREG8(MGAREG_VCOUNT) + 2; 706414c4531SDave Airlie while (RREG8(MGAREG_VCOUNT) < count); 707414c4531SDave Airlie 7089f1d0366SChristopher Harvey WREG8(MGAREG_CRTCEXT_INDEX, 0); 7099f1d0366SChristopher Harvey crtcext0 = RREG8(MGAREG_CRTCEXT_DATA); 7109f1d0366SChristopher Harvey crtcext0 &= 0xB0; 7119f1d0366SChristopher Harvey addr = offset / 8; 7129f1d0366SChristopher Harvey /* Can't store addresses any higher than that... 7139f1d0366SChristopher Harvey but we also don't have more than 16MB of memory, so it should be fine. */ 7149f1d0366SChristopher Harvey WARN_ON(addr > 0x1fffff); 7159f1d0366SChristopher Harvey crtcext0 |= (!!(addr & (1<<20)))<<6; 716414c4531SDave Airlie WREG_CRT(0x0d, (u8)(addr & 0xff)); 717414c4531SDave Airlie WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff); 7189f1d0366SChristopher Harvey WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0); 719414c4531SDave Airlie } 720414c4531SDave Airlie 721414c4531SDave Airlie 722414c4531SDave Airlie /* ast is different - we will force move buffers out of VRAM */ 723414c4531SDave Airlie static int mga_crtc_do_set_base(struct drm_crtc *crtc, 724414c4531SDave Airlie struct drm_framebuffer *fb, 725414c4531SDave Airlie int x, int y, int atomic) 726414c4531SDave Airlie { 727414c4531SDave Airlie struct mga_device *mdev = crtc->dev->dev_private; 728414c4531SDave Airlie struct drm_gem_object *obj; 729414c4531SDave Airlie struct mga_framebuffer *mga_fb; 730414c4531SDave Airlie struct mgag200_bo *bo; 731414c4531SDave Airlie int ret; 732414c4531SDave Airlie u64 gpu_addr; 733414c4531SDave Airlie 734414c4531SDave Airlie /* push the previous fb to system ram */ 735414c4531SDave Airlie if (!atomic && fb) { 736414c4531SDave Airlie mga_fb = to_mga_framebuffer(fb); 737414c4531SDave Airlie obj = mga_fb->obj; 738414c4531SDave Airlie bo = gem_to_mga_bo(obj); 739414c4531SDave Airlie ret = mgag200_bo_reserve(bo, false); 740414c4531SDave Airlie if (ret) 741414c4531SDave Airlie return ret; 742414c4531SDave Airlie mgag200_bo_push_sysram(bo); 743414c4531SDave Airlie mgag200_bo_unreserve(bo); 744414c4531SDave Airlie } 745414c4531SDave Airlie 746f4510a27SMatt Roper mga_fb = to_mga_framebuffer(crtc->primary->fb); 747414c4531SDave Airlie obj = mga_fb->obj; 748414c4531SDave Airlie bo = gem_to_mga_bo(obj); 749414c4531SDave Airlie 750414c4531SDave Airlie ret = mgag200_bo_reserve(bo, false); 751414c4531SDave Airlie if (ret) 752414c4531SDave Airlie return ret; 753414c4531SDave Airlie 754414c4531SDave Airlie ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); 755414c4531SDave Airlie if (ret) { 756414c4531SDave Airlie mgag200_bo_unreserve(bo); 757414c4531SDave Airlie return ret; 758414c4531SDave Airlie } 759414c4531SDave Airlie 760414c4531SDave Airlie if (&mdev->mfbdev->mfb == mga_fb) { 761414c4531SDave Airlie /* if pushing console in kmap it */ 762414c4531SDave Airlie ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); 763414c4531SDave Airlie if (ret) 764414c4531SDave Airlie DRM_ERROR("failed to kmap fbcon\n"); 765414c4531SDave Airlie 766414c4531SDave Airlie } 767414c4531SDave Airlie mgag200_bo_unreserve(bo); 768414c4531SDave Airlie 769414c4531SDave Airlie mga_set_start_address(crtc, (u32)gpu_addr); 770414c4531SDave Airlie 771414c4531SDave Airlie return 0; 772414c4531SDave Airlie } 773414c4531SDave Airlie 774414c4531SDave Airlie static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 775414c4531SDave Airlie struct drm_framebuffer *old_fb) 776414c4531SDave Airlie { 777414c4531SDave Airlie return mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 778414c4531SDave Airlie } 779414c4531SDave Airlie 780414c4531SDave Airlie static int mga_crtc_mode_set(struct drm_crtc *crtc, 781414c4531SDave Airlie struct drm_display_mode *mode, 782414c4531SDave Airlie struct drm_display_mode *adjusted_mode, 783414c4531SDave Airlie int x, int y, struct drm_framebuffer *old_fb) 784414c4531SDave Airlie { 785414c4531SDave Airlie struct drm_device *dev = crtc->dev; 786414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 787414c4531SDave Airlie int hdisplay, hsyncstart, hsyncend, htotal; 788414c4531SDave Airlie int vdisplay, vsyncstart, vsyncend, vtotal; 789414c4531SDave Airlie int pitch; 790414c4531SDave Airlie int option = 0, option2 = 0; 791414c4531SDave Airlie int i; 792414c4531SDave Airlie unsigned char misc = 0; 793414c4531SDave Airlie unsigned char ext_vga[6]; 794414c4531SDave Airlie u8 bppshift; 795414c4531SDave Airlie 796414c4531SDave Airlie static unsigned char dacvalue[] = { 797414c4531SDave Airlie /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, 798414c4531SDave Airlie /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, 799414c4531SDave Airlie /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, 800414c4531SDave Airlie /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, 801414c4531SDave Airlie /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 802414c4531SDave Airlie /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, 803414c4531SDave Airlie /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, 804414c4531SDave Airlie /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, 805414c4531SDave Airlie /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, 806414c4531SDave Airlie /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 807414c4531SDave Airlie }; 808414c4531SDave Airlie 809f4510a27SMatt Roper bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1]; 810414c4531SDave Airlie 811414c4531SDave Airlie switch (mdev->type) { 812414c4531SDave Airlie case G200_SE_A: 813414c4531SDave Airlie case G200_SE_B: 814414c4531SDave Airlie dacvalue[MGA1064_VREF_CTL] = 0x03; 815414c4531SDave Airlie dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 816414c4531SDave Airlie dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | 817414c4531SDave Airlie MGA1064_MISC_CTL_VGA8 | 818414c4531SDave Airlie MGA1064_MISC_CTL_DAC_RAM_CS; 819414c4531SDave Airlie if (mdev->has_sdram) 820414c4531SDave Airlie option = 0x40049120; 821414c4531SDave Airlie else 822414c4531SDave Airlie option = 0x4004d120; 823414c4531SDave Airlie option2 = 0x00008000; 824414c4531SDave Airlie break; 825414c4531SDave Airlie case G200_WB: 826414c4531SDave Airlie dacvalue[MGA1064_VREF_CTL] = 0x07; 827414c4531SDave Airlie option = 0x41049120; 828414c4531SDave Airlie option2 = 0x0000b000; 829414c4531SDave Airlie break; 830414c4531SDave Airlie case G200_EV: 831414c4531SDave Airlie dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; 832414c4531SDave Airlie dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 833414c4531SDave Airlie MGA1064_MISC_CTL_DAC_RAM_CS; 834414c4531SDave Airlie option = 0x00000120; 835414c4531SDave Airlie option2 = 0x0000b000; 836414c4531SDave Airlie break; 837414c4531SDave Airlie case G200_EH: 838414c4531SDave Airlie dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | 839414c4531SDave Airlie MGA1064_MISC_CTL_DAC_RAM_CS; 840414c4531SDave Airlie option = 0x00000120; 841414c4531SDave Airlie option2 = 0x0000b000; 842414c4531SDave Airlie break; 843414c4531SDave Airlie case G200_ER: 844414c4531SDave Airlie break; 845414c4531SDave Airlie } 846414c4531SDave Airlie 847f4510a27SMatt Roper switch (crtc->primary->fb->bits_per_pixel) { 848414c4531SDave Airlie case 8: 849414c4531SDave Airlie dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits; 850414c4531SDave Airlie break; 851414c4531SDave Airlie case 16: 852f4510a27SMatt Roper if (crtc->primary->fb->depth == 15) 853414c4531SDave Airlie dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits; 854414c4531SDave Airlie else 855414c4531SDave Airlie dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits; 856414c4531SDave Airlie break; 857414c4531SDave Airlie case 24: 858414c4531SDave Airlie dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits; 859414c4531SDave Airlie break; 860414c4531SDave Airlie case 32: 861414c4531SDave Airlie dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits; 862414c4531SDave Airlie break; 863414c4531SDave Airlie } 864414c4531SDave Airlie 865414c4531SDave Airlie if (mode->flags & DRM_MODE_FLAG_NHSYNC) 866414c4531SDave Airlie misc |= 0x40; 867414c4531SDave Airlie if (mode->flags & DRM_MODE_FLAG_NVSYNC) 868414c4531SDave Airlie misc |= 0x80; 869414c4531SDave Airlie 870414c4531SDave Airlie 871414c4531SDave Airlie for (i = 0; i < sizeof(dacvalue); i++) { 8729d8aa55fSChristopher Harvey if ((i <= 0x17) || 873414c4531SDave Airlie (i == 0x1b) || 874414c4531SDave Airlie (i == 0x1c) || 875414c4531SDave Airlie ((i >= 0x1f) && (i <= 0x29)) || 876414c4531SDave Airlie ((i >= 0x30) && (i <= 0x37))) 877414c4531SDave Airlie continue; 878414c4531SDave Airlie if (IS_G200_SE(mdev) && 879414c4531SDave Airlie ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) 880414c4531SDave Airlie continue; 881414c4531SDave Airlie if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) && 882414c4531SDave Airlie (i >= 0x44) && (i <= 0x4e)) 883414c4531SDave Airlie continue; 884414c4531SDave Airlie 885414c4531SDave Airlie WREG_DAC(i, dacvalue[i]); 886414c4531SDave Airlie } 887414c4531SDave Airlie 8881812a3dbSChristopher Harvey if (mdev->type == G200_ER) 8891812a3dbSChristopher Harvey WREG_DAC(0x90, 0); 890414c4531SDave Airlie 891414c4531SDave Airlie if (option) 892414c4531SDave Airlie pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); 893414c4531SDave Airlie if (option2) 894414c4531SDave Airlie pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); 895414c4531SDave Airlie 896414c4531SDave Airlie WREG_SEQ(2, 0xf); 897414c4531SDave Airlie WREG_SEQ(3, 0); 898414c4531SDave Airlie WREG_SEQ(4, 0xe); 899414c4531SDave Airlie 900f4510a27SMatt Roper pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8); 901f4510a27SMatt Roper if (crtc->primary->fb->bits_per_pixel == 24) 902da558398STakashi Iwai pitch = (pitch * 3) >> (4 - bppshift); 903414c4531SDave Airlie else 904414c4531SDave Airlie pitch = pitch >> (4 - bppshift); 905414c4531SDave Airlie 906414c4531SDave Airlie hdisplay = mode->hdisplay / 8 - 1; 907414c4531SDave Airlie hsyncstart = mode->hsync_start / 8 - 1; 908414c4531SDave Airlie hsyncend = mode->hsync_end / 8 - 1; 909414c4531SDave Airlie htotal = mode->htotal / 8 - 1; 910414c4531SDave Airlie 911414c4531SDave Airlie /* Work around hardware quirk */ 912414c4531SDave Airlie if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 913414c4531SDave Airlie htotal++; 914414c4531SDave Airlie 915414c4531SDave Airlie vdisplay = mode->vdisplay - 1; 916414c4531SDave Airlie vsyncstart = mode->vsync_start - 1; 917414c4531SDave Airlie vsyncend = mode->vsync_end - 1; 918414c4531SDave Airlie vtotal = mode->vtotal - 2; 919414c4531SDave Airlie 920414c4531SDave Airlie WREG_GFX(0, 0); 921414c4531SDave Airlie WREG_GFX(1, 0); 922414c4531SDave Airlie WREG_GFX(2, 0); 923414c4531SDave Airlie WREG_GFX(3, 0); 924414c4531SDave Airlie WREG_GFX(4, 0); 925414c4531SDave Airlie WREG_GFX(5, 0x40); 926414c4531SDave Airlie WREG_GFX(6, 0x5); 927414c4531SDave Airlie WREG_GFX(7, 0xf); 928414c4531SDave Airlie WREG_GFX(8, 0xf); 929414c4531SDave Airlie 930414c4531SDave Airlie WREG_CRT(0, htotal - 4); 931414c4531SDave Airlie WREG_CRT(1, hdisplay); 932414c4531SDave Airlie WREG_CRT(2, hdisplay); 933414c4531SDave Airlie WREG_CRT(3, (htotal & 0x1F) | 0x80); 934414c4531SDave Airlie WREG_CRT(4, hsyncstart); 935414c4531SDave Airlie WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); 936414c4531SDave Airlie WREG_CRT(6, vtotal & 0xFF); 937414c4531SDave Airlie WREG_CRT(7, ((vtotal & 0x100) >> 8) | 938414c4531SDave Airlie ((vdisplay & 0x100) >> 7) | 939414c4531SDave Airlie ((vsyncstart & 0x100) >> 6) | 940414c4531SDave Airlie ((vdisplay & 0x100) >> 5) | 941414c4531SDave Airlie ((vdisplay & 0x100) >> 4) | /* linecomp */ 942414c4531SDave Airlie ((vtotal & 0x200) >> 4)| 943414c4531SDave Airlie ((vdisplay & 0x200) >> 3) | 944414c4531SDave Airlie ((vsyncstart & 0x200) >> 2)); 945414c4531SDave Airlie WREG_CRT(9, ((vdisplay & 0x200) >> 4) | 946414c4531SDave Airlie ((vdisplay & 0x200) >> 3)); 947414c4531SDave Airlie WREG_CRT(10, 0); 948414c4531SDave Airlie WREG_CRT(11, 0); 949414c4531SDave Airlie WREG_CRT(12, 0); 950414c4531SDave Airlie WREG_CRT(13, 0); 951414c4531SDave Airlie WREG_CRT(14, 0); 952414c4531SDave Airlie WREG_CRT(15, 0); 953414c4531SDave Airlie WREG_CRT(16, vsyncstart & 0xFF); 954414c4531SDave Airlie WREG_CRT(17, (vsyncend & 0x0F) | 0x20); 955414c4531SDave Airlie WREG_CRT(18, vdisplay & 0xFF); 956414c4531SDave Airlie WREG_CRT(19, pitch & 0xFF); 957414c4531SDave Airlie WREG_CRT(20, 0); 958414c4531SDave Airlie WREG_CRT(21, vdisplay & 0xFF); 959414c4531SDave Airlie WREG_CRT(22, (vtotal + 1) & 0xFF); 960414c4531SDave Airlie WREG_CRT(23, 0xc3); 961414c4531SDave Airlie WREG_CRT(24, vdisplay & 0xFF); 962414c4531SDave Airlie 963414c4531SDave Airlie ext_vga[0] = 0; 964414c4531SDave Airlie ext_vga[5] = 0; 965414c4531SDave Airlie 966414c4531SDave Airlie /* TODO interlace */ 967414c4531SDave Airlie 968414c4531SDave Airlie ext_vga[0] |= (pitch & 0x300) >> 4; 969414c4531SDave Airlie ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | 970414c4531SDave Airlie ((hdisplay & 0x100) >> 7) | 971414c4531SDave Airlie ((hsyncstart & 0x100) >> 6) | 972414c4531SDave Airlie (htotal & 0x40); 973414c4531SDave Airlie ext_vga[2] = ((vtotal & 0xc00) >> 10) | 974414c4531SDave Airlie ((vdisplay & 0x400) >> 8) | 975414c4531SDave Airlie ((vdisplay & 0xc00) >> 7) | 976414c4531SDave Airlie ((vsyncstart & 0xc00) >> 5) | 977414c4531SDave Airlie ((vdisplay & 0x400) >> 3); 978f4510a27SMatt Roper if (crtc->primary->fb->bits_per_pixel == 24) 979414c4531SDave Airlie ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80; 980414c4531SDave Airlie else 981414c4531SDave Airlie ext_vga[3] = ((1 << bppshift) - 1) | 0x80; 982414c4531SDave Airlie ext_vga[4] = 0; 983414c4531SDave Airlie if (mdev->type == G200_WB) 984414c4531SDave Airlie ext_vga[1] |= 0x88; 985414c4531SDave Airlie 986414c4531SDave Airlie /* Set pixel clocks */ 987414c4531SDave Airlie misc = 0x2d; 988414c4531SDave Airlie WREG8(MGA_MISC_OUT, misc); 989414c4531SDave Airlie 990414c4531SDave Airlie mga_crtc_set_plls(mdev, mode->clock); 991414c4531SDave Airlie 992414c4531SDave Airlie for (i = 0; i < 6; i++) { 993414c4531SDave Airlie WREG_ECRT(i, ext_vga[i]); 994414c4531SDave Airlie } 995414c4531SDave Airlie 996414c4531SDave Airlie if (mdev->type == G200_ER) 9971812a3dbSChristopher Harvey WREG_ECRT(0x24, 0x5); 998414c4531SDave Airlie 999414c4531SDave Airlie if (mdev->type == G200_EV) { 1000414c4531SDave Airlie WREG_ECRT(6, 0); 1001414c4531SDave Airlie } 1002414c4531SDave Airlie 1003414c4531SDave Airlie WREG_ECRT(0, ext_vga[0]); 1004414c4531SDave Airlie /* Enable mga pixel clock */ 1005414c4531SDave Airlie misc = 0x2d; 1006414c4531SDave Airlie 1007414c4531SDave Airlie WREG8(MGA_MISC_OUT, misc); 1008414c4531SDave Airlie 1009414c4531SDave Airlie if (adjusted_mode) 1010414c4531SDave Airlie memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode)); 1011414c4531SDave Airlie 1012414c4531SDave Airlie mga_crtc_do_set_base(crtc, old_fb, x, y, 0); 1013414c4531SDave Airlie 1014414c4531SDave Airlie /* reset tagfifo */ 1015414c4531SDave Airlie if (mdev->type == G200_ER) { 1016414c4531SDave Airlie u32 mem_ctl = RREG32(MGAREG_MEMCTL); 1017414c4531SDave Airlie u8 seq1; 1018414c4531SDave Airlie 1019414c4531SDave Airlie /* screen off */ 1020414c4531SDave Airlie WREG8(MGAREG_SEQ_INDEX, 0x01); 1021414c4531SDave Airlie seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20; 1022414c4531SDave Airlie WREG8(MGAREG_SEQ_DATA, seq1); 1023414c4531SDave Airlie 1024414c4531SDave Airlie WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); 1025414c4531SDave Airlie udelay(1000); 1026414c4531SDave Airlie WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); 1027414c4531SDave Airlie 1028414c4531SDave Airlie WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20); 1029414c4531SDave Airlie } 1030414c4531SDave Airlie 1031414c4531SDave Airlie 1032414c4531SDave Airlie if (IS_G200_SE(mdev)) { 1033abbee623SJulia Lemire if (mdev->unique_rev_id >= 0x02) { 1034414c4531SDave Airlie u8 hi_pri_lvl; 1035414c4531SDave Airlie u32 bpp; 1036414c4531SDave Airlie u32 mb; 1037414c4531SDave Airlie 1038f4510a27SMatt Roper if (crtc->primary->fb->bits_per_pixel > 16) 1039414c4531SDave Airlie bpp = 32; 1040f4510a27SMatt Roper else if (crtc->primary->fb->bits_per_pixel > 8) 1041414c4531SDave Airlie bpp = 16; 1042414c4531SDave Airlie else 1043414c4531SDave Airlie bpp = 8; 1044414c4531SDave Airlie 1045414c4531SDave Airlie mb = (mode->clock * bpp) / 1000; 1046414c4531SDave Airlie if (mb > 3100) 1047414c4531SDave Airlie hi_pri_lvl = 0; 1048414c4531SDave Airlie else if (mb > 2600) 1049414c4531SDave Airlie hi_pri_lvl = 1; 1050414c4531SDave Airlie else if (mb > 1900) 1051414c4531SDave Airlie hi_pri_lvl = 2; 1052414c4531SDave Airlie else if (mb > 1160) 1053414c4531SDave Airlie hi_pri_lvl = 3; 1054414c4531SDave Airlie else if (mb > 440) 1055414c4531SDave Airlie hi_pri_lvl = 4; 1056414c4531SDave Airlie else 1057414c4531SDave Airlie hi_pri_lvl = 5; 1058414c4531SDave Airlie 105991f8f105SChristopher Harvey WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 106091f8f105SChristopher Harvey WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl); 1061414c4531SDave Airlie } else { 106291f8f105SChristopher Harvey WREG8(MGAREG_CRTCEXT_INDEX, 0x06); 1063abbee623SJulia Lemire if (mdev->unique_rev_id >= 0x01) 106491f8f105SChristopher Harvey WREG8(MGAREG_CRTCEXT_DATA, 0x03); 1065414c4531SDave Airlie else 106691f8f105SChristopher Harvey WREG8(MGAREG_CRTCEXT_DATA, 0x04); 1067414c4531SDave Airlie } 1068414c4531SDave Airlie } 1069414c4531SDave Airlie return 0; 1070414c4531SDave Airlie } 1071414c4531SDave Airlie 1072414c4531SDave Airlie #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */ 1073414c4531SDave Airlie static int mga_suspend(struct drm_crtc *crtc) 1074414c4531SDave Airlie { 1075414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1076414c4531SDave Airlie struct drm_device *dev = crtc->dev; 1077414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 1078414c4531SDave Airlie struct pci_dev *pdev = dev->pdev; 1079414c4531SDave Airlie int option; 1080414c4531SDave Airlie 1081414c4531SDave Airlie if (mdev->suspended) 1082414c4531SDave Airlie return 0; 1083414c4531SDave Airlie 1084414c4531SDave Airlie WREG_SEQ(1, 0x20); 1085414c4531SDave Airlie WREG_ECRT(1, 0x30); 1086414c4531SDave Airlie /* Disable the pixel clock */ 1087414c4531SDave Airlie WREG_DAC(0x1a, 0x05); 1088414c4531SDave Airlie /* Power down the DAC */ 1089414c4531SDave Airlie WREG_DAC(0x1e, 0x18); 1090414c4531SDave Airlie /* Power down the pixel PLL */ 1091414c4531SDave Airlie WREG_DAC(0x1a, 0x0d); 1092414c4531SDave Airlie 1093414c4531SDave Airlie /* Disable PLLs and clocks */ 1094414c4531SDave Airlie pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1095414c4531SDave Airlie option &= ~(0x1F8024); 1096414c4531SDave Airlie pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1097414c4531SDave Airlie pci_set_power_state(pdev, PCI_D3hot); 1098414c4531SDave Airlie pci_disable_device(pdev); 1099414c4531SDave Airlie 1100414c4531SDave Airlie mdev->suspended = true; 1101414c4531SDave Airlie 1102414c4531SDave Airlie return 0; 1103414c4531SDave Airlie } 1104414c4531SDave Airlie 1105414c4531SDave Airlie static int mga_resume(struct drm_crtc *crtc) 1106414c4531SDave Airlie { 1107414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1108414c4531SDave Airlie struct drm_device *dev = crtc->dev; 1109414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 1110414c4531SDave Airlie struct pci_dev *pdev = dev->pdev; 1111414c4531SDave Airlie int option; 1112414c4531SDave Airlie 1113414c4531SDave Airlie if (!mdev->suspended) 1114414c4531SDave Airlie return 0; 1115414c4531SDave Airlie 1116414c4531SDave Airlie pci_set_power_state(pdev, PCI_D0); 1117414c4531SDave Airlie pci_enable_device(pdev); 1118414c4531SDave Airlie 1119414c4531SDave Airlie /* Disable sysclk */ 1120414c4531SDave Airlie pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); 1121414c4531SDave Airlie option &= ~(0x4); 1122414c4531SDave Airlie pci_write_config_dword(pdev, PCI_MGA_OPTION, option); 1123414c4531SDave Airlie 1124414c4531SDave Airlie mdev->suspended = false; 1125414c4531SDave Airlie 1126414c4531SDave Airlie return 0; 1127414c4531SDave Airlie } 1128414c4531SDave Airlie 1129414c4531SDave Airlie #endif 1130414c4531SDave Airlie 1131414c4531SDave Airlie static void mga_crtc_dpms(struct drm_crtc *crtc, int mode) 1132414c4531SDave Airlie { 1133414c4531SDave Airlie struct drm_device *dev = crtc->dev; 1134414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 1135414c4531SDave Airlie u8 seq1 = 0, crtcext1 = 0; 1136414c4531SDave Airlie 1137414c4531SDave Airlie switch (mode) { 1138414c4531SDave Airlie case DRM_MODE_DPMS_ON: 1139414c4531SDave Airlie seq1 = 0; 1140414c4531SDave Airlie crtcext1 = 0; 1141414c4531SDave Airlie mga_crtc_load_lut(crtc); 1142414c4531SDave Airlie break; 1143414c4531SDave Airlie case DRM_MODE_DPMS_STANDBY: 1144414c4531SDave Airlie seq1 = 0x20; 1145414c4531SDave Airlie crtcext1 = 0x10; 1146414c4531SDave Airlie break; 1147414c4531SDave Airlie case DRM_MODE_DPMS_SUSPEND: 1148414c4531SDave Airlie seq1 = 0x20; 1149414c4531SDave Airlie crtcext1 = 0x20; 1150414c4531SDave Airlie break; 1151414c4531SDave Airlie case DRM_MODE_DPMS_OFF: 1152414c4531SDave Airlie seq1 = 0x20; 1153414c4531SDave Airlie crtcext1 = 0x30; 1154414c4531SDave Airlie break; 1155414c4531SDave Airlie } 1156414c4531SDave Airlie 1157414c4531SDave Airlie #if 0 1158414c4531SDave Airlie if (mode == DRM_MODE_DPMS_OFF) { 1159414c4531SDave Airlie mga_suspend(crtc); 1160414c4531SDave Airlie } 1161414c4531SDave Airlie #endif 1162414c4531SDave Airlie WREG8(MGAREG_SEQ_INDEX, 0x01); 1163414c4531SDave Airlie seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20; 1164414c4531SDave Airlie mga_wait_vsync(mdev); 1165414c4531SDave Airlie mga_wait_busy(mdev); 1166414c4531SDave Airlie WREG8(MGAREG_SEQ_DATA, seq1); 1167414c4531SDave Airlie msleep(20); 1168414c4531SDave Airlie WREG8(MGAREG_CRTCEXT_INDEX, 0x01); 1169414c4531SDave Airlie crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30; 1170414c4531SDave Airlie WREG8(MGAREG_CRTCEXT_DATA, crtcext1); 1171414c4531SDave Airlie 1172414c4531SDave Airlie #if 0 1173414c4531SDave Airlie if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) { 1174414c4531SDave Airlie mga_resume(crtc); 1175414c4531SDave Airlie drm_helper_resume_force_mode(dev); 1176414c4531SDave Airlie } 1177414c4531SDave Airlie #endif 1178414c4531SDave Airlie } 1179414c4531SDave Airlie 1180414c4531SDave Airlie /* 1181414c4531SDave Airlie * This is called before a mode is programmed. A typical use might be to 1182414c4531SDave Airlie * enable DPMS during the programming to avoid seeing intermediate stages, 1183414c4531SDave Airlie * but that's not relevant to us 1184414c4531SDave Airlie */ 1185414c4531SDave Airlie static void mga_crtc_prepare(struct drm_crtc *crtc) 1186414c4531SDave Airlie { 1187414c4531SDave Airlie struct drm_device *dev = crtc->dev; 1188414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 1189414c4531SDave Airlie u8 tmp; 1190414c4531SDave Airlie 1191414c4531SDave Airlie /* mga_resume(crtc);*/ 1192414c4531SDave Airlie 1193414c4531SDave Airlie WREG8(MGAREG_CRTC_INDEX, 0x11); 1194414c4531SDave Airlie tmp = RREG8(MGAREG_CRTC_DATA); 1195414c4531SDave Airlie WREG_CRT(0x11, tmp | 0x80); 1196414c4531SDave Airlie 1197414c4531SDave Airlie if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1198414c4531SDave Airlie WREG_SEQ(0, 1); 1199414c4531SDave Airlie msleep(50); 1200414c4531SDave Airlie WREG_SEQ(1, 0x20); 1201414c4531SDave Airlie msleep(20); 1202414c4531SDave Airlie } else { 1203414c4531SDave Airlie WREG8(MGAREG_SEQ_INDEX, 0x1); 1204414c4531SDave Airlie tmp = RREG8(MGAREG_SEQ_DATA); 1205414c4531SDave Airlie 1206414c4531SDave Airlie /* start sync reset */ 1207414c4531SDave Airlie WREG_SEQ(0, 1); 1208414c4531SDave Airlie WREG_SEQ(1, tmp | 0x20); 1209414c4531SDave Airlie } 1210414c4531SDave Airlie 1211414c4531SDave Airlie if (mdev->type == G200_WB) 1212414c4531SDave Airlie mga_g200wb_prepare(crtc); 1213414c4531SDave Airlie 1214414c4531SDave Airlie WREG_CRT(17, 0); 1215414c4531SDave Airlie } 1216414c4531SDave Airlie 1217414c4531SDave Airlie /* 1218414c4531SDave Airlie * This is called after a mode is programmed. It should reverse anything done 1219414c4531SDave Airlie * by the prepare function 1220414c4531SDave Airlie */ 1221414c4531SDave Airlie static void mga_crtc_commit(struct drm_crtc *crtc) 1222414c4531SDave Airlie { 1223414c4531SDave Airlie struct drm_device *dev = crtc->dev; 1224414c4531SDave Airlie struct mga_device *mdev = dev->dev_private; 1225*d584ff82SJani Nikula const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 1226414c4531SDave Airlie u8 tmp; 1227414c4531SDave Airlie 1228414c4531SDave Airlie if (mdev->type == G200_WB) 1229414c4531SDave Airlie mga_g200wb_commit(crtc); 1230414c4531SDave Airlie 1231414c4531SDave Airlie if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { 1232414c4531SDave Airlie msleep(50); 1233414c4531SDave Airlie WREG_SEQ(1, 0x0); 1234414c4531SDave Airlie msleep(20); 1235414c4531SDave Airlie WREG_SEQ(0, 0x3); 1236414c4531SDave Airlie } else { 1237414c4531SDave Airlie WREG8(MGAREG_SEQ_INDEX, 0x1); 1238414c4531SDave Airlie tmp = RREG8(MGAREG_SEQ_DATA); 1239414c4531SDave Airlie 1240414c4531SDave Airlie tmp &= ~0x20; 1241414c4531SDave Airlie WREG_SEQ(0x1, tmp); 1242414c4531SDave Airlie WREG_SEQ(0, 3); 1243414c4531SDave Airlie } 1244414c4531SDave Airlie crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 1245414c4531SDave Airlie } 1246414c4531SDave Airlie 1247414c4531SDave Airlie /* 1248414c4531SDave Airlie * The core can pass us a set of gamma values to program. We actually only 1249414c4531SDave Airlie * use this for 8-bit mode so can't perform smooth fades on deeper modes, 1250414c4531SDave Airlie * but it's a requirement that we provide the function 1251414c4531SDave Airlie */ 1252414c4531SDave Airlie static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 1253414c4531SDave Airlie u16 *blue, uint32_t start, uint32_t size) 1254414c4531SDave Airlie { 1255414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1256414c4531SDave Airlie int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size; 1257414c4531SDave Airlie int i; 1258414c4531SDave Airlie 1259414c4531SDave Airlie for (i = start; i < end; i++) { 1260414c4531SDave Airlie mga_crtc->lut_r[i] = red[i] >> 8; 1261414c4531SDave Airlie mga_crtc->lut_g[i] = green[i] >> 8; 1262414c4531SDave Airlie mga_crtc->lut_b[i] = blue[i] >> 8; 1263414c4531SDave Airlie } 1264414c4531SDave Airlie mga_crtc_load_lut(crtc); 1265414c4531SDave Airlie } 1266414c4531SDave Airlie 1267414c4531SDave Airlie /* Simple cleanup function */ 1268414c4531SDave Airlie static void mga_crtc_destroy(struct drm_crtc *crtc) 1269414c4531SDave Airlie { 1270414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1271414c4531SDave Airlie 1272414c4531SDave Airlie drm_crtc_cleanup(crtc); 1273414c4531SDave Airlie kfree(mga_crtc); 1274414c4531SDave Airlie } 1275414c4531SDave Airlie 127664c29076SEgbert Eich static void mga_crtc_disable(struct drm_crtc *crtc) 127764c29076SEgbert Eich { 127864c29076SEgbert Eich int ret; 127964c29076SEgbert Eich DRM_DEBUG_KMS("\n"); 128064c29076SEgbert Eich mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1281f4510a27SMatt Roper if (crtc->primary->fb) { 1282f4510a27SMatt Roper struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb); 128364c29076SEgbert Eich struct drm_gem_object *obj = mga_fb->obj; 128464c29076SEgbert Eich struct mgag200_bo *bo = gem_to_mga_bo(obj); 128564c29076SEgbert Eich ret = mgag200_bo_reserve(bo, false); 128664c29076SEgbert Eich if (ret) 128764c29076SEgbert Eich return; 128864c29076SEgbert Eich mgag200_bo_push_sysram(bo); 128964c29076SEgbert Eich mgag200_bo_unreserve(bo); 129064c29076SEgbert Eich } 1291f4510a27SMatt Roper crtc->primary->fb = NULL; 129264c29076SEgbert Eich } 129364c29076SEgbert Eich 1294414c4531SDave Airlie /* These provide the minimum set of functions required to handle a CRTC */ 1295414c4531SDave Airlie static const struct drm_crtc_funcs mga_crtc_funcs = { 1296a080db9fSChristopher Harvey .cursor_set = mga_crtc_cursor_set, 1297a080db9fSChristopher Harvey .cursor_move = mga_crtc_cursor_move, 1298414c4531SDave Airlie .gamma_set = mga_crtc_gamma_set, 1299414c4531SDave Airlie .set_config = drm_crtc_helper_set_config, 1300414c4531SDave Airlie .destroy = mga_crtc_destroy, 1301414c4531SDave Airlie }; 1302414c4531SDave Airlie 1303414c4531SDave Airlie static const struct drm_crtc_helper_funcs mga_helper_funcs = { 130464c29076SEgbert Eich .disable = mga_crtc_disable, 1305414c4531SDave Airlie .dpms = mga_crtc_dpms, 1306414c4531SDave Airlie .mode_fixup = mga_crtc_mode_fixup, 1307414c4531SDave Airlie .mode_set = mga_crtc_mode_set, 1308414c4531SDave Airlie .mode_set_base = mga_crtc_mode_set_base, 1309414c4531SDave Airlie .prepare = mga_crtc_prepare, 1310414c4531SDave Airlie .commit = mga_crtc_commit, 1311414c4531SDave Airlie .load_lut = mga_crtc_load_lut, 1312414c4531SDave Airlie }; 1313414c4531SDave Airlie 1314414c4531SDave Airlie /* CRTC setup */ 1315f1998fe2SChristopher Harvey static void mga_crtc_init(struct mga_device *mdev) 1316414c4531SDave Airlie { 1317414c4531SDave Airlie struct mga_crtc *mga_crtc; 1318414c4531SDave Airlie int i; 1319414c4531SDave Airlie 1320414c4531SDave Airlie mga_crtc = kzalloc(sizeof(struct mga_crtc) + 1321414c4531SDave Airlie (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)), 1322414c4531SDave Airlie GFP_KERNEL); 1323414c4531SDave Airlie 1324414c4531SDave Airlie if (mga_crtc == NULL) 1325414c4531SDave Airlie return; 1326414c4531SDave Airlie 1327f1998fe2SChristopher Harvey drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); 1328414c4531SDave Airlie 1329414c4531SDave Airlie drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); 1330414c4531SDave Airlie mdev->mode_info.crtc = mga_crtc; 1331414c4531SDave Airlie 1332414c4531SDave Airlie for (i = 0; i < MGAG200_LUT_SIZE; i++) { 1333414c4531SDave Airlie mga_crtc->lut_r[i] = i; 1334414c4531SDave Airlie mga_crtc->lut_g[i] = i; 1335414c4531SDave Airlie mga_crtc->lut_b[i] = i; 1336414c4531SDave Airlie } 1337414c4531SDave Airlie 1338414c4531SDave Airlie drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); 1339414c4531SDave Airlie } 1340414c4531SDave Airlie 1341414c4531SDave Airlie /** Sets the color ramps on behalf of fbcon */ 1342414c4531SDave Airlie void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 1343414c4531SDave Airlie u16 blue, int regno) 1344414c4531SDave Airlie { 1345414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1346414c4531SDave Airlie 1347414c4531SDave Airlie mga_crtc->lut_r[regno] = red >> 8; 1348414c4531SDave Airlie mga_crtc->lut_g[regno] = green >> 8; 1349414c4531SDave Airlie mga_crtc->lut_b[regno] = blue >> 8; 1350414c4531SDave Airlie } 1351414c4531SDave Airlie 1352414c4531SDave Airlie /** Gets the color ramps on behalf of fbcon */ 1353414c4531SDave Airlie void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 1354414c4531SDave Airlie u16 *blue, int regno) 1355414c4531SDave Airlie { 1356414c4531SDave Airlie struct mga_crtc *mga_crtc = to_mga_crtc(crtc); 1357414c4531SDave Airlie 1358414c4531SDave Airlie *red = (u16)mga_crtc->lut_r[regno] << 8; 1359414c4531SDave Airlie *green = (u16)mga_crtc->lut_g[regno] << 8; 1360414c4531SDave Airlie *blue = (u16)mga_crtc->lut_b[regno] << 8; 1361414c4531SDave Airlie } 1362414c4531SDave Airlie 1363414c4531SDave Airlie /* 1364414c4531SDave Airlie * The encoder comes after the CRTC in the output pipeline, but before 1365414c4531SDave Airlie * the connector. It's responsible for ensuring that the digital 1366414c4531SDave Airlie * stream is appropriately converted into the output format. Setup is 1367414c4531SDave Airlie * very simple in this case - all we have to do is inform qemu of the 1368414c4531SDave Airlie * colour depth in order to ensure that it displays appropriately 1369414c4531SDave Airlie */ 1370414c4531SDave Airlie 1371414c4531SDave Airlie /* 1372414c4531SDave Airlie * These functions are analagous to those in the CRTC code, but are intended 1373414c4531SDave Airlie * to handle any encoder-specific limitations 1374414c4531SDave Airlie */ 1375414c4531SDave Airlie static bool mga_encoder_mode_fixup(struct drm_encoder *encoder, 1376e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 1377414c4531SDave Airlie struct drm_display_mode *adjusted_mode) 1378414c4531SDave Airlie { 1379414c4531SDave Airlie return true; 1380414c4531SDave Airlie } 1381414c4531SDave Airlie 1382414c4531SDave Airlie static void mga_encoder_mode_set(struct drm_encoder *encoder, 1383414c4531SDave Airlie struct drm_display_mode *mode, 1384414c4531SDave Airlie struct drm_display_mode *adjusted_mode) 1385414c4531SDave Airlie { 1386414c4531SDave Airlie 1387414c4531SDave Airlie } 1388414c4531SDave Airlie 1389414c4531SDave Airlie static void mga_encoder_dpms(struct drm_encoder *encoder, int state) 1390414c4531SDave Airlie { 1391414c4531SDave Airlie return; 1392414c4531SDave Airlie } 1393414c4531SDave Airlie 1394414c4531SDave Airlie static void mga_encoder_prepare(struct drm_encoder *encoder) 1395414c4531SDave Airlie { 1396414c4531SDave Airlie } 1397414c4531SDave Airlie 1398414c4531SDave Airlie static void mga_encoder_commit(struct drm_encoder *encoder) 1399414c4531SDave Airlie { 1400414c4531SDave Airlie } 1401414c4531SDave Airlie 1402080fd6b5SRashika static void mga_encoder_destroy(struct drm_encoder *encoder) 1403414c4531SDave Airlie { 1404414c4531SDave Airlie struct mga_encoder *mga_encoder = to_mga_encoder(encoder); 1405414c4531SDave Airlie drm_encoder_cleanup(encoder); 1406414c4531SDave Airlie kfree(mga_encoder); 1407414c4531SDave Airlie } 1408414c4531SDave Airlie 1409414c4531SDave Airlie static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = { 1410414c4531SDave Airlie .dpms = mga_encoder_dpms, 1411414c4531SDave Airlie .mode_fixup = mga_encoder_mode_fixup, 1412414c4531SDave Airlie .mode_set = mga_encoder_mode_set, 1413414c4531SDave Airlie .prepare = mga_encoder_prepare, 1414414c4531SDave Airlie .commit = mga_encoder_commit, 1415414c4531SDave Airlie }; 1416414c4531SDave Airlie 1417414c4531SDave Airlie static const struct drm_encoder_funcs mga_encoder_encoder_funcs = { 1418414c4531SDave Airlie .destroy = mga_encoder_destroy, 1419414c4531SDave Airlie }; 1420414c4531SDave Airlie 1421414c4531SDave Airlie static struct drm_encoder *mga_encoder_init(struct drm_device *dev) 1422414c4531SDave Airlie { 1423414c4531SDave Airlie struct drm_encoder *encoder; 1424414c4531SDave Airlie struct mga_encoder *mga_encoder; 1425414c4531SDave Airlie 1426414c4531SDave Airlie mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL); 1427414c4531SDave Airlie if (!mga_encoder) 1428414c4531SDave Airlie return NULL; 1429414c4531SDave Airlie 1430414c4531SDave Airlie encoder = &mga_encoder->base; 1431414c4531SDave Airlie encoder->possible_crtcs = 0x1; 1432414c4531SDave Airlie 1433414c4531SDave Airlie drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs, 1434414c4531SDave Airlie DRM_MODE_ENCODER_DAC); 1435414c4531SDave Airlie drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs); 1436414c4531SDave Airlie 1437414c4531SDave Airlie return encoder; 1438414c4531SDave Airlie } 1439414c4531SDave Airlie 1440414c4531SDave Airlie 1441414c4531SDave Airlie static int mga_vga_get_modes(struct drm_connector *connector) 1442414c4531SDave Airlie { 1443414c4531SDave Airlie struct mga_connector *mga_connector = to_mga_connector(connector); 1444414c4531SDave Airlie struct edid *edid; 1445414c4531SDave Airlie int ret = 0; 1446414c4531SDave Airlie 1447414c4531SDave Airlie edid = drm_get_edid(connector, &mga_connector->i2c->adapter); 1448414c4531SDave Airlie if (edid) { 1449414c4531SDave Airlie drm_mode_connector_update_edid_property(connector, edid); 1450414c4531SDave Airlie ret = drm_add_edid_modes(connector, edid); 1451414c4531SDave Airlie kfree(edid); 1452414c4531SDave Airlie } 1453414c4531SDave Airlie return ret; 1454414c4531SDave Airlie } 1455414c4531SDave Airlie 1456abbee623SJulia Lemire static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode, 1457abbee623SJulia Lemire int bits_per_pixel) 1458abbee623SJulia Lemire { 1459abbee623SJulia Lemire uint32_t total_area, divisor; 1460abbee623SJulia Lemire int64_t active_area, pixels_per_second, bandwidth; 1461abbee623SJulia Lemire uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 1462abbee623SJulia Lemire 1463abbee623SJulia Lemire divisor = 1024; 1464abbee623SJulia Lemire 1465abbee623SJulia Lemire if (!mode->htotal || !mode->vtotal || !mode->clock) 1466abbee623SJulia Lemire return 0; 1467abbee623SJulia Lemire 1468abbee623SJulia Lemire active_area = mode->hdisplay * mode->vdisplay; 1469abbee623SJulia Lemire total_area = mode->htotal * mode->vtotal; 1470abbee623SJulia Lemire 1471abbee623SJulia Lemire pixels_per_second = active_area * mode->clock * 1000; 1472abbee623SJulia Lemire do_div(pixels_per_second, total_area); 1473abbee623SJulia Lemire 1474abbee623SJulia Lemire bandwidth = pixels_per_second * bytes_per_pixel * 100; 1475abbee623SJulia Lemire do_div(bandwidth, divisor); 1476abbee623SJulia Lemire 1477abbee623SJulia Lemire return (uint32_t)(bandwidth); 1478abbee623SJulia Lemire } 1479abbee623SJulia Lemire 1480abbee623SJulia Lemire #define MODE_BANDWIDTH MODE_BAD 1481abbee623SJulia Lemire 1482414c4531SDave Airlie static int mga_vga_mode_valid(struct drm_connector *connector, 1483414c4531SDave Airlie struct drm_display_mode *mode) 1484414c4531SDave Airlie { 14850ba53171SChristopher Harvey struct drm_device *dev = connector->dev; 14860ba53171SChristopher Harvey struct mga_device *mdev = (struct mga_device*)dev->dev_private; 14870ba53171SChristopher Harvey int bpp = 32; 14880ba53171SChristopher Harvey 1489abbee623SJulia Lemire if (IS_G200_SE(mdev)) { 1490abbee623SJulia Lemire if (mdev->unique_rev_id == 0x01) { 1491abbee623SJulia Lemire if (mode->hdisplay > 1600) 1492abbee623SJulia Lemire return MODE_VIRTUAL_X; 1493abbee623SJulia Lemire if (mode->vdisplay > 1200) 1494abbee623SJulia Lemire return MODE_VIRTUAL_Y; 1495abbee623SJulia Lemire if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1496abbee623SJulia Lemire > (24400 * 1024)) 1497abbee623SJulia Lemire return MODE_BANDWIDTH; 1498abbee623SJulia Lemire } else if (mdev->unique_rev_id >= 0x02) { 1499abbee623SJulia Lemire if (mode->hdisplay > 1920) 1500abbee623SJulia Lemire return MODE_VIRTUAL_X; 1501abbee623SJulia Lemire if (mode->vdisplay > 1200) 1502abbee623SJulia Lemire return MODE_VIRTUAL_Y; 1503abbee623SJulia Lemire if (mga_vga_calculate_mode_bandwidth(mode, bpp) 1504abbee623SJulia Lemire > (30100 * 1024)) 1505abbee623SJulia Lemire return MODE_BANDWIDTH; 1506abbee623SJulia Lemire } 1507abbee623SJulia Lemire } else if (mdev->type == G200_WB) { 1508abbee623SJulia Lemire if (mode->hdisplay > 1280) 1509abbee623SJulia Lemire return MODE_VIRTUAL_X; 1510abbee623SJulia Lemire if (mode->vdisplay > 1024) 1511abbee623SJulia Lemire return MODE_VIRTUAL_Y; 1512abbee623SJulia Lemire if (mga_vga_calculate_mode_bandwidth(mode, 1513abbee623SJulia Lemire bpp > (31877 * 1024))) 1514abbee623SJulia Lemire return MODE_BANDWIDTH; 1515abbee623SJulia Lemire } else if (mdev->type == G200_EV && 1516abbee623SJulia Lemire (mga_vga_calculate_mode_bandwidth(mode, bpp) 1517abbee623SJulia Lemire > (32700 * 1024))) { 1518abbee623SJulia Lemire return MODE_BANDWIDTH; 1519ec22b4aaSDave Airlie } else if (mdev->type == G200_EH && 1520abbee623SJulia Lemire (mga_vga_calculate_mode_bandwidth(mode, bpp) 1521abbee623SJulia Lemire > (37500 * 1024))) { 1522abbee623SJulia Lemire return MODE_BANDWIDTH; 1523ec22b4aaSDave Airlie } else if (mdev->type == G200_ER && 1524abbee623SJulia Lemire (mga_vga_calculate_mode_bandwidth(mode, 1525abbee623SJulia Lemire bpp) > (55000 * 1024))) { 1526abbee623SJulia Lemire return MODE_BANDWIDTH; 1527abbee623SJulia Lemire } 1528414c4531SDave Airlie 1529414c4531SDave Airlie if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 1530414c4531SDave Airlie mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 1531414c4531SDave Airlie mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 1532414c4531SDave Airlie mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 1533414c4531SDave Airlie return MODE_BAD; 1534414c4531SDave Airlie } 1535414c4531SDave Airlie 15360ba53171SChristopher Harvey /* Validate the mode input by the user */ 1537eaf99c74SChris Wilson if (connector->cmdline_mode.specified) { 1538eaf99c74SChris Wilson if (connector->cmdline_mode.bpp_specified) 1539eaf99c74SChris Wilson bpp = connector->cmdline_mode.bpp; 15400ba53171SChristopher Harvey } 15410ba53171SChristopher Harvey 15420ba53171SChristopher Harvey if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { 1543eaf99c74SChris Wilson if (connector->cmdline_mode.specified) 1544eaf99c74SChris Wilson connector->cmdline_mode.specified = false; 15450ba53171SChristopher Harvey return MODE_BAD; 15460ba53171SChristopher Harvey } 15470ba53171SChristopher Harvey 1548414c4531SDave Airlie return MODE_OK; 1549414c4531SDave Airlie } 1550414c4531SDave Airlie 1551080fd6b5SRashika static struct drm_encoder *mga_connector_best_encoder(struct drm_connector 1552414c4531SDave Airlie *connector) 1553414c4531SDave Airlie { 1554414c4531SDave Airlie int enc_id = connector->encoder_ids[0]; 1555414c4531SDave Airlie /* pick the encoder ids */ 1556c7e95114SRob Clark if (enc_id) 1557c7e95114SRob Clark return drm_encoder_find(connector->dev, enc_id); 1558414c4531SDave Airlie return NULL; 1559414c4531SDave Airlie } 1560414c4531SDave Airlie 1561414c4531SDave Airlie static enum drm_connector_status mga_vga_detect(struct drm_connector 1562414c4531SDave Airlie *connector, bool force) 1563414c4531SDave Airlie { 1564414c4531SDave Airlie return connector_status_connected; 1565414c4531SDave Airlie } 1566414c4531SDave Airlie 1567414c4531SDave Airlie static void mga_connector_destroy(struct drm_connector *connector) 1568414c4531SDave Airlie { 1569414c4531SDave Airlie struct mga_connector *mga_connector = to_mga_connector(connector); 1570414c4531SDave Airlie mgag200_i2c_destroy(mga_connector->i2c); 1571414c4531SDave Airlie drm_connector_cleanup(connector); 1572414c4531SDave Airlie kfree(connector); 1573414c4531SDave Airlie } 1574414c4531SDave Airlie 1575414c4531SDave Airlie struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { 1576414c4531SDave Airlie .get_modes = mga_vga_get_modes, 1577414c4531SDave Airlie .mode_valid = mga_vga_mode_valid, 1578414c4531SDave Airlie .best_encoder = mga_connector_best_encoder, 1579414c4531SDave Airlie }; 1580414c4531SDave Airlie 1581414c4531SDave Airlie struct drm_connector_funcs mga_vga_connector_funcs = { 1582414c4531SDave Airlie .dpms = drm_helper_connector_dpms, 1583414c4531SDave Airlie .detect = mga_vga_detect, 1584414c4531SDave Airlie .fill_modes = drm_helper_probe_single_connector_modes, 1585414c4531SDave Airlie .destroy = mga_connector_destroy, 1586414c4531SDave Airlie }; 1587414c4531SDave Airlie 1588414c4531SDave Airlie static struct drm_connector *mga_vga_init(struct drm_device *dev) 1589414c4531SDave Airlie { 1590414c4531SDave Airlie struct drm_connector *connector; 1591414c4531SDave Airlie struct mga_connector *mga_connector; 1592414c4531SDave Airlie 1593414c4531SDave Airlie mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL); 1594414c4531SDave Airlie if (!mga_connector) 1595414c4531SDave Airlie return NULL; 1596414c4531SDave Airlie 1597414c4531SDave Airlie connector = &mga_connector->base; 1598414c4531SDave Airlie 1599414c4531SDave Airlie drm_connector_init(dev, connector, 1600414c4531SDave Airlie &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1601414c4531SDave Airlie 1602414c4531SDave Airlie drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); 1603414c4531SDave Airlie 160434ea3d38SThomas Wood drm_connector_register(connector); 16053d5a1c5eSEgbert Eich 1606414c4531SDave Airlie mga_connector->i2c = mgag200_i2c_create(dev); 1607414c4531SDave Airlie if (!mga_connector->i2c) 1608414c4531SDave Airlie DRM_ERROR("failed to add ddc bus\n"); 1609414c4531SDave Airlie 1610414c4531SDave Airlie return connector; 1611414c4531SDave Airlie } 1612414c4531SDave Airlie 1613414c4531SDave Airlie 1614414c4531SDave Airlie int mgag200_modeset_init(struct mga_device *mdev) 1615414c4531SDave Airlie { 1616414c4531SDave Airlie struct drm_encoder *encoder; 1617414c4531SDave Airlie struct drm_connector *connector; 1618414c4531SDave Airlie int ret; 1619414c4531SDave Airlie 1620414c4531SDave Airlie mdev->mode_info.mode_config_initialized = true; 1621414c4531SDave Airlie 1622414c4531SDave Airlie mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 1623414c4531SDave Airlie mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 1624414c4531SDave Airlie 1625414c4531SDave Airlie mdev->dev->mode_config.fb_base = mdev->mc.vram_base; 1626414c4531SDave Airlie 1627f1998fe2SChristopher Harvey mga_crtc_init(mdev); 1628414c4531SDave Airlie 1629414c4531SDave Airlie encoder = mga_encoder_init(mdev->dev); 1630414c4531SDave Airlie if (!encoder) { 1631414c4531SDave Airlie DRM_ERROR("mga_encoder_init failed\n"); 1632414c4531SDave Airlie return -1; 1633414c4531SDave Airlie } 1634414c4531SDave Airlie 1635414c4531SDave Airlie connector = mga_vga_init(mdev->dev); 1636414c4531SDave Airlie if (!connector) { 1637414c4531SDave Airlie DRM_ERROR("mga_vga_init failed\n"); 1638414c4531SDave Airlie return -1; 1639414c4531SDave Airlie } 1640414c4531SDave Airlie 1641414c4531SDave Airlie drm_mode_connector_attach_encoder(connector, encoder); 1642414c4531SDave Airlie 1643414c4531SDave Airlie ret = mgag200_fbdev_init(mdev); 1644414c4531SDave Airlie if (ret) { 1645414c4531SDave Airlie DRM_ERROR("mga_fbdev_init failed\n"); 1646414c4531SDave Airlie return ret; 1647414c4531SDave Airlie } 1648414c4531SDave Airlie 1649414c4531SDave Airlie return 0; 1650414c4531SDave Airlie } 1651414c4531SDave Airlie 1652414c4531SDave Airlie void mgag200_modeset_fini(struct mga_device *mdev) 1653414c4531SDave Airlie { 1654414c4531SDave Airlie 1655414c4531SDave Airlie } 1656