1c51669eaSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2414c4531SDave Airlie /* 3414c4531SDave Airlie * Copyright 2010 Matt Turner. 4414c4531SDave Airlie * Copyright 2012 Red Hat 5414c4531SDave Airlie * 6414c4531SDave Airlie * Authors: Matthew Garrett 7414c4531SDave Airlie * Matt Turner 8414c4531SDave Airlie * Dave Airlie 9414c4531SDave Airlie */ 10414c4531SDave Airlie 11414c4531SDave Airlie #include <linux/delay.h> 127938f421SLucas De Marchi #include <linux/iosys-map.h> 13414c4531SDave Airlie 142d70b9a1SThomas Zimmermann #include <drm/drm_atomic.h> 1588fabb75SThomas Zimmermann #include <drm/drm_atomic_helper.h> 16913ec479SThomas Zimmermann #include <drm/drm_damage_helper.h> 172e367ad4SJani Nikula #include <drm/drm_edid.h> 18913ec479SThomas Zimmermann #include <drm/drm_format_helper.h> 199f397801SSam Ravnborg #include <drm/drm_fourcc.h> 20720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h> 214862ffaeSThomas Zimmermann #include <drm/drm_gem_atomic_helper.h> 225635b7cfSThomas Zimmermann #include <drm/drm_gem_framebuffer_helper.h> 237e64f7c8SJocelyn Falempe #include <drm/drm_panic.h> 2488fabb75SThomas Zimmermann #include <drm/drm_print.h> 2589c6ea20SThomas Zimmermann #include <drm/drm_vblank.h> 26414c4531SDave Airlie 27f2e99524SThomas Zimmermann #include "mgag200_ddc.h" 28414c4531SDave Airlie #include "mgag200_drv.h" 29414c4531SDave Airlie 30414c4531SDave Airlie /* 31414c4531SDave Airlie * This file contains setup code for the CRTC. 32414c4531SDave Airlie */ 33414c4531SDave Airlie 3411f9eb89SJocelyn Falempe void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, 35c577b2f4SJocelyn Falempe const struct drm_format_info *format) 36414c4531SDave Airlie { 37414c4531SDave Airlie int i; 38414c4531SDave Airlie 39414c4531SDave Airlie WREG8(DAC_INDEX + MGA1064_INDEX, 0); 40414c4531SDave Airlie 41c577b2f4SJocelyn Falempe switch (format->format) { 42c577b2f4SJocelyn Falempe case DRM_FORMAT_RGB565: 43c577b2f4SJocelyn Falempe /* Use better interpolation, to take 32 values from 0 to 255 */ 44c577b2f4SJocelyn Falempe for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 45c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 46c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 47c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); 48de7500eaSEgbert Eich } 49c577b2f4SJocelyn Falempe /* Green has one more bit, so add padding with 0 for red and blue. */ 50c577b2f4SJocelyn Falempe for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 51c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 52c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); 53c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 54de7500eaSEgbert Eich } 55c577b2f4SJocelyn Falempe break; 56c577b2f4SJocelyn Falempe case DRM_FORMAT_RGB888: 57c577b2f4SJocelyn Falempe case DRM_FORMAT_XRGB8888: 58414c4531SDave Airlie for (i = 0; i < MGAG200_LUT_SIZE; i++) { 59c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 60c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 61c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, i); 62c577b2f4SJocelyn Falempe } 63c577b2f4SJocelyn Falempe break; 64c577b2f4SJocelyn Falempe default: 65c577b2f4SJocelyn Falempe drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 66c577b2f4SJocelyn Falempe &format->format); 67c577b2f4SJocelyn Falempe break; 68c577b2f4SJocelyn Falempe } 69c577b2f4SJocelyn Falempe } 70c577b2f4SJocelyn Falempe 7111f9eb89SJocelyn Falempe void mgag200_crtc_set_gamma(struct mga_device *mdev, 72c577b2f4SJocelyn Falempe const struct drm_format_info *format, 73c577b2f4SJocelyn Falempe struct drm_color_lut *lut) 74c577b2f4SJocelyn Falempe { 75c577b2f4SJocelyn Falempe int i; 76c577b2f4SJocelyn Falempe 77c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_INDEX, 0); 78c577b2f4SJocelyn Falempe 79c577b2f4SJocelyn Falempe switch (format->format) { 80c577b2f4SJocelyn Falempe case DRM_FORMAT_RGB565: 81c577b2f4SJocelyn Falempe /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 82c577b2f4SJocelyn Falempe for (i = 0; i < MGAG200_LUT_SIZE / 8; i++) { 83c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); 84c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 85c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].blue >> 8); 86c577b2f4SJocelyn Falempe } 87c577b2f4SJocelyn Falempe /* Green has one more bit, so add padding with 0 for red and blue. */ 88c577b2f4SJocelyn Falempe for (i = MGAG200_LUT_SIZE / 8; i < MGAG200_LUT_SIZE / 4; i++) { 89c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 90c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); 91c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); 92c577b2f4SJocelyn Falempe } 93c577b2f4SJocelyn Falempe break; 94c577b2f4SJocelyn Falempe case DRM_FORMAT_RGB888: 95c577b2f4SJocelyn Falempe case DRM_FORMAT_XRGB8888: 96c577b2f4SJocelyn Falempe for (i = 0; i < MGAG200_LUT_SIZE; i++) { 97c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].red >> 8); 98c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].green >> 8); 99c577b2f4SJocelyn Falempe WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i].blue >> 8); 100c577b2f4SJocelyn Falempe } 101c577b2f4SJocelyn Falempe break; 102c577b2f4SJocelyn Falempe default: 103c577b2f4SJocelyn Falempe drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 104c577b2f4SJocelyn Falempe &format->format); 105c577b2f4SJocelyn Falempe break; 106414c4531SDave Airlie } 107414c4531SDave Airlie } 108414c4531SDave Airlie 109414c4531SDave Airlie static inline void mga_wait_vsync(struct mga_device *mdev) 110414c4531SDave Airlie { 1113cdc0e8dSChristopher Harvey unsigned long timeout = jiffies + HZ/10; 112414c4531SDave Airlie unsigned int status = 0; 113414c4531SDave Airlie 114414c4531SDave Airlie do { 11568550521SThomas Zimmermann status = RREG32(MGAREG_STATUS); 1163cdc0e8dSChristopher Harvey } while ((status & 0x08) && time_before(jiffies, timeout)); 1173cdc0e8dSChristopher Harvey timeout = jiffies + HZ/10; 118414c4531SDave Airlie status = 0; 119414c4531SDave Airlie do { 12068550521SThomas Zimmermann status = RREG32(MGAREG_STATUS); 1213cdc0e8dSChristopher Harvey } while (!(status & 0x08) && time_before(jiffies, timeout)); 122414c4531SDave Airlie } 123414c4531SDave Airlie 124414c4531SDave Airlie static inline void mga_wait_busy(struct mga_device *mdev) 125414c4531SDave Airlie { 1263cdc0e8dSChristopher Harvey unsigned long timeout = jiffies + HZ; 127414c4531SDave Airlie unsigned int status = 0; 128414c4531SDave Airlie do { 12968550521SThomas Zimmermann status = RREG8(MGAREG_STATUS + 2); 1303cdc0e8dSChristopher Harvey } while ((status & 0x01) && time_before(jiffies, timeout)); 131414c4531SDave Airlie } 132414c4531SDave Airlie 1339f1d0366SChristopher Harvey /* 134d6237687SThomas Zimmermann * This is how the framebuffer base address is stored in g200 cards: 135d6237687SThomas Zimmermann * * Assume @offset is the gpu_addr variable of the framebuffer object 136d6237687SThomas Zimmermann * * Then addr is the number of _pixels_ (not bytes) from the start of 137d6237687SThomas Zimmermann * VRAM to the first pixel we want to display. (divided by 2 for 32bit 138d6237687SThomas Zimmermann * framebuffers) 139d6237687SThomas Zimmermann * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 140d6237687SThomas Zimmermann * addr<20> -> CRTCEXT0<6> 141d6237687SThomas Zimmermann * addr<19-16> -> CRTCEXT0<3-0> 142d6237687SThomas Zimmermann * addr<15-8> -> CRTCC<7-0> 143d6237687SThomas Zimmermann * addr<7-0> -> CRTCD<7-0> 144d6237687SThomas Zimmermann * 145d6237687SThomas Zimmermann * CRTCEXT0 has to be programmed last to trigger an update and make the 146d6237687SThomas Zimmermann * new addr variable take effect. 1479f1d0366SChristopher Harvey */ 148d6237687SThomas Zimmermann static void mgag200_set_startadd(struct mga_device *mdev, 149d6237687SThomas Zimmermann unsigned long offset) 150414c4531SDave Airlie { 151832eddf5SThomas Zimmermann struct drm_device *dev = &mdev->base; 152d6237687SThomas Zimmermann u32 startadd; 153d6237687SThomas Zimmermann u8 crtcc, crtcd, crtcext0; 154414c4531SDave Airlie 155d6237687SThomas Zimmermann startadd = offset / 8; 156414c4531SDave Airlie 157d2addf89SJocelyn Falempe if (startadd > 0) 15821e74bf9SThomas Zimmermann drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd); 159d2addf89SJocelyn Falempe 160d6237687SThomas Zimmermann /* 161d6237687SThomas Zimmermann * Can't store addresses any higher than that, but we also 162d6237687SThomas Zimmermann * don't have more than 16 MiB of memory, so it should be fine. 163d6237687SThomas Zimmermann */ 164d6237687SThomas Zimmermann drm_WARN_ON(dev, startadd > 0x1fffff); 165414c4531SDave Airlie 166d6237687SThomas Zimmermann RREG_ECRT(0x00, crtcext0); 167d6237687SThomas Zimmermann 168d6237687SThomas Zimmermann crtcc = (startadd >> 8) & 0xff; 169d6237687SThomas Zimmermann crtcd = startadd & 0xff; 170d6237687SThomas Zimmermann crtcext0 &= 0xb0; 171d6237687SThomas Zimmermann crtcext0 |= ((startadd >> 14) & BIT(6)) | 172d6237687SThomas Zimmermann ((startadd >> 16) & 0x0f); 173d6237687SThomas Zimmermann 174d6237687SThomas Zimmermann WREG_CRT(0x0c, crtcc); 175d6237687SThomas Zimmermann WREG_CRT(0x0d, crtcd); 176d6237687SThomas Zimmermann WREG_ECRT(0x00, crtcext0); 177414c4531SDave Airlie } 178414c4531SDave Airlie 1791ee181feSThomas Zimmermann void mgag200_init_registers(struct mga_device *mdev) 1804f710d7cSThomas Zimmermann { 1819053cad2SThomas Zimmermann u8 crtc11, misc; 1824f710d7cSThomas Zimmermann 1834f710d7cSThomas Zimmermann WREG_SEQ(2, 0x0f); 1844f710d7cSThomas Zimmermann WREG_SEQ(3, 0x00); 1854f710d7cSThomas Zimmermann WREG_SEQ(4, 0x0e); 1864f710d7cSThomas Zimmermann 1874f710d7cSThomas Zimmermann WREG_CRT(10, 0); 1884f710d7cSThomas Zimmermann WREG_CRT(11, 0); 1894f710d7cSThomas Zimmermann WREG_CRT(12, 0); 1904f710d7cSThomas Zimmermann WREG_CRT(13, 0); 1914f710d7cSThomas Zimmermann WREG_CRT(14, 0); 1924f710d7cSThomas Zimmermann WREG_CRT(15, 0); 1934f710d7cSThomas Zimmermann 194da568d5eSThomas Zimmermann RREG_CRT(0x11, crtc11); 195da568d5eSThomas Zimmermann crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 196da568d5eSThomas Zimmermann MGAREG_CRTC11_VINTEN | 197da568d5eSThomas Zimmermann MGAREG_CRTC11_VINTCLR); 198da568d5eSThomas Zimmermann WREG_CRT(0x11, crtc11); 199da568d5eSThomas Zimmermann 2004f710d7cSThomas Zimmermann misc = RREG8(MGA_MISC_IN); 201b9fa77ecSThomas Zimmermann misc |= MGAREG_MISC_IOADSEL; 2024f710d7cSThomas Zimmermann WREG8(MGA_MISC_OUT, misc); 2034f710d7cSThomas Zimmermann } 2044f710d7cSThomas Zimmermann 205cd3a2e8bSThomas Zimmermann void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode, 206cd3a2e8bSThomas Zimmermann bool set_vidrst) 207a6edae07SThomas Zimmermann { 208d6460bd5SThomas Zimmermann unsigned int hdispend, hsyncstr, hsyncend, htotal, hblkstr, hblkend; 209d6460bd5SThomas Zimmermann unsigned int vdispend, vsyncstr, vsyncend, vtotal, vblkstr, vblkend; 2105cd522b5SThomas Zimmermann unsigned int linecomp; 211db05f8d3SThomas Zimmermann u8 misc, crtcext1, crtcext2, crtcext5; 212a6edae07SThomas Zimmermann 213e8f834b5SThomas Zimmermann hdispend = mode->crtc_hdisplay / 8 - 1; 214e8f834b5SThomas Zimmermann hsyncstr = mode->crtc_hsync_start / 8 - 1; 215e8f834b5SThomas Zimmermann hsyncend = mode->crtc_hsync_end / 8 - 1; 216e8f834b5SThomas Zimmermann htotal = mode->crtc_htotal / 8 - 1; 217a6edae07SThomas Zimmermann /* Work around hardware quirk */ 218a6edae07SThomas Zimmermann if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 219a6edae07SThomas Zimmermann htotal++; 220d6460bd5SThomas Zimmermann hblkstr = mode->crtc_hblank_start / 8 - 1; 221d6460bd5SThomas Zimmermann hblkend = htotal; 222a6edae07SThomas Zimmermann 223e8f834b5SThomas Zimmermann vdispend = mode->crtc_vdisplay - 1; 224e8f834b5SThomas Zimmermann vsyncstr = mode->crtc_vsync_start - 1; 225e8f834b5SThomas Zimmermann vsyncend = mode->crtc_vsync_end - 1; 226e8f834b5SThomas Zimmermann vtotal = mode->crtc_vtotal - 2; 227d6460bd5SThomas Zimmermann vblkstr = mode->crtc_vblank_start; 228d6460bd5SThomas Zimmermann vblkend = vtotal + 1; 229a6edae07SThomas Zimmermann 23089c6ea20SThomas Zimmermann /* 23189c6ea20SThomas Zimmermann * There's no VBLANK interrupt on Matrox chipsets, so we use 23289c6ea20SThomas Zimmermann * the VLINE interrupt instead. It triggers when the current 23389c6ea20SThomas Zimmermann * <linecomp> has been reached. For VBLANK, this is the first 23489c6ea20SThomas Zimmermann * non-visible line at the bottom of the screen. Therefore, 23589c6ea20SThomas Zimmermann * keep <linecomp> in sync with <vblkstr>. 23689c6ea20SThomas Zimmermann */ 23789c6ea20SThomas Zimmermann linecomp = vblkstr; 2385cd522b5SThomas Zimmermann 239db05f8d3SThomas Zimmermann misc = RREG8(MGA_MISC_IN); 240db05f8d3SThomas Zimmermann 241a6edae07SThomas Zimmermann if (mode->flags & DRM_MODE_FLAG_NHSYNC) 242db05f8d3SThomas Zimmermann misc |= MGAREG_MISC_HSYNCPOL; 243db05f8d3SThomas Zimmermann else 244db05f8d3SThomas Zimmermann misc &= ~MGAREG_MISC_HSYNCPOL; 245db05f8d3SThomas Zimmermann 246a6edae07SThomas Zimmermann if (mode->flags & DRM_MODE_FLAG_NVSYNC) 247db05f8d3SThomas Zimmermann misc |= MGAREG_MISC_VSYNCPOL; 248db05f8d3SThomas Zimmermann else 249db05f8d3SThomas Zimmermann misc &= ~MGAREG_MISC_VSYNCPOL; 250a6edae07SThomas Zimmermann 251a6edae07SThomas Zimmermann crtcext1 = (((htotal - 4) & 0x100) >> 8) | 252d6460bd5SThomas Zimmermann ((hblkstr & 0x100) >> 7) | 253b345b354SThomas Zimmermann ((hsyncstr & 0x100) >> 6) | 254d6460bd5SThomas Zimmermann (hblkend & 0x40); 255cd3a2e8bSThomas Zimmermann if (set_vidrst) 256d1e40d8eSThomas Zimmermann crtcext1 |= MGAREG_CRTCEXT1_VRSTEN | 257d1e40d8eSThomas Zimmermann MGAREG_CRTCEXT1_HRSTEN; 258a6edae07SThomas Zimmermann 259a6edae07SThomas Zimmermann crtcext2 = ((vtotal & 0xc00) >> 10) | 260b345b354SThomas Zimmermann ((vdispend & 0x400) >> 8) | 261d6460bd5SThomas Zimmermann ((vblkstr & 0xc00) >> 7) | 262b345b354SThomas Zimmermann ((vsyncstr & 0xc00) >> 5) | 2635cd522b5SThomas Zimmermann ((linecomp & 0x400) >> 3); 264a6edae07SThomas Zimmermann crtcext5 = 0x00; 265a6edae07SThomas Zimmermann 266754c9129SThomas Zimmermann WREG_CRT(0x00, htotal - 4); 267b345b354SThomas Zimmermann WREG_CRT(0x01, hdispend); 268d6460bd5SThomas Zimmermann WREG_CRT(0x02, hblkstr); 269d6460bd5SThomas Zimmermann WREG_CRT(0x03, (hblkend & 0x1f) | 0x80); 270b345b354SThomas Zimmermann WREG_CRT(0x04, hsyncstr); 271d6460bd5SThomas Zimmermann WREG_CRT(0x05, ((hblkend & 0x20) << 2) | (hsyncend & 0x1f)); 272754c9129SThomas Zimmermann WREG_CRT(0x06, vtotal & 0xff); 273754c9129SThomas Zimmermann WREG_CRT(0x07, ((vtotal & 0x100) >> 8) | 274b345b354SThomas Zimmermann ((vdispend & 0x100) >> 7) | 275b345b354SThomas Zimmermann ((vsyncstr & 0x100) >> 6) | 276d6460bd5SThomas Zimmermann ((vblkstr & 0x100) >> 5) | 2775cd522b5SThomas Zimmermann ((linecomp & 0x100) >> 4) | 278a6edae07SThomas Zimmermann ((vtotal & 0x200) >> 4) | 279b345b354SThomas Zimmermann ((vdispend & 0x200) >> 3) | 280b345b354SThomas Zimmermann ((vsyncstr & 0x200) >> 2)); 281d6460bd5SThomas Zimmermann WREG_CRT(0x09, ((vblkstr & 0x200) >> 4) | 2825cd522b5SThomas Zimmermann ((linecomp & 0x200) >> 3)); 283b345b354SThomas Zimmermann WREG_CRT(0x10, vsyncstr & 0xff); 284754c9129SThomas Zimmermann WREG_CRT(0x11, (vsyncend & 0x0f) | 0x20); 285b345b354SThomas Zimmermann WREG_CRT(0x12, vdispend & 0xff); 286754c9129SThomas Zimmermann WREG_CRT(0x14, 0); 287d6460bd5SThomas Zimmermann WREG_CRT(0x15, vblkstr & 0xff); 288d6460bd5SThomas Zimmermann WREG_CRT(0x16, vblkend & 0xff); 289754c9129SThomas Zimmermann WREG_CRT(0x17, 0xc3); 2905cd522b5SThomas Zimmermann WREG_CRT(0x18, linecomp & 0xff); 291a6edae07SThomas Zimmermann 292a6edae07SThomas Zimmermann WREG_ECRT(0x01, crtcext1); 293a6edae07SThomas Zimmermann WREG_ECRT(0x02, crtcext2); 294a6edae07SThomas Zimmermann WREG_ECRT(0x05, crtcext5); 295db05f8d3SThomas Zimmermann 296db05f8d3SThomas Zimmermann WREG8(MGA_MISC_OUT, misc); 297a6edae07SThomas Zimmermann } 298a6edae07SThomas Zimmermann 299d9cc564bSThomas Zimmermann static u8 mgag200_get_bpp_shift(const struct drm_format_info *format) 30072a03a35SThomas Zimmermann { 301d9cc564bSThomas Zimmermann static const u8 bpp_shift[] = {0, 1, 0, 2}; 302d9cc564bSThomas Zimmermann 303d9cc564bSThomas Zimmermann return bpp_shift[format->cpp[0] - 1]; 30472a03a35SThomas Zimmermann } 30572a03a35SThomas Zimmermann 30672a03a35SThomas Zimmermann /* 30772a03a35SThomas Zimmermann * Calculates the HW offset value from the framebuffer's pitch. The 30872a03a35SThomas Zimmermann * offset is a multiple of the pixel size and depends on the display 30972a03a35SThomas Zimmermann * format. 31072a03a35SThomas Zimmermann */ 31172a03a35SThomas Zimmermann static u32 mgag200_calculate_offset(struct mga_device *mdev, 31272a03a35SThomas Zimmermann const struct drm_framebuffer *fb) 31372a03a35SThomas Zimmermann { 31472a03a35SThomas Zimmermann u32 offset = fb->pitches[0] / fb->format->cpp[0]; 315d9cc564bSThomas Zimmermann u8 bppshift = mgag200_get_bpp_shift(fb->format); 31672a03a35SThomas Zimmermann 31772a03a35SThomas Zimmermann if (fb->format->cpp[0] * 8 == 24) 31872a03a35SThomas Zimmermann offset = (offset * 3) >> (4 - bppshift); 31972a03a35SThomas Zimmermann else 32072a03a35SThomas Zimmermann offset = offset >> (4 - bppshift); 32172a03a35SThomas Zimmermann 32272a03a35SThomas Zimmermann return offset; 32372a03a35SThomas Zimmermann } 32472a03a35SThomas Zimmermann 32572a03a35SThomas Zimmermann static void mgag200_set_offset(struct mga_device *mdev, 32672a03a35SThomas Zimmermann const struct drm_framebuffer *fb) 32772a03a35SThomas Zimmermann { 32872a03a35SThomas Zimmermann u8 crtc13, crtcext0; 32972a03a35SThomas Zimmermann u32 offset = mgag200_calculate_offset(mdev, fb); 33072a03a35SThomas Zimmermann 33172a03a35SThomas Zimmermann RREG_ECRT(0, crtcext0); 33272a03a35SThomas Zimmermann 33372a03a35SThomas Zimmermann crtc13 = offset & 0xff; 33472a03a35SThomas Zimmermann 33572a03a35SThomas Zimmermann crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 33672a03a35SThomas Zimmermann crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 33772a03a35SThomas Zimmermann 33872a03a35SThomas Zimmermann WREG_CRT(0x13, crtc13); 33972a03a35SThomas Zimmermann WREG_ECRT(0x00, crtcext0); 34072a03a35SThomas Zimmermann } 34172a03a35SThomas Zimmermann 342828369f2SThomas Zimmermann void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format) 343836d5368SThomas Zimmermann { 344832eddf5SThomas Zimmermann struct drm_device *dev = &mdev->base; 345836d5368SThomas Zimmermann unsigned int bpp, bppshift, scale; 346836d5368SThomas Zimmermann u8 crtcext3, xmulctrl; 347836d5368SThomas Zimmermann 348836d5368SThomas Zimmermann bpp = format->cpp[0] * 8; 349836d5368SThomas Zimmermann 350d9cc564bSThomas Zimmermann bppshift = mgag200_get_bpp_shift(format); 351836d5368SThomas Zimmermann switch (bpp) { 352836d5368SThomas Zimmermann case 24: 353836d5368SThomas Zimmermann scale = ((1 << bppshift) * 3) - 1; 354836d5368SThomas Zimmermann break; 355836d5368SThomas Zimmermann default: 356836d5368SThomas Zimmermann scale = (1 << bppshift) - 1; 357836d5368SThomas Zimmermann break; 358836d5368SThomas Zimmermann } 359836d5368SThomas Zimmermann 360836d5368SThomas Zimmermann RREG_ECRT(3, crtcext3); 361836d5368SThomas Zimmermann 362836d5368SThomas Zimmermann switch (bpp) { 363836d5368SThomas Zimmermann case 8: 364836d5368SThomas Zimmermann xmulctrl = MGA1064_MUL_CTL_8bits; 365836d5368SThomas Zimmermann break; 366836d5368SThomas Zimmermann case 16: 367836d5368SThomas Zimmermann if (format->depth == 15) 368836d5368SThomas Zimmermann xmulctrl = MGA1064_MUL_CTL_15bits; 369836d5368SThomas Zimmermann else 370836d5368SThomas Zimmermann xmulctrl = MGA1064_MUL_CTL_16bits; 371836d5368SThomas Zimmermann break; 372836d5368SThomas Zimmermann case 24: 373836d5368SThomas Zimmermann xmulctrl = MGA1064_MUL_CTL_24bits; 374836d5368SThomas Zimmermann break; 375836d5368SThomas Zimmermann case 32: 376836d5368SThomas Zimmermann xmulctrl = MGA1064_MUL_CTL_32_24bits; 377836d5368SThomas Zimmermann break; 378836d5368SThomas Zimmermann default: 379836d5368SThomas Zimmermann /* BUG: We should have caught this problem already. */ 380836d5368SThomas Zimmermann drm_WARN_ON(dev, "invalid format depth\n"); 381836d5368SThomas Zimmermann return; 382836d5368SThomas Zimmermann } 383836d5368SThomas Zimmermann 384836d5368SThomas Zimmermann crtcext3 &= ~GENMASK(2, 0); 385836d5368SThomas Zimmermann crtcext3 |= scale; 386836d5368SThomas Zimmermann 387836d5368SThomas Zimmermann WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 388836d5368SThomas Zimmermann 389836d5368SThomas Zimmermann WREG_GFX(0, 0x00); 390836d5368SThomas Zimmermann WREG_GFX(1, 0x00); 391836d5368SThomas Zimmermann WREG_GFX(2, 0x00); 392836d5368SThomas Zimmermann WREG_GFX(3, 0x00); 393836d5368SThomas Zimmermann WREG_GFX(4, 0x00); 394836d5368SThomas Zimmermann WREG_GFX(5, 0x40); 395028a73e1SJocelyn Falempe /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 396028a73e1SJocelyn Falempe * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 397028a73e1SJocelyn Falempe */ 398028a73e1SJocelyn Falempe WREG_GFX(6, 0x0d); 399836d5368SThomas Zimmermann WREG_GFX(7, 0x0f); 400836d5368SThomas Zimmermann WREG_GFX(8, 0x0f); 401836d5368SThomas Zimmermann 402836d5368SThomas Zimmermann WREG_ECRT(3, crtcext3); 403836d5368SThomas Zimmermann } 404836d5368SThomas Zimmermann 405828369f2SThomas Zimmermann void mgag200_enable_display(struct mga_device *mdev) 406414c4531SDave Airlie { 4075cd062e3SThomas Zimmermann u8 seq0, crtcext1; 40870c3881eSThomas Zimmermann 40970c3881eSThomas Zimmermann RREG_SEQ(0x00, seq0); 41070c3881eSThomas Zimmermann seq0 |= MGAREG_SEQ0_SYNCRST | 41170c3881eSThomas Zimmermann MGAREG_SEQ0_ASYNCRST; 41270c3881eSThomas Zimmermann WREG_SEQ(0x00, seq0); 413414c4531SDave Airlie 414153fef41SThomas Zimmermann /* 415153fef41SThomas Zimmermann * TODO: replace busy waiting with vblank IRQ; put 416153fef41SThomas Zimmermann * msleep(50) before changing SCROFF 417153fef41SThomas Zimmermann */ 418414c4531SDave Airlie mga_wait_vsync(mdev); 419414c4531SDave Airlie mga_wait_busy(mdev); 420153fef41SThomas Zimmermann 421153fef41SThomas Zimmermann RREG_ECRT(0x01, crtcext1); 422153fef41SThomas Zimmermann crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 423153fef41SThomas Zimmermann crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 424153fef41SThomas Zimmermann WREG_ECRT(0x01, crtcext1); 425153fef41SThomas Zimmermann } 426153fef41SThomas Zimmermann 427153fef41SThomas Zimmermann static void mgag200_disable_display(struct mga_device *mdev) 428153fef41SThomas Zimmermann { 4295cd062e3SThomas Zimmermann u8 seq0, crtcext1; 43070c3881eSThomas Zimmermann 43170c3881eSThomas Zimmermann RREG_SEQ(0x00, seq0); 43270c3881eSThomas Zimmermann seq0 &= ~MGAREG_SEQ0_SYNCRST; 43370c3881eSThomas Zimmermann WREG_SEQ(0x00, seq0); 434153fef41SThomas Zimmermann 435153fef41SThomas Zimmermann /* 436153fef41SThomas Zimmermann * TODO: replace busy waiting with vblank IRQ; put 437153fef41SThomas Zimmermann * msleep(50) before changing SCROFF 438153fef41SThomas Zimmermann */ 439153fef41SThomas Zimmermann mga_wait_vsync(mdev); 440153fef41SThomas Zimmermann mga_wait_busy(mdev); 441153fef41SThomas Zimmermann 442153fef41SThomas Zimmermann RREG_ECRT(0x01, crtcext1); 443153fef41SThomas Zimmermann crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 444153fef41SThomas Zimmermann MGAREG_CRTCEXT1_HSYNCOFF; 445153fef41SThomas Zimmermann WREG_ECRT(0x01, crtcext1); 446414c4531SDave Airlie } 447414c4531SDave Airlie 4484f4dc37eSThomas Zimmermann static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap, 449edbe262aSThomas Zimmermann struct drm_framebuffer *fb, struct drm_rect *clip) 450414c4531SDave Airlie { 451edbe262aSThomas Zimmermann struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 452414c4531SDave Airlie 453edbe262aSThomas Zimmermann iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip)); 454edbe262aSThomas Zimmermann drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip); 455414c4531SDave Airlie } 456414c4531SDave Airlie 45788fabb75SThomas Zimmermann /* 4581baf9127SThomas Zimmermann * Primary plane 45988fabb75SThomas Zimmermann */ 46088fabb75SThomas Zimmermann 461bc835040SThomas Zimmermann const uint32_t mgag200_primary_plane_formats[] = { 4624f4dc37eSThomas Zimmermann DRM_FORMAT_XRGB8888, 4634f4dc37eSThomas Zimmermann DRM_FORMAT_RGB565, 4644f4dc37eSThomas Zimmermann DRM_FORMAT_RGB888, 4654f4dc37eSThomas Zimmermann }; 4664f4dc37eSThomas Zimmermann 467bc835040SThomas Zimmermann const size_t mgag200_primary_plane_formats_size = ARRAY_SIZE(mgag200_primary_plane_formats); 468bc835040SThomas Zimmermann 469bc835040SThomas Zimmermann const uint64_t mgag200_primary_plane_fmtmods[] = { 4704f4dc37eSThomas Zimmermann DRM_FORMAT_MOD_LINEAR, 4714f4dc37eSThomas Zimmermann DRM_FORMAT_MOD_INVALID 4724f4dc37eSThomas Zimmermann }; 4734f4dc37eSThomas Zimmermann 474bc835040SThomas Zimmermann int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 4751baf9127SThomas Zimmermann struct drm_atomic_state *new_state) 4761baf9127SThomas Zimmermann { 4771baf9127SThomas Zimmermann struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); 4781baf9127SThomas Zimmermann struct drm_framebuffer *new_fb = new_plane_state->fb; 4791baf9127SThomas Zimmermann struct drm_framebuffer *fb = NULL; 4801baf9127SThomas Zimmermann struct drm_crtc *new_crtc = new_plane_state->crtc; 4811baf9127SThomas Zimmermann struct drm_crtc_state *new_crtc_state = NULL; 4821baf9127SThomas Zimmermann struct mgag200_crtc_state *new_mgag200_crtc_state; 4831baf9127SThomas Zimmermann int ret; 4841baf9127SThomas Zimmermann 4851baf9127SThomas Zimmermann if (new_crtc) 4861baf9127SThomas Zimmermann new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_crtc); 4871baf9127SThomas Zimmermann 4881baf9127SThomas Zimmermann ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 4891baf9127SThomas Zimmermann DRM_PLANE_NO_SCALING, 4901baf9127SThomas Zimmermann DRM_PLANE_NO_SCALING, 4911baf9127SThomas Zimmermann false, true); 4921baf9127SThomas Zimmermann if (ret) 4931baf9127SThomas Zimmermann return ret; 4941baf9127SThomas Zimmermann else if (!new_plane_state->visible) 4951baf9127SThomas Zimmermann return 0; 4961baf9127SThomas Zimmermann 4971baf9127SThomas Zimmermann if (plane->state) 4981baf9127SThomas Zimmermann fb = plane->state->fb; 4991baf9127SThomas Zimmermann 5001baf9127SThomas Zimmermann if (!fb || (fb->format != new_fb->format)) 5011baf9127SThomas Zimmermann new_crtc_state->mode_changed = true; /* update PLL settings */ 5021baf9127SThomas Zimmermann 5031baf9127SThomas Zimmermann new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state); 5041baf9127SThomas Zimmermann new_mgag200_crtc_state->format = new_fb->format; 5051baf9127SThomas Zimmermann 5061baf9127SThomas Zimmermann return 0; 5071baf9127SThomas Zimmermann } 5081baf9127SThomas Zimmermann 509bc835040SThomas Zimmermann void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 5101baf9127SThomas Zimmermann struct drm_atomic_state *old_state) 5111baf9127SThomas Zimmermann { 5121baf9127SThomas Zimmermann struct drm_device *dev = plane->dev; 5131baf9127SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 5141baf9127SThomas Zimmermann struct drm_plane_state *plane_state = plane->state; 5151baf9127SThomas Zimmermann struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane); 5161baf9127SThomas Zimmermann struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 5171baf9127SThomas Zimmermann struct drm_framebuffer *fb = plane_state->fb; 5181baf9127SThomas Zimmermann struct drm_atomic_helper_damage_iter iter; 5191baf9127SThomas Zimmermann struct drm_rect damage; 5201baf9127SThomas Zimmermann 5211baf9127SThomas Zimmermann drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 5221baf9127SThomas Zimmermann drm_atomic_for_each_plane_damage(&iter, &damage) { 5231baf9127SThomas Zimmermann mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage); 5241baf9127SThomas Zimmermann } 5251baf9127SThomas Zimmermann 5261baf9127SThomas Zimmermann /* Always scanout image at VRAM offset 0 */ 5271baf9127SThomas Zimmermann mgag200_set_startadd(mdev, (u32)0); 5281baf9127SThomas Zimmermann mgag200_set_offset(mdev, fb); 5292a742fd1SThomas Zimmermann } 5305cd062e3SThomas Zimmermann 5312a742fd1SThomas Zimmermann void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, 5322a742fd1SThomas Zimmermann struct drm_atomic_state *state) 5332a742fd1SThomas Zimmermann { 5342a742fd1SThomas Zimmermann struct drm_device *dev = plane->dev; 5352a742fd1SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 5362a742fd1SThomas Zimmermann u8 seq1; 5372a742fd1SThomas Zimmermann 5385cd062e3SThomas Zimmermann RREG_SEQ(0x01, seq1); 5395cd062e3SThomas Zimmermann seq1 &= ~MGAREG_SEQ1_SCROFF; 5405cd062e3SThomas Zimmermann WREG_SEQ(0x01, seq1); 5415cd062e3SThomas Zimmermann msleep(20); 5425cd062e3SThomas Zimmermann } 5431baf9127SThomas Zimmermann 544bc835040SThomas Zimmermann void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 5451baf9127SThomas Zimmermann struct drm_atomic_state *old_state) 5465cd062e3SThomas Zimmermann { 5475cd062e3SThomas Zimmermann struct drm_device *dev = plane->dev; 5485cd062e3SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 5495cd062e3SThomas Zimmermann u8 seq1; 5505cd062e3SThomas Zimmermann 5515cd062e3SThomas Zimmermann RREG_SEQ(0x01, seq1); 5525cd062e3SThomas Zimmermann seq1 |= MGAREG_SEQ1_SCROFF; 5535cd062e3SThomas Zimmermann WREG_SEQ(0x01, seq1); 5545cd062e3SThomas Zimmermann msleep(20); 5555cd062e3SThomas Zimmermann } 5561baf9127SThomas Zimmermann 5577e64f7c8SJocelyn Falempe int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 5587e64f7c8SJocelyn Falempe struct drm_scanout_buffer *sb) 5597e64f7c8SJocelyn Falempe { 5607e64f7c8SJocelyn Falempe struct mga_device *mdev = to_mga_device(plane->dev); 5617e64f7c8SJocelyn Falempe struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 5627e64f7c8SJocelyn Falempe 5637e64f7c8SJocelyn Falempe if (plane->state && plane->state->fb) { 5647e64f7c8SJocelyn Falempe sb->format = plane->state->fb->format; 5657e64f7c8SJocelyn Falempe sb->width = plane->state->fb->width; 5667e64f7c8SJocelyn Falempe sb->height = plane->state->fb->height; 5677e64f7c8SJocelyn Falempe sb->pitch[0] = plane->state->fb->pitches[0]; 5687e64f7c8SJocelyn Falempe sb->map[0] = map; 5697e64f7c8SJocelyn Falempe return 0; 5707e64f7c8SJocelyn Falempe } 5717e64f7c8SJocelyn Falempe return -ENODEV; 5727e64f7c8SJocelyn Falempe } 5737e64f7c8SJocelyn Falempe 5741baf9127SThomas Zimmermann /* 5751baf9127SThomas Zimmermann * CRTC 5761baf9127SThomas Zimmermann */ 5771baf9127SThomas Zimmermann 578bc835040SThomas Zimmermann enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 57988fabb75SThomas Zimmermann const struct drm_display_mode *mode) 58088fabb75SThomas Zimmermann { 5811baf9127SThomas Zimmermann struct mga_device *mdev = to_mga_device(crtc->dev); 58298da4b99SThomas Zimmermann const struct mgag200_device_info *info = mdev->info; 583475e2b97SThomas Zimmermann 58498da4b99SThomas Zimmermann /* 58598da4b99SThomas Zimmermann * Some devices have additional limits on the size of the 58698da4b99SThomas Zimmermann * display mode. 58798da4b99SThomas Zimmermann */ 58898da4b99SThomas Zimmermann if (mode->hdisplay > info->max_hdisplay) 589475e2b97SThomas Zimmermann return MODE_VIRTUAL_X; 59098da4b99SThomas Zimmermann if (mode->vdisplay > info->max_vdisplay) 591475e2b97SThomas Zimmermann return MODE_VIRTUAL_Y; 592475e2b97SThomas Zimmermann 593475e2b97SThomas Zimmermann if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 594475e2b97SThomas Zimmermann (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 595475e2b97SThomas Zimmermann return MODE_H_ILLEGAL; 596475e2b97SThomas Zimmermann } 597475e2b97SThomas Zimmermann 598475e2b97SThomas Zimmermann if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 599475e2b97SThomas Zimmermann mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 600475e2b97SThomas Zimmermann mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 601475e2b97SThomas Zimmermann mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 602475e2b97SThomas Zimmermann return MODE_BAD; 603475e2b97SThomas Zimmermann } 604475e2b97SThomas Zimmermann 60588fabb75SThomas Zimmermann return MODE_OK; 60688fabb75SThomas Zimmermann } 60788fabb75SThomas Zimmermann 608bc835040SThomas Zimmermann int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state) 60988fabb75SThomas Zimmermann { 61088fabb75SThomas Zimmermann struct drm_device *dev = crtc->dev; 61188fabb75SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 612877507bbSThomas Zimmermann const struct mgag200_device_funcs *funcs = mdev->funcs; 6131baf9127SThomas Zimmermann struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 6141baf9127SThomas Zimmermann struct drm_property_blob *new_gamma_lut = new_crtc_state->gamma_lut; 6151baf9127SThomas Zimmermann int ret; 6161baf9127SThomas Zimmermann 6171baf9127SThomas Zimmermann if (!new_crtc_state->enable) 6181baf9127SThomas Zimmermann return 0; 6191baf9127SThomas Zimmermann 6208f2fd57dSThomas Zimmermann ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state); 6218f2fd57dSThomas Zimmermann if (ret) 6228f2fd57dSThomas Zimmermann return ret; 6238f2fd57dSThomas Zimmermann 6241baf9127SThomas Zimmermann if (new_crtc_state->mode_changed) { 625877507bbSThomas Zimmermann if (funcs->pixpllc_atomic_check) { 626877507bbSThomas Zimmermann ret = funcs->pixpllc_atomic_check(crtc, new_state); 6271baf9127SThomas Zimmermann if (ret) 6281baf9127SThomas Zimmermann return ret; 6291baf9127SThomas Zimmermann } 630877507bbSThomas Zimmermann } 6311baf9127SThomas Zimmermann 6321baf9127SThomas Zimmermann if (new_crtc_state->color_mgmt_changed && new_gamma_lut) { 6331baf9127SThomas Zimmermann if (new_gamma_lut->length != MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 6341baf9127SThomas Zimmermann drm_dbg(dev, "Wrong size for gamma_lut %zu\n", new_gamma_lut->length); 6351baf9127SThomas Zimmermann return -EINVAL; 6361baf9127SThomas Zimmermann } 6371baf9127SThomas Zimmermann } 6381baf9127SThomas Zimmermann 6399cebffdfSJavier Martinez Canillas return 0; 6401baf9127SThomas Zimmermann } 6411baf9127SThomas Zimmermann 642bc835040SThomas Zimmermann void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 6431baf9127SThomas Zimmermann { 6441baf9127SThomas Zimmermann struct drm_crtc_state *crtc_state = crtc->state; 6451baf9127SThomas Zimmermann struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 6461baf9127SThomas Zimmermann struct drm_device *dev = crtc->dev; 6471baf9127SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 64889c6ea20SThomas Zimmermann struct drm_pending_vblank_event *event; 64989c6ea20SThomas Zimmermann unsigned long flags; 6501baf9127SThomas Zimmermann 6511baf9127SThomas Zimmermann if (crtc_state->enable && crtc_state->color_mgmt_changed) { 6521baf9127SThomas Zimmermann const struct drm_format_info *format = mgag200_crtc_state->format; 6531baf9127SThomas Zimmermann 6541baf9127SThomas Zimmermann if (crtc_state->gamma_lut) 6551baf9127SThomas Zimmermann mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data); 6561baf9127SThomas Zimmermann else 6571baf9127SThomas Zimmermann mgag200_crtc_set_gamma_linear(mdev, format); 6581baf9127SThomas Zimmermann } 65989c6ea20SThomas Zimmermann 66089c6ea20SThomas Zimmermann event = crtc->state->event; 66189c6ea20SThomas Zimmermann if (event) { 66289c6ea20SThomas Zimmermann crtc->state->event = NULL; 66389c6ea20SThomas Zimmermann 66489c6ea20SThomas Zimmermann spin_lock_irqsave(&dev->event_lock, flags); 66589c6ea20SThomas Zimmermann if (drm_crtc_vblank_get(crtc) != 0) 66689c6ea20SThomas Zimmermann drm_crtc_send_vblank_event(crtc, event); 66789c6ea20SThomas Zimmermann else 66889c6ea20SThomas Zimmermann drm_crtc_arm_vblank_event(crtc, event); 66989c6ea20SThomas Zimmermann spin_unlock_irqrestore(&dev->event_lock, flags); 67089c6ea20SThomas Zimmermann } 6711baf9127SThomas Zimmermann } 6721baf9127SThomas Zimmermann 673bc835040SThomas Zimmermann void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 6741baf9127SThomas Zimmermann { 6751baf9127SThomas Zimmermann struct drm_device *dev = crtc->dev; 6761baf9127SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 6778aeeb314SThomas Zimmermann const struct mgag200_device_funcs *funcs = mdev->funcs; 6781baf9127SThomas Zimmermann struct drm_crtc_state *crtc_state = crtc->state; 67988fabb75SThomas Zimmermann struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 6800a6dab7dSThomas Zimmermann struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 681ed2ef21fSThomas Zimmermann const struct drm_format_info *format = mgag200_crtc_state->format; 68288fabb75SThomas Zimmermann 683ed2ef21fSThomas Zimmermann mgag200_set_format_regs(mdev, format); 684cd3a2e8bSThomas Zimmermann mgag200_set_mode_regs(mdev, adjusted_mode, mgag200_crtc_state->set_vidrst); 6850a6dab7dSThomas Zimmermann 686877507bbSThomas Zimmermann if (funcs->pixpllc_atomic_update) 687877507bbSThomas Zimmermann funcs->pixpllc_atomic_update(crtc, old_state); 68888fabb75SThomas Zimmermann 689ad81e234SJocelyn Falempe if (crtc_state->gamma_lut) 690ad81e234SJocelyn Falempe mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data); 691ad81e234SJocelyn Falempe else 692ad81e234SJocelyn Falempe mgag200_crtc_set_gamma_linear(mdev, format); 693ad81e234SJocelyn Falempe 694895a4790SThomas Zimmermann mgag200_enable_display(mdev); 695913ec479SThomas Zimmermann 69689c6ea20SThomas Zimmermann drm_crtc_vblank_on(crtc); 69788fabb75SThomas Zimmermann } 69888fabb75SThomas Zimmermann 699bc835040SThomas Zimmermann void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state) 70088fabb75SThomas Zimmermann { 701153fef41SThomas Zimmermann struct mga_device *mdev = to_mga_device(crtc->dev); 70288fabb75SThomas Zimmermann 70389c6ea20SThomas Zimmermann drm_crtc_vblank_off(crtc); 70489c6ea20SThomas Zimmermann 705153fef41SThomas Zimmermann mgag200_disable_display(mdev); 70688fabb75SThomas Zimmermann } 70788fabb75SThomas Zimmermann 708*d5070c9bSThomas Zimmermann bool mgag200_crtc_helper_get_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, 709*d5070c9bSThomas Zimmermann int *vpos, int *hpos, 710*d5070c9bSThomas Zimmermann ktime_t *stime, ktime_t *etime, 711*d5070c9bSThomas Zimmermann const struct drm_display_mode *mode) 712*d5070c9bSThomas Zimmermann { 713*d5070c9bSThomas Zimmermann struct mga_device *mdev = to_mga_device(crtc->dev); 714*d5070c9bSThomas Zimmermann u32 vcount; 715*d5070c9bSThomas Zimmermann 716*d5070c9bSThomas Zimmermann if (stime) 717*d5070c9bSThomas Zimmermann *stime = ktime_get(); 718*d5070c9bSThomas Zimmermann 719*d5070c9bSThomas Zimmermann if (vpos) { 720*d5070c9bSThomas Zimmermann vcount = RREG32(MGAREG_VCOUNT); 721*d5070c9bSThomas Zimmermann *vpos = vcount & GENMASK(11, 0); 722*d5070c9bSThomas Zimmermann } 723*d5070c9bSThomas Zimmermann 724*d5070c9bSThomas Zimmermann if (hpos) 725*d5070c9bSThomas Zimmermann *hpos = mode->htotal >> 1; // near middle of scanline on average 726*d5070c9bSThomas Zimmermann 727*d5070c9bSThomas Zimmermann if (etime) 728*d5070c9bSThomas Zimmermann *etime = ktime_get(); 729*d5070c9bSThomas Zimmermann 730*d5070c9bSThomas Zimmermann return true; 731*d5070c9bSThomas Zimmermann } 732*d5070c9bSThomas Zimmermann 733bc835040SThomas Zimmermann void mgag200_crtc_reset(struct drm_crtc *crtc) 73488fabb75SThomas Zimmermann { 7351baf9127SThomas Zimmermann struct mgag200_crtc_state *mgag200_crtc_state; 73688fabb75SThomas Zimmermann 7371baf9127SThomas Zimmermann if (crtc->state) 7381baf9127SThomas Zimmermann crtc->funcs->atomic_destroy_state(crtc, crtc->state); 73988fabb75SThomas Zimmermann 7401baf9127SThomas Zimmermann mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL); 7411baf9127SThomas Zimmermann if (mgag200_crtc_state) 7421baf9127SThomas Zimmermann __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 7431baf9127SThomas Zimmermann else 7441baf9127SThomas Zimmermann __drm_atomic_helper_crtc_reset(crtc, NULL); 7450a6dab7dSThomas Zimmermann } 7460a6dab7dSThomas Zimmermann 747bc835040SThomas Zimmermann struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 74888fabb75SThomas Zimmermann { 74951b56939SThomas Zimmermann struct drm_crtc_state *crtc_state = crtc->state; 7500a6dab7dSThomas Zimmermann struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 75151b56939SThomas Zimmermann struct mgag200_crtc_state *new_mgag200_crtc_state; 75251b56939SThomas Zimmermann 75351b56939SThomas Zimmermann if (!crtc_state) 75451b56939SThomas Zimmermann return NULL; 75551b56939SThomas Zimmermann 75651b56939SThomas Zimmermann new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL); 75751b56939SThomas Zimmermann if (!new_mgag200_crtc_state) 75851b56939SThomas Zimmermann return NULL; 75951b56939SThomas Zimmermann __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 76051b56939SThomas Zimmermann 761ed2ef21fSThomas Zimmermann new_mgag200_crtc_state->format = mgag200_crtc_state->format; 7620a6dab7dSThomas Zimmermann memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 7630a6dab7dSThomas Zimmermann sizeof(new_mgag200_crtc_state->pixpllc)); 764cd3a2e8bSThomas Zimmermann new_mgag200_crtc_state->set_vidrst = mgag200_crtc_state->set_vidrst; 7650a6dab7dSThomas Zimmermann 76651b56939SThomas Zimmermann return &new_mgag200_crtc_state->base; 76751b56939SThomas Zimmermann } 76851b56939SThomas Zimmermann 769bc835040SThomas Zimmermann void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 77051b56939SThomas Zimmermann { 77151b56939SThomas Zimmermann struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 77251b56939SThomas Zimmermann 77351b56939SThomas Zimmermann __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 77451b56939SThomas Zimmermann kfree(mgag200_crtc_state); 77551b56939SThomas Zimmermann } 77651b56939SThomas Zimmermann 77789c6ea20SThomas Zimmermann int mgag200_crtc_enable_vblank(struct drm_crtc *crtc) 77889c6ea20SThomas Zimmermann { 77989c6ea20SThomas Zimmermann struct mga_device *mdev = to_mga_device(crtc->dev); 78089c6ea20SThomas Zimmermann u32 ien; 78189c6ea20SThomas Zimmermann 78289c6ea20SThomas Zimmermann WREG32(MGAREG_ICLEAR, MGAREG_ICLEAR_VLINEICLR); 78389c6ea20SThomas Zimmermann 78489c6ea20SThomas Zimmermann ien = RREG32(MGAREG_IEN); 78589c6ea20SThomas Zimmermann ien |= MGAREG_IEN_VLINEIEN; 78689c6ea20SThomas Zimmermann WREG32(MGAREG_IEN, ien); 78789c6ea20SThomas Zimmermann 78889c6ea20SThomas Zimmermann return 0; 78989c6ea20SThomas Zimmermann } 79089c6ea20SThomas Zimmermann 79189c6ea20SThomas Zimmermann void mgag200_crtc_disable_vblank(struct drm_crtc *crtc) 79289c6ea20SThomas Zimmermann { 79389c6ea20SThomas Zimmermann struct mga_device *mdev = to_mga_device(crtc->dev); 79489c6ea20SThomas Zimmermann u32 ien; 79589c6ea20SThomas Zimmermann 79689c6ea20SThomas Zimmermann ien = RREG32(MGAREG_IEN); 79789c6ea20SThomas Zimmermann ien &= ~(MGAREG_IEN_VLINEIEN); 79889c6ea20SThomas Zimmermann WREG32(MGAREG_IEN, ien); 79989c6ea20SThomas Zimmermann } 80089c6ea20SThomas Zimmermann 8014f4dc37eSThomas Zimmermann /* 80288fabb75SThomas Zimmermann * Mode config 80388fabb75SThomas Zimmermann */ 80488fabb75SThomas Zimmermann 8052d70b9a1SThomas Zimmermann static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state) 8062d70b9a1SThomas Zimmermann { 8072d70b9a1SThomas Zimmermann struct mga_device *mdev = to_mga_device(state->dev); 8082d70b9a1SThomas Zimmermann 8092d70b9a1SThomas Zimmermann /* 8102d70b9a1SThomas Zimmermann * Concurrent operations could possibly trigger a call to 8112d70b9a1SThomas Zimmermann * drm_connector_helper_funcs.get_modes by trying to read the 8122d70b9a1SThomas Zimmermann * display modes. Protect access to I/O registers by acquiring 8132d70b9a1SThomas Zimmermann * the I/O-register lock. 8142d70b9a1SThomas Zimmermann */ 8152d70b9a1SThomas Zimmermann mutex_lock(&mdev->rmmio_lock); 8162d70b9a1SThomas Zimmermann drm_atomic_helper_commit_tail(state); 8172d70b9a1SThomas Zimmermann mutex_unlock(&mdev->rmmio_lock); 8182d70b9a1SThomas Zimmermann } 8192d70b9a1SThomas Zimmermann 8202d70b9a1SThomas Zimmermann static const struct drm_mode_config_helper_funcs mgag200_mode_config_helper_funcs = { 8212d70b9a1SThomas Zimmermann .atomic_commit_tail = mgag200_mode_config_helper_atomic_commit_tail, 8222d70b9a1SThomas Zimmermann }; 8232d70b9a1SThomas Zimmermann 824475e2b97SThomas Zimmermann /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 825475e2b97SThomas Zimmermann static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 826475e2b97SThomas Zimmermann unsigned int bits_per_pixel) 827475e2b97SThomas Zimmermann { 828475e2b97SThomas Zimmermann uint32_t total_area, divisor; 829475e2b97SThomas Zimmermann uint64_t active_area, pixels_per_second, bandwidth; 830475e2b97SThomas Zimmermann uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 831475e2b97SThomas Zimmermann 832475e2b97SThomas Zimmermann divisor = 1024; 833475e2b97SThomas Zimmermann 834475e2b97SThomas Zimmermann if (!mode->htotal || !mode->vtotal || !mode->clock) 835475e2b97SThomas Zimmermann return 0; 836475e2b97SThomas Zimmermann 837475e2b97SThomas Zimmermann active_area = mode->hdisplay * mode->vdisplay; 838475e2b97SThomas Zimmermann total_area = mode->htotal * mode->vtotal; 839475e2b97SThomas Zimmermann 840475e2b97SThomas Zimmermann pixels_per_second = active_area * mode->clock * 1000; 841475e2b97SThomas Zimmermann do_div(pixels_per_second, total_area); 842475e2b97SThomas Zimmermann 843475e2b97SThomas Zimmermann bandwidth = pixels_per_second * bytes_per_pixel * 100; 844475e2b97SThomas Zimmermann do_div(bandwidth, divisor); 845475e2b97SThomas Zimmermann 846475e2b97SThomas Zimmermann return (uint32_t)bandwidth; 847475e2b97SThomas Zimmermann } 848475e2b97SThomas Zimmermann 84969340e52SThomas Zimmermann static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 85069340e52SThomas Zimmermann const struct drm_display_mode *mode) 85169340e52SThomas Zimmermann { 85269340e52SThomas Zimmermann static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 85369340e52SThomas Zimmermann struct mga_device *mdev = to_mga_device(dev); 85469340e52SThomas Zimmermann unsigned long fbsize, fbpages, max_fbpages; 85598da4b99SThomas Zimmermann const struct mgag200_device_info *info = mdev->info; 85669340e52SThomas Zimmermann 857d45e32c9SThomas Zimmermann max_fbpages = mdev->vram_available >> PAGE_SHIFT; 85869340e52SThomas Zimmermann 85969340e52SThomas Zimmermann fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 86069340e52SThomas Zimmermann fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 86169340e52SThomas Zimmermann 86269340e52SThomas Zimmermann if (fbpages > max_fbpages) 86369340e52SThomas Zimmermann return MODE_MEM; 86469340e52SThomas Zimmermann 86598da4b99SThomas Zimmermann /* 86698da4b99SThomas Zimmermann * Test the mode's required memory bandwidth if the device 86798da4b99SThomas Zimmermann * specifies a maximum. Not all devices do though. 86898da4b99SThomas Zimmermann */ 86998da4b99SThomas Zimmermann if (info->max_mem_bandwidth) { 87098da4b99SThomas Zimmermann uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8); 871475e2b97SThomas Zimmermann 87298da4b99SThomas Zimmermann if (mode_bandwidth > (info->max_mem_bandwidth * 1024)) 873475e2b97SThomas Zimmermann return MODE_BAD; 874475e2b97SThomas Zimmermann } 875475e2b97SThomas Zimmermann 87669340e52SThomas Zimmermann return MODE_OK; 87769340e52SThomas Zimmermann } 87869340e52SThomas Zimmermann 8795635b7cfSThomas Zimmermann static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 880913ec479SThomas Zimmermann .fb_create = drm_gem_fb_create_with_dirty, 88169340e52SThomas Zimmermann .mode_valid = mgag200_mode_config_mode_valid, 88288fabb75SThomas Zimmermann .atomic_check = drm_atomic_helper_check, 88388fabb75SThomas Zimmermann .atomic_commit = drm_atomic_helper_commit, 8845635b7cfSThomas Zimmermann }; 8855635b7cfSThomas Zimmermann 886bc835040SThomas Zimmermann int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available) 887414c4531SDave Airlie { 888832eddf5SThomas Zimmermann struct drm_device *dev = &mdev->base; 88903e44ad1SThomas Zimmermann int ret; 890414c4531SDave Airlie 891d45e32c9SThomas Zimmermann mdev->vram_available = vram_available; 892d45e32c9SThomas Zimmermann 8935635b7cfSThomas Zimmermann ret = drmm_mode_config_init(dev); 8945635b7cfSThomas Zimmermann if (ret) { 89544373151SThomas Zimmermann drm_err(dev, "drmm_mode_config_init() failed: %d\n", ret); 8965635b7cfSThomas Zimmermann return ret; 8975635b7cfSThomas Zimmermann } 8985635b7cfSThomas Zimmermann 899ed5877b6SThomas Zimmermann dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 900ed5877b6SThomas Zimmermann dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 90173f54d5dSThomas Zimmermann dev->mode_config.preferred_depth = 24; 9025635b7cfSThomas Zimmermann dev->mode_config.funcs = &mgag200_mode_config_funcs; 9032d70b9a1SThomas Zimmermann dev->mode_config.helper_private = &mgag200_mode_config_helper_funcs; 9045635b7cfSThomas Zimmermann 90544373151SThomas Zimmermann return 0; 90644373151SThomas Zimmermann } 907