1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/delay.h> 4 #include <linux/pci.h> 5 6 #include <drm/drm_atomic.h> 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_drv.h> 9 #include <drm/drm_gem_atomic_helper.h> 10 #include <drm/drm_print.h> 11 #include <drm/drm_probe_helper.h> 12 13 #include "mgag200_drv.h" 14 15 static void mgag200_g200ev_init_registers(struct mga_device *mdev) 16 { 17 static const u8 dacvalue[] = { 18 MGAG200_DAC_DEFAULT(0x00, 19 MGA1064_PIX_CLK_CTL_SEL_PLL, 20 MGA1064_MISC_CTL_VGA8 | MGA1064_MISC_CTL_DAC_RAM_CS, 21 0x00, 0x00, 0x00) 22 }; 23 24 size_t i; 25 26 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { 27 if ((i <= 0x17) || 28 (i == 0x1b) || 29 (i == 0x1c) || 30 ((i >= 0x1f) && (i <= 0x29)) || 31 ((i >= 0x30) && (i <= 0x37)) || 32 ((i >= 0x44) && (i <= 0x4e))) 33 continue; 34 WREG_DAC(i, dacvalue[i]); 35 } 36 37 mgag200_init_registers(mdev); 38 } 39 40 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev) 41 { 42 WREG_ECRT(0x06, 0x00); 43 } 44 45 /* 46 * PIXPLLC 47 */ 48 49 static int mgag200_g200ev_pixpllc_atomic_check(struct drm_crtc *crtc, 50 struct drm_atomic_state *new_state) 51 { 52 static const unsigned int vcomax = 550000; 53 static const unsigned int vcomin = 150000; 54 static const unsigned int pllreffreq = 50000; 55 56 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 57 struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state); 58 long clock = new_crtc_state->mode.clock; 59 struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc; 60 unsigned int delta, tmpdelta; 61 unsigned int testp, testm, testn; 62 unsigned int p, m, n, s; 63 unsigned int computed; 64 65 m = n = p = s = 0; 66 delta = 0xffffffff; 67 68 for (testp = 16; testp > 0; testp--) { 69 if (clock * testp > vcomax) 70 continue; 71 if (clock * testp < vcomin) 72 continue; 73 74 for (testn = 1; testn < 257; testn++) { 75 for (testm = 1; testm < 17; testm++) { 76 computed = (pllreffreq * testn) / 77 (testm * testp); 78 if (computed > clock) 79 tmpdelta = computed - clock; 80 else 81 tmpdelta = clock - computed; 82 if (tmpdelta < delta) { 83 delta = tmpdelta; 84 n = testn; 85 m = testm; 86 p = testp; 87 } 88 } 89 } 90 } 91 92 pixpllc->m = m; 93 pixpllc->n = n; 94 pixpllc->p = p; 95 pixpllc->s = s; 96 97 return 0; 98 } 99 100 static void mgag200_g200ev_pixpllc_atomic_update(struct drm_crtc *crtc, 101 struct drm_atomic_state *old_state) 102 { 103 struct drm_device *dev = crtc->dev; 104 struct mga_device *mdev = to_mga_device(dev); 105 struct drm_crtc_state *crtc_state = crtc->state; 106 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 107 struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc; 108 unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs; 109 u8 xpixpllcm, xpixpllcn, xpixpllcp, tmp; 110 111 pixpllcm = pixpllc->m - 1; 112 pixpllcn = pixpllc->n - 1; 113 pixpllcp = pixpllc->p - 1; 114 pixpllcs = pixpllc->s; 115 116 xpixpllcm = pixpllcm; 117 xpixpllcn = pixpllcn; 118 xpixpllcp = (pixpllcs << 3) | pixpllcp; 119 120 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK); 121 122 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 123 tmp = RREG8(DAC_DATA); 124 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; 125 WREG8(DAC_DATA, tmp); 126 127 tmp = RREG8(MGAREG_MEM_MISC_READ); 128 tmp |= 0x3 << 2; 129 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 130 131 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 132 tmp = RREG8(DAC_DATA); 133 WREG8(DAC_DATA, tmp & ~0x40); 134 135 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 136 tmp = RREG8(DAC_DATA); 137 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 138 WREG8(DAC_DATA, tmp); 139 140 WREG_DAC(MGA1064_EV_PIX_PLLC_M, xpixpllcm); 141 WREG_DAC(MGA1064_EV_PIX_PLLC_N, xpixpllcn); 142 WREG_DAC(MGA1064_EV_PIX_PLLC_P, xpixpllcp); 143 144 udelay(50); 145 146 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 147 tmp = RREG8(DAC_DATA); 148 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; 149 WREG8(DAC_DATA, tmp); 150 151 udelay(500); 152 153 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 154 tmp = RREG8(DAC_DATA); 155 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; 156 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; 157 WREG8(DAC_DATA, tmp); 158 159 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); 160 tmp = RREG8(DAC_DATA); 161 WREG8(DAC_DATA, tmp | 0x40); 162 163 tmp = RREG8(MGAREG_MEM_MISC_READ); 164 tmp |= (0x3 << 2); 165 WREG8(MGAREG_MEM_MISC_WRITE, tmp); 166 167 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); 168 tmp = RREG8(DAC_DATA); 169 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; 170 WREG8(DAC_DATA, tmp); 171 } 172 173 /* 174 * Mode-setting pipeline 175 */ 176 177 static const struct drm_plane_helper_funcs mgag200_g200ev_primary_plane_helper_funcs = { 178 MGAG200_PRIMARY_PLANE_HELPER_FUNCS, 179 }; 180 181 static const struct drm_plane_funcs mgag200_g200ev_primary_plane_funcs = { 182 MGAG200_PRIMARY_PLANE_FUNCS, 183 }; 184 185 static void mgag200_g200ev_crtc_helper_atomic_enable(struct drm_crtc *crtc, 186 struct drm_atomic_state *old_state) 187 { 188 struct drm_device *dev = crtc->dev; 189 struct mga_device *mdev = to_mga_device(dev); 190 const struct mgag200_device_funcs *funcs = mdev->funcs; 191 struct drm_crtc_state *crtc_state = crtc->state; 192 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 193 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 194 const struct drm_format_info *format = mgag200_crtc_state->format; 195 196 mgag200_set_format_regs(mdev, format); 197 mgag200_set_mode_regs(mdev, adjusted_mode, mgag200_crtc_state->set_vidrst); 198 199 if (funcs->pixpllc_atomic_update) 200 funcs->pixpllc_atomic_update(crtc, old_state); 201 202 mgag200_g200ev_set_hiprilvl(mdev); 203 204 if (crtc_state->gamma_lut) 205 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data); 206 else 207 mgag200_crtc_fill_gamma(mdev, format); 208 209 mgag200_enable_display(mdev); 210 } 211 212 static const struct drm_crtc_helper_funcs mgag200_g200ev_crtc_helper_funcs = { 213 .mode_valid = mgag200_crtc_helper_mode_valid, 214 .atomic_check = mgag200_crtc_helper_atomic_check, 215 .atomic_flush = mgag200_crtc_helper_atomic_flush, 216 .atomic_enable = mgag200_g200ev_crtc_helper_atomic_enable, 217 .atomic_disable = mgag200_crtc_helper_atomic_disable 218 }; 219 220 static const struct drm_crtc_funcs mgag200_g200ev_crtc_funcs = { 221 MGAG200_CRTC_FUNCS, 222 }; 223 224 static int mgag200_g200ev_pipeline_init(struct mga_device *mdev) 225 { 226 struct drm_device *dev = &mdev->base; 227 struct drm_plane *primary_plane = &mdev->primary_plane; 228 struct drm_crtc *crtc = &mdev->crtc; 229 int ret; 230 231 ret = drm_universal_plane_init(dev, primary_plane, 0, 232 &mgag200_g200ev_primary_plane_funcs, 233 mgag200_primary_plane_formats, 234 mgag200_primary_plane_formats_size, 235 mgag200_primary_plane_fmtmods, 236 DRM_PLANE_TYPE_PRIMARY, NULL); 237 if (ret) { 238 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret); 239 return ret; 240 } 241 drm_plane_helper_add(primary_plane, &mgag200_g200ev_primary_plane_helper_funcs); 242 drm_plane_enable_fb_damage_clips(primary_plane); 243 244 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 245 &mgag200_g200ev_crtc_funcs, NULL); 246 if (ret) { 247 drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n", ret); 248 return ret; 249 } 250 drm_crtc_helper_add(crtc, &mgag200_g200ev_crtc_helper_funcs); 251 252 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ 253 drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE); 254 drm_crtc_enable_color_mgmt(crtc, 0, false, MGAG200_LUT_SIZE); 255 256 ret = mgag200_vga_bmc_output_init(mdev); 257 if (ret) 258 return ret; 259 260 return 0; 261 } 262 263 /* 264 * DRM device 265 */ 266 267 static const struct mgag200_device_info mgag200_g200ev_device_info = 268 MGAG200_DEVICE_INFO_INIT(2048, 2048, 32700, false, 0, 1, false); 269 270 static const struct mgag200_device_funcs mgag200_g200ev_device_funcs = { 271 .pixpllc_atomic_check = mgag200_g200ev_pixpllc_atomic_check, 272 .pixpllc_atomic_update = mgag200_g200ev_pixpllc_atomic_update, 273 }; 274 275 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv) 276 { 277 struct mga_device *mdev; 278 struct drm_device *dev; 279 resource_size_t vram_available; 280 int ret; 281 282 mdev = devm_drm_dev_alloc(&pdev->dev, drv, struct mga_device, base); 283 if (IS_ERR(mdev)) 284 return mdev; 285 dev = &mdev->base; 286 287 pci_set_drvdata(pdev, dev); 288 289 ret = mgag200_init_pci_options(pdev, 0x00000120, 0x0000b000); 290 if (ret) 291 return ERR_PTR(ret); 292 293 ret = mgag200_device_preinit(mdev); 294 if (ret) 295 return ERR_PTR(ret); 296 297 ret = mgag200_device_init(mdev, &mgag200_g200ev_device_info, 298 &mgag200_g200ev_device_funcs); 299 if (ret) 300 return ERR_PTR(ret); 301 302 mgag200_g200ev_init_registers(mdev); 303 304 vram_available = mgag200_device_probe_vram(mdev); 305 306 ret = mgag200_mode_config_init(mdev, vram_available); 307 if (ret) 308 return ERR_PTR(ret); 309 310 ret = mgag200_g200ev_pipeline_init(mdev); 311 if (ret) 312 return ERR_PTR(ret); 313 314 drm_mode_config_reset(dev); 315 drm_kms_helper_poll_init(dev); 316 317 return mdev; 318 } 319