1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 #ifndef __MGAG200_DRV_H__ 11 #define __MGAG200_DRV_H__ 12 13 #include <video/vga.h> 14 15 #include <drm/drm_connector.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_encoder.h> 18 #include <drm/drm_gem.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_plane.h> 21 22 #include "mgag200_reg.h" 23 24 #define DRIVER_AUTHOR "Matthew Garrett" 25 26 #define DRIVER_NAME "mgag200" 27 #define DRIVER_DESC "MGA G200 SE" 28 #define DRIVER_DATE "20110418" 29 30 #define DRIVER_MAJOR 1 31 #define DRIVER_MINOR 0 32 #define DRIVER_PATCHLEVEL 0 33 34 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) 35 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) 36 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) 37 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) 38 39 #define MGA_BIOS_OFFSET 0x7ffc 40 41 #define ATTR_INDEX 0x1fc0 42 #define ATTR_DATA 0x1fc1 43 44 #define WREG_MISC(v) \ 45 WREG8(MGA_MISC_OUT, v) 46 47 #define RREG_MISC(v) \ 48 ((v) = RREG8(MGA_MISC_IN)) 49 50 #define WREG_MISC_MASKED(v, mask) \ 51 do { \ 52 u8 misc_; \ 53 u8 mask_ = (mask); \ 54 RREG_MISC(misc_); \ 55 misc_ &= ~mask_; \ 56 misc_ |= ((v) & mask_); \ 57 WREG_MISC(misc_); \ 58 } while (0) 59 60 #define WREG_ATTR(reg, v) \ 61 do { \ 62 RREG8(0x1fda); \ 63 WREG8(ATTR_INDEX, reg); \ 64 WREG8(ATTR_DATA, v); \ 65 } while (0) \ 66 67 #define RREG_SEQ(reg, v) \ 68 do { \ 69 WREG8(MGAREG_SEQ_INDEX, reg); \ 70 v = RREG8(MGAREG_SEQ_DATA); \ 71 } while (0) \ 72 73 #define WREG_SEQ(reg, v) \ 74 do { \ 75 WREG8(MGAREG_SEQ_INDEX, reg); \ 76 WREG8(MGAREG_SEQ_DATA, v); \ 77 } while (0) \ 78 79 #define RREG_CRT(reg, v) \ 80 do { \ 81 WREG8(MGAREG_CRTC_INDEX, reg); \ 82 v = RREG8(MGAREG_CRTC_DATA); \ 83 } while (0) \ 84 85 #define WREG_CRT(reg, v) \ 86 do { \ 87 WREG8(MGAREG_CRTC_INDEX, reg); \ 88 WREG8(MGAREG_CRTC_DATA, v); \ 89 } while (0) \ 90 91 #define RREG_ECRT(reg, v) \ 92 do { \ 93 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 94 v = RREG8(MGAREG_CRTCEXT_DATA); \ 95 } while (0) \ 96 97 #define WREG_ECRT(reg, v) \ 98 do { \ 99 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 100 WREG8(MGAREG_CRTCEXT_DATA, v); \ 101 } while (0) \ 102 103 #define GFX_INDEX 0x1fce 104 #define GFX_DATA 0x1fcf 105 106 #define WREG_GFX(reg, v) \ 107 do { \ 108 WREG8(GFX_INDEX, reg); \ 109 WREG8(GFX_DATA, v); \ 110 } while (0) \ 111 112 #define DAC_INDEX 0x3c00 113 #define DAC_DATA 0x3c0a 114 115 #define WREG_DAC(reg, v) \ 116 do { \ 117 WREG8(DAC_INDEX, reg); \ 118 WREG8(DAC_DATA, v); \ 119 } while (0) \ 120 121 #define MGA_MISC_OUT 0x1fc2 122 #define MGA_MISC_IN 0x1fcc 123 124 /* 125 * TODO: This is a pretty large set of default values for all kinds of 126 * settings. It should be split and set in the various DRM helpers, 127 * such as the CRTC reset or atomic_enable helpers. The PLL values 128 * probably belong to each model's PLL code. 129 */ 130 #define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \ 131 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \ 132 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 133 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 134 /* 0x18: */ (xvrefctrl), \ 135 /* 0x19: */ 0, \ 136 /* 0x1a: */ (xpixclkctrl), \ 137 /* 0x1b: */ 0xff, 0xbf, 0x20, \ 138 /* 0x1e: */ (xmiscctrl), \ 139 /* 0x1f: */ 0x20, \ 140 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ 141 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, \ 142 /* 0x2c: */ (xsyspllm), \ 143 /* 0x2d: */ (xsysplln), \ 144 /* 0x2e: */ (xsyspllp), \ 145 /* 0x2f: */ 0x40, \ 146 /* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \ 147 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \ 148 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 149 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \ 150 151 #define MGAG200_LUT_SIZE 256 152 153 #define MGAG200_MAX_FB_HEIGHT 4096 154 #define MGAG200_MAX_FB_WIDTH 4096 155 156 struct mga_device; 157 158 /* 159 * Stores parameters for programming the PLLs 160 * 161 * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz) 162 * Fo: output frequency 163 * Fvco = Fref * (N / M) 164 * Fo = Fvco / P 165 * 166 * S = [0..3] 167 */ 168 struct mgag200_pll_values { 169 unsigned int m; 170 unsigned int n; 171 unsigned int p; 172 unsigned int s; 173 }; 174 175 struct mgag200_crtc_state { 176 struct drm_crtc_state base; 177 178 /* Primary-plane format; required for modesetting and color mgmt. */ 179 const struct drm_format_info *format; 180 181 struct mgag200_pll_values pixpllc; 182 183 bool set_vidrst; 184 }; 185 186 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base) 187 { 188 return container_of(base, struct mgag200_crtc_state, base); 189 } 190 191 enum mga_type { 192 G200_PCI, 193 G200_AGP, 194 G200_SE_A, 195 G200_SE_B, 196 G200_WB, 197 G200_EV, 198 G200_EH, 199 G200_EH3, 200 G200_ER, 201 G200_EW3, 202 }; 203 204 struct mgag200_device_info { 205 u16 max_hdisplay; 206 u16 max_vdisplay; 207 208 /* 209 * Maximum memory bandwidth (MiB/sec). Setting this to zero disables 210 * the rsp test during mode validation. 211 */ 212 unsigned long max_mem_bandwidth; 213 214 /* Synchronize scanout with BMC */ 215 bool sync_bmc:1; 216 217 struct { 218 unsigned data_bit:3; 219 unsigned clock_bit:3; 220 } i2c; 221 222 /* 223 * HW does not handle 'startadd' register correctly. Always set 224 * it's value to 0. 225 */ 226 bool bug_no_startadd:1; 227 }; 228 229 #define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \ 230 _sync_bmc, _i2c_data_bit, _i2c_clock_bit, \ 231 _bug_no_startadd) \ 232 { \ 233 .max_hdisplay = (_max_hdisplay), \ 234 .max_vdisplay = (_max_vdisplay), \ 235 .max_mem_bandwidth = (_max_mem_bandwidth), \ 236 .sync_bmc = (_sync_bmc), \ 237 .i2c = { \ 238 .data_bit = (_i2c_data_bit), \ 239 .clock_bit = (_i2c_clock_bit), \ 240 }, \ 241 .bug_no_startadd = (_bug_no_startadd), \ 242 } 243 244 struct mgag200_device_funcs { 245 /* 246 * Validate that the given state can be programmed into PIXPLLC. On 247 * success, the calculated parameters should be stored in the CRTC's 248 * state in struct @mgag200_crtc_state.pixpllc. 249 */ 250 int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state); 251 252 /* 253 * Program PIXPLLC from the CRTC state. The parameters should have been 254 * stored in struct @mgag200_crtc_state.pixpllc by the corresponding 255 * implementation of @pixpllc_atomic_check. 256 */ 257 void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 258 }; 259 260 struct mga_device { 261 struct drm_device base; 262 263 const struct mgag200_device_info *info; 264 const struct mgag200_device_funcs *funcs; 265 266 struct resource *rmmio_res; 267 void __iomem *rmmio; 268 struct mutex rmmio_lock; /* Protects access to rmmio */ 269 270 struct resource *vram_res; 271 void __iomem *vram; 272 resource_size_t vram_available; 273 274 struct drm_plane primary_plane; 275 struct drm_crtc crtc; 276 struct { 277 struct { 278 struct drm_encoder encoder; 279 struct drm_connector connector; 280 } vga; 281 } output; 282 }; 283 284 static inline struct mga_device *to_mga_device(struct drm_device *dev) 285 { 286 return container_of(dev, struct mga_device, base); 287 } 288 289 struct mgag200_g200_device { 290 struct mga_device base; 291 292 /* PLL constants */ 293 long ref_clk; 294 long pclk_min; 295 long pclk_max; 296 }; 297 298 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev) 299 { 300 return container_of(to_mga_device(dev), struct mgag200_g200_device, base); 301 } 302 303 struct mgag200_g200se_device { 304 struct mga_device base; 305 306 /* SE model number stored in reg 0x1e24 */ 307 u32 unique_rev_id; 308 }; 309 310 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev) 311 { 312 return container_of(to_mga_device(dev), struct mgag200_g200se_device, base); 313 } 314 315 /* mgag200_drv.c */ 316 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2); 317 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size); 318 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); 319 int mgag200_device_preinit(struct mga_device *mdev); 320 int mgag200_device_init(struct mga_device *mdev, 321 const struct mgag200_device_info *info, 322 const struct mgag200_device_funcs *funcs); 323 324 /* mgag200_<device type>.c */ 325 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 326 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 327 enum mga_type type); 328 void mgag200_g200wb_init_registers(struct mga_device *mdev); 329 void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 330 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 331 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 332 void mgag200_g200eh_init_registers(struct mga_device *mdev); 333 void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 334 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, 335 const struct drm_driver *drv); 336 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, 337 const struct drm_driver *drv); 338 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, 339 const struct drm_driver *drv); 340 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, 341 const struct drm_driver *drv); 342 343 /* 344 * mgag200_mode.c 345 */ 346 347 struct drm_crtc; 348 struct drm_crtc_state; 349 struct drm_display_mode; 350 struct drm_plane; 351 struct drm_atomic_state; 352 struct drm_scanout_buffer; 353 354 extern const uint32_t mgag200_primary_plane_formats[]; 355 extern const size_t mgag200_primary_plane_formats_size; 356 extern const uint64_t mgag200_primary_plane_fmtmods[]; 357 358 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 359 struct drm_atomic_state *new_state); 360 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 361 struct drm_atomic_state *old_state); 362 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, 363 struct drm_atomic_state *state); 364 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 365 struct drm_atomic_state *old_state); 366 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 367 struct drm_scanout_buffer *sb); 368 369 #define MGAG200_PRIMARY_PLANE_HELPER_FUNCS \ 370 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \ 371 .atomic_check = mgag200_primary_plane_helper_atomic_check, \ 372 .atomic_update = mgag200_primary_plane_helper_atomic_update, \ 373 .atomic_enable = mgag200_primary_plane_helper_atomic_enable, \ 374 .atomic_disable = mgag200_primary_plane_helper_atomic_disable, \ 375 .get_scanout_buffer = mgag200_primary_plane_helper_get_scanout_buffer 376 377 #define MGAG200_PRIMARY_PLANE_FUNCS \ 378 .update_plane = drm_atomic_helper_update_plane, \ 379 .disable_plane = drm_atomic_helper_disable_plane, \ 380 .destroy = drm_plane_cleanup, \ 381 DRM_GEM_SHADOW_PLANE_FUNCS 382 383 void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, const struct drm_format_info *format); 384 void mgag200_crtc_set_gamma(struct mga_device *mdev, 385 const struct drm_format_info *format, 386 struct drm_color_lut *lut); 387 388 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 389 const struct drm_display_mode *mode); 390 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state); 391 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 392 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 393 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 394 bool mgag200_crtc_helper_get_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, 395 int *vpos, int *hpos, 396 ktime_t *stime, ktime_t *etime, 397 const struct drm_display_mode *mode); 398 399 #define MGAG200_CRTC_HELPER_FUNCS \ 400 .mode_valid = mgag200_crtc_helper_mode_valid, \ 401 .atomic_check = mgag200_crtc_helper_atomic_check, \ 402 .atomic_flush = mgag200_crtc_helper_atomic_flush, \ 403 .atomic_enable = mgag200_crtc_helper_atomic_enable, \ 404 .atomic_disable = mgag200_crtc_helper_atomic_disable, \ 405 .get_scanout_position = mgag200_crtc_helper_get_scanout_position 406 407 void mgag200_crtc_reset(struct drm_crtc *crtc); 408 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc); 409 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); 410 int mgag200_crtc_enable_vblank(struct drm_crtc *crtc); 411 void mgag200_crtc_disable_vblank(struct drm_crtc *crtc); 412 413 #define MGAG200_CRTC_FUNCS \ 414 .reset = mgag200_crtc_reset, \ 415 .destroy = drm_crtc_cleanup, \ 416 .set_config = drm_atomic_helper_set_config, \ 417 .page_flip = drm_atomic_helper_page_flip, \ 418 .atomic_duplicate_state = mgag200_crtc_atomic_duplicate_state, \ 419 .atomic_destroy_state = mgag200_crtc_atomic_destroy_state, \ 420 .enable_vblank = mgag200_crtc_enable_vblank, \ 421 .disable_vblank = mgag200_crtc_disable_vblank, \ 422 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp 423 424 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode, 425 bool set_vidrst); 426 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format); 427 void mgag200_enable_display(struct mga_device *mdev); 428 void mgag200_init_registers(struct mga_device *mdev); 429 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available); 430 431 /* mgag200_vga_bmc.c */ 432 int mgag200_vga_bmc_output_init(struct mga_device *mdev); 433 434 /* mgag200_vga.c */ 435 int mgag200_vga_output_init(struct mga_device *mdev); 436 437 /* mgag200_bmc.c */ 438 void mgag200_bmc_stop_scanout(struct mga_device *mdev); 439 void mgag200_bmc_start_scanout(struct mga_device *mdev); 440 441 #endif /* __MGAG200_DRV_H__ */ 442