1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 #ifndef __MGAG200_DRV_H__ 11 #define __MGAG200_DRV_H__ 12 13 #include <linux/i2c-algo-bit.h> 14 #include <linux/i2c.h> 15 16 #include <video/vga.h> 17 18 #include <drm/drm_encoder.h> 19 #include <drm/drm_fb_helper.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_shmem_helper.h> 22 #include <drm/drm_simple_kms_helper.h> 23 24 #include "mgag200_reg.h" 25 26 #define DRIVER_AUTHOR "Matthew Garrett" 27 28 #define DRIVER_NAME "mgag200" 29 #define DRIVER_DESC "MGA G200 SE" 30 #define DRIVER_DATE "20110418" 31 32 #define DRIVER_MAJOR 1 33 #define DRIVER_MINOR 0 34 #define DRIVER_PATCHLEVEL 0 35 36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) 37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) 38 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) 39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) 40 41 #define MGA_BIOS_OFFSET 0x7ffc 42 43 #define ATTR_INDEX 0x1fc0 44 #define ATTR_DATA 0x1fc1 45 46 #define WREG_MISC(v) \ 47 WREG8(MGA_MISC_OUT, v) 48 49 #define RREG_MISC(v) \ 50 ((v) = RREG8(MGA_MISC_IN)) 51 52 #define WREG_MISC_MASKED(v, mask) \ 53 do { \ 54 u8 misc_; \ 55 u8 mask_ = (mask); \ 56 RREG_MISC(misc_); \ 57 misc_ &= ~mask_; \ 58 misc_ |= ((v) & mask_); \ 59 WREG_MISC(misc_); \ 60 } while (0) 61 62 #define WREG_ATTR(reg, v) \ 63 do { \ 64 RREG8(0x1fda); \ 65 WREG8(ATTR_INDEX, reg); \ 66 WREG8(ATTR_DATA, v); \ 67 } while (0) \ 68 69 #define RREG_SEQ(reg, v) \ 70 do { \ 71 WREG8(MGAREG_SEQ_INDEX, reg); \ 72 v = RREG8(MGAREG_SEQ_DATA); \ 73 } while (0) \ 74 75 #define WREG_SEQ(reg, v) \ 76 do { \ 77 WREG8(MGAREG_SEQ_INDEX, reg); \ 78 WREG8(MGAREG_SEQ_DATA, v); \ 79 } while (0) \ 80 81 #define RREG_CRT(reg, v) \ 82 do { \ 83 WREG8(MGAREG_CRTC_INDEX, reg); \ 84 v = RREG8(MGAREG_CRTC_DATA); \ 85 } while (0) \ 86 87 #define WREG_CRT(reg, v) \ 88 do { \ 89 WREG8(MGAREG_CRTC_INDEX, reg); \ 90 WREG8(MGAREG_CRTC_DATA, v); \ 91 } while (0) \ 92 93 #define RREG_ECRT(reg, v) \ 94 do { \ 95 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 96 v = RREG8(MGAREG_CRTCEXT_DATA); \ 97 } while (0) \ 98 99 #define WREG_ECRT(reg, v) \ 100 do { \ 101 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 102 WREG8(MGAREG_CRTCEXT_DATA, v); \ 103 } while (0) \ 104 105 #define GFX_INDEX 0x1fce 106 #define GFX_DATA 0x1fcf 107 108 #define WREG_GFX(reg, v) \ 109 do { \ 110 WREG8(GFX_INDEX, reg); \ 111 WREG8(GFX_DATA, v); \ 112 } while (0) \ 113 114 #define DAC_INDEX 0x3c00 115 #define DAC_DATA 0x3c0a 116 117 #define WREG_DAC(reg, v) \ 118 do { \ 119 WREG8(DAC_INDEX, reg); \ 120 WREG8(DAC_DATA, v); \ 121 } while (0) \ 122 123 #define MGA_MISC_OUT 0x1fc2 124 #define MGA_MISC_IN 0x1fcc 125 126 #define MGAG200_MAX_FB_HEIGHT 4096 127 #define MGAG200_MAX_FB_WIDTH 4096 128 129 struct mga_device; 130 struct mgag200_pll; 131 132 /* 133 * Stores parameters for programming the PLLs 134 * 135 * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz) 136 * Fo: output frequency 137 * Fvco = Fref * (N / M) 138 * Fo = Fvco / P 139 * 140 * S = [0..3] 141 */ 142 struct mgag200_pll_values { 143 unsigned int m; 144 unsigned int n; 145 unsigned int p; 146 unsigned int s; 147 }; 148 149 struct mgag200_pll_funcs { 150 int (*compute)(struct mgag200_pll *pll, long clock, struct mgag200_pll_values *pllc); 151 void (*update)(struct mgag200_pll *pll, const struct mgag200_pll_values *pllc); 152 }; 153 154 struct mgag200_pll { 155 struct mga_device *mdev; 156 157 const struct mgag200_pll_funcs *funcs; 158 }; 159 160 struct mgag200_crtc_state { 161 struct drm_crtc_state base; 162 163 struct mgag200_pll_values pixpllc; 164 }; 165 166 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base) 167 { 168 return container_of(base, struct mgag200_crtc_state, base); 169 } 170 171 struct mga_i2c_chan { 172 struct i2c_adapter adapter; 173 struct drm_device *dev; 174 struct i2c_algo_bit_data bit; 175 int data, clock; 176 }; 177 178 struct mga_mc { 179 resource_size_t vram_size; 180 resource_size_t vram_base; 181 resource_size_t vram_window; 182 }; 183 184 enum mga_type { 185 G200_PCI, 186 G200_AGP, 187 G200_SE_A, 188 G200_SE_B, 189 G200_WB, 190 G200_EV, 191 G200_EH, 192 G200_EH3, 193 G200_ER, 194 G200_EW3, 195 }; 196 197 /* HW does not handle 'startadd' field correct. */ 198 #define MGAG200_FLAG_HW_BUG_NO_STARTADD (1ul << 8) 199 200 #define MGAG200_TYPE_MASK (0x000000ff) 201 #define MGAG200_FLAG_MASK (0x00ffff00) 202 203 #define IS_G200_SE(mdev) (mdev->type == G200_SE_A || mdev->type == G200_SE_B) 204 205 struct mga_device { 206 struct drm_device base; 207 unsigned long flags; 208 209 struct mutex rmmio_lock; /* Protects access to rmmio */ 210 resource_size_t rmmio_base; 211 resource_size_t rmmio_size; 212 void __iomem *rmmio; 213 214 struct mga_mc mc; 215 216 void __iomem *vram; 217 resource_size_t vram_available; 218 219 enum mga_type type; 220 221 struct mgag200_pll pixpll; 222 struct mga_i2c_chan i2c; 223 struct drm_connector connector; 224 struct drm_simple_display_pipe display_pipe; 225 }; 226 227 static inline struct mga_device *to_mga_device(struct drm_device *dev) 228 { 229 return container_of(dev, struct mga_device, base); 230 } 231 232 struct mgag200_g200_device { 233 struct mga_device base; 234 235 /* PLL constants */ 236 long ref_clk; 237 long pclk_min; 238 long pclk_max; 239 }; 240 241 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev) 242 { 243 return container_of(to_mga_device(dev), struct mgag200_g200_device, base); 244 } 245 246 struct mgag200_g200se_device { 247 struct mga_device base; 248 249 /* SE model number stored in reg 0x1e24 */ 250 u32 unique_rev_id; 251 }; 252 253 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev) 254 { 255 return container_of(to_mga_device(dev), struct mgag200_g200se_device, base); 256 } 257 258 /* mgag200_drv.c */ 259 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2); 260 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size); 261 int mgag200_regs_init(struct mga_device *mdev); 262 263 /* mgag200_<device type>.c */ 264 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 265 enum mga_type type, unsigned long flags); 266 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 267 enum mga_type type, unsigned long flags); 268 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 269 enum mga_type type, unsigned long flags); 270 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 271 enum mga_type type, unsigned long flags); 272 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 273 enum mga_type type, unsigned long flags); 274 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 275 enum mga_type type, unsigned long flags); 276 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 277 enum mga_type type, unsigned long flags); 278 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 279 enum mga_type type, unsigned long flags); 280 281 /* mgag200_mode.c */ 282 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); 283 int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_fb_available); 284 285 /* mgag200_i2c.c */ 286 int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c); 287 288 /* mgag200_mm.c */ 289 int mgag200_mm_init(struct mga_device *mdev); 290 291 /* mgag200_pll.c */ 292 int mgag200_pixpll_init(struct mgag200_pll *pixpll, struct mga_device *mdev); 293 294 #endif /* __MGAG200_DRV_H__ */ 295