xref: /linux/drivers/gpu/drm/mgag200/mgag200_drv.h (revision a1c3be890440a1769ed6f822376a3e3ab0d42994) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright 2010 Matt Turner.
4  * Copyright 2012 Red Hat
5  *
6  * Authors: Matthew Garrett
7  * 	    Matt Turner
8  *	    Dave Airlie
9  */
10 #ifndef __MGAG200_DRV_H__
11 #define __MGAG200_DRV_H__
12 
13 #include <linux/i2c-algo-bit.h>
14 #include <linux/i2c.h>
15 
16 #include <video/vga.h>
17 
18 #include <drm/drm_encoder.h>
19 #include <drm/drm_fb_helper.h>
20 #include <drm/drm_gem.h>
21 #include <drm/drm_gem_shmem_helper.h>
22 #include <drm/drm_simple_kms_helper.h>
23 
24 #include "mgag200_reg.h"
25 
26 #define DRIVER_AUTHOR		"Matthew Garrett"
27 
28 #define DRIVER_NAME		"mgag200"
29 #define DRIVER_DESC		"MGA G200 SE"
30 #define DRIVER_DATE		"20110418"
31 
32 #define DRIVER_MAJOR		1
33 #define DRIVER_MINOR		0
34 #define DRIVER_PATCHLEVEL	0
35 
36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
38 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
40 
41 #define MGA_BIOS_OFFSET		0x7ffc
42 
43 #define ATTR_INDEX 0x1fc0
44 #define ATTR_DATA 0x1fc1
45 
46 #define WREG_ATTR(reg, v)					\
47 	do {							\
48 		RREG8(0x1fda);					\
49 		WREG8(ATTR_INDEX, reg);				\
50 		WREG8(ATTR_DATA, v);				\
51 	} while (0)						\
52 
53 #define RREG_SEQ(reg, v)					\
54 	do {							\
55 		WREG8(MGAREG_SEQ_INDEX, reg);			\
56 		v = RREG8(MGAREG_SEQ_DATA);			\
57 	} while (0)						\
58 
59 #define WREG_SEQ(reg, v)					\
60 	do {							\
61 		WREG8(MGAREG_SEQ_INDEX, reg);			\
62 		WREG8(MGAREG_SEQ_DATA, v);			\
63 	} while (0)						\
64 
65 #define RREG_CRT(reg, v)					\
66 	do {							\
67 		WREG8(MGAREG_CRTC_INDEX, reg);			\
68 		v = RREG8(MGAREG_CRTC_DATA);			\
69 	} while (0)						\
70 
71 #define WREG_CRT(reg, v)					\
72 	do {							\
73 		WREG8(MGAREG_CRTC_INDEX, reg);			\
74 		WREG8(MGAREG_CRTC_DATA, v);			\
75 	} while (0)						\
76 
77 #define RREG_ECRT(reg, v)					\
78 	do {							\
79 		WREG8(MGAREG_CRTCEXT_INDEX, reg);		\
80 		v = RREG8(MGAREG_CRTCEXT_DATA);			\
81 	} while (0)						\
82 
83 #define WREG_ECRT(reg, v)					\
84 	do {							\
85 		WREG8(MGAREG_CRTCEXT_INDEX, reg);				\
86 		WREG8(MGAREG_CRTCEXT_DATA, v);				\
87 	} while (0)						\
88 
89 #define GFX_INDEX 0x1fce
90 #define GFX_DATA 0x1fcf
91 
92 #define WREG_GFX(reg, v)					\
93 	do {							\
94 		WREG8(GFX_INDEX, reg);				\
95 		WREG8(GFX_DATA, v);				\
96 	} while (0)						\
97 
98 #define DAC_INDEX 0x3c00
99 #define DAC_DATA 0x3c0a
100 
101 #define WREG_DAC(reg, v)					\
102 	do {							\
103 		WREG8(DAC_INDEX, reg);				\
104 		WREG8(DAC_DATA, v);				\
105 	} while (0)						\
106 
107 #define MGA_MISC_OUT 0x1fc2
108 #define MGA_MISC_IN 0x1fcc
109 
110 #define MGAG200_MAX_FB_HEIGHT 4096
111 #define MGAG200_MAX_FB_WIDTH 4096
112 
113 #define to_mga_connector(x) container_of(x, struct mga_connector, base)
114 
115 struct mga_i2c_chan {
116 	struct i2c_adapter adapter;
117 	struct drm_device *dev;
118 	struct i2c_algo_bit_data bit;
119 	int data, clock;
120 };
121 
122 struct mga_connector {
123 	struct drm_connector base;
124 	struct mga_i2c_chan *i2c;
125 };
126 
127 struct mga_mc {
128 	resource_size_t			vram_size;
129 	resource_size_t			vram_base;
130 	resource_size_t			vram_window;
131 };
132 
133 enum mga_type {
134 	G200_PCI,
135 	G200_AGP,
136 	G200_SE_A,
137 	G200_SE_B,
138 	G200_WB,
139 	G200_EV,
140 	G200_EH,
141 	G200_EH3,
142 	G200_ER,
143 	G200_EW3,
144 };
145 
146 /* HW does not handle 'startadd' field correct. */
147 #define MGAG200_FLAG_HW_BUG_NO_STARTADD	(1ul << 8)
148 
149 #define MGAG200_TYPE_MASK	(0x000000ff)
150 #define MGAG200_FLAG_MASK	(0x00ffff00)
151 
152 #define IS_G200_SE(mdev) (mdev->type == G200_SE_A || mdev->type == G200_SE_B)
153 
154 struct mga_device {
155 	struct drm_device		base;
156 	unsigned long			flags;
157 
158 	resource_size_t			rmmio_base;
159 	resource_size_t			rmmio_size;
160 	void __iomem			*rmmio;
161 
162 	struct mga_mc			mc;
163 
164 	void __iomem			*vram;
165 	size_t				vram_fb_available;
166 
167 	enum mga_type			type;
168 
169 	int bpp_shifts[4];
170 
171 	int fb_mtrr;
172 
173 	union {
174 		struct {
175 			long ref_clk;
176 			long pclk_min;
177 			long pclk_max;
178 		} g200;
179 		struct {
180 			/* SE model number stored in reg 0x1e24 */
181 			u32 unique_rev_id;
182 		} g200se;
183 	} model;
184 
185 
186 	struct mga_connector connector;
187 	struct drm_simple_display_pipe display_pipe;
188 };
189 
190 static inline struct mga_device *to_mga_device(struct drm_device *dev)
191 {
192 	return container_of(dev, struct mga_device, base);
193 }
194 
195 static inline enum mga_type
196 mgag200_type_from_driver_data(kernel_ulong_t driver_data)
197 {
198 	return (enum mga_type)(driver_data & MGAG200_TYPE_MASK);
199 }
200 
201 static inline unsigned long
202 mgag200_flags_from_driver_data(kernel_ulong_t driver_data)
203 {
204 	return driver_data & MGAG200_FLAG_MASK;
205 }
206 
207 				/* mgag200_mode.c */
208 int mgag200_modeset_init(struct mga_device *mdev);
209 
210 				/* mgag200_i2c.c */
211 struct mga_i2c_chan *mgag200_i2c_create(struct drm_device *dev);
212 void mgag200_i2c_destroy(struct mga_i2c_chan *i2c);
213 
214 				/* mgag200_mm.c */
215 int mgag200_mm_init(struct mga_device *mdev);
216 
217 #endif				/* __MGAG200_DRV_H__ */
218