1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 #ifndef __MGAG200_DRV_H__ 11 #define __MGAG200_DRV_H__ 12 13 #include <video/vga.h> 14 15 #include <drm/drm_connector.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_encoder.h> 18 #include <drm/drm_gem.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_plane.h> 21 22 #include "mgag200_reg.h" 23 24 #define DRIVER_AUTHOR "Matthew Garrett" 25 26 #define DRIVER_NAME "mgag200" 27 #define DRIVER_DESC "MGA G200 SE" 28 29 #define DRIVER_MAJOR 1 30 #define DRIVER_MINOR 0 31 #define DRIVER_PATCHLEVEL 0 32 33 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) 34 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) 35 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) 36 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) 37 38 #define MGA_BIOS_OFFSET 0x7ffc 39 40 #define ATTR_INDEX 0x1fc0 41 #define ATTR_DATA 0x1fc1 42 43 #define WREG_MISC(v) \ 44 WREG8(MGA_MISC_OUT, v) 45 46 #define RREG_MISC(v) \ 47 ((v) = RREG8(MGA_MISC_IN)) 48 49 #define WREG_MISC_MASKED(v, mask) \ 50 do { \ 51 u8 misc_; \ 52 u8 mask_ = (mask); \ 53 RREG_MISC(misc_); \ 54 misc_ &= ~mask_; \ 55 misc_ |= ((v) & mask_); \ 56 WREG_MISC(misc_); \ 57 } while (0) 58 59 #define WREG_ATTR(reg, v) \ 60 do { \ 61 RREG8(0x1fda); \ 62 WREG8(ATTR_INDEX, reg); \ 63 WREG8(ATTR_DATA, v); \ 64 } while (0) \ 65 66 #define RREG_SEQ(reg, v) \ 67 do { \ 68 WREG8(MGAREG_SEQ_INDEX, reg); \ 69 v = RREG8(MGAREG_SEQ_DATA); \ 70 } while (0) \ 71 72 #define WREG_SEQ(reg, v) \ 73 do { \ 74 WREG8(MGAREG_SEQ_INDEX, reg); \ 75 WREG8(MGAREG_SEQ_DATA, v); \ 76 } while (0) \ 77 78 #define RREG_CRT(reg, v) \ 79 do { \ 80 WREG8(MGAREG_CRTC_INDEX, reg); \ 81 v = RREG8(MGAREG_CRTC_DATA); \ 82 } while (0) \ 83 84 #define WREG_CRT(reg, v) \ 85 do { \ 86 WREG8(MGAREG_CRTC_INDEX, reg); \ 87 WREG8(MGAREG_CRTC_DATA, v); \ 88 } while (0) \ 89 90 #define RREG_ECRT(reg, v) \ 91 do { \ 92 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 93 v = RREG8(MGAREG_CRTCEXT_DATA); \ 94 } while (0) \ 95 96 #define WREG_ECRT(reg, v) \ 97 do { \ 98 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 99 WREG8(MGAREG_CRTCEXT_DATA, v); \ 100 } while (0) \ 101 102 #define GFX_INDEX 0x1fce 103 #define GFX_DATA 0x1fcf 104 105 #define WREG_GFX(reg, v) \ 106 do { \ 107 WREG8(GFX_INDEX, reg); \ 108 WREG8(GFX_DATA, v); \ 109 } while (0) \ 110 111 #define DAC_INDEX 0x3c00 112 #define DAC_DATA 0x3c0a 113 114 #define RREG_DAC(reg) \ 115 ({ \ 116 WREG8(DAC_INDEX, reg); \ 117 RREG8(DAC_DATA); \ 118 }) \ 119 120 #define WREG_DAC(reg, v) \ 121 do { \ 122 WREG8(DAC_INDEX, reg); \ 123 WREG8(DAC_DATA, v); \ 124 } while (0) \ 125 126 #define MGA_MISC_OUT 0x1fc2 127 #define MGA_MISC_IN 0x1fcc 128 129 /* 130 * TODO: This is a pretty large set of default values for all kinds of 131 * settings. It should be split and set in the various DRM helpers, 132 * such as the CRTC reset or atomic_enable helpers. The PLL values 133 * probably belong to each model's PLL code. 134 */ 135 #define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \ 136 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \ 137 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 138 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 139 /* 0x18: */ (xvrefctrl), \ 140 /* 0x19: */ 0, \ 141 /* 0x1a: */ (xpixclkctrl), \ 142 /* 0x1b: */ 0xff, 0xbf, 0x20, \ 143 /* 0x1e: */ (xmiscctrl), \ 144 /* 0x1f: */ 0x20, \ 145 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ 146 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, \ 147 /* 0x2c: */ (xsyspllm), \ 148 /* 0x2d: */ (xsysplln), \ 149 /* 0x2e: */ (xsyspllp), \ 150 /* 0x2f: */ 0x40, \ 151 /* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \ 152 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \ 153 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \ 154 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \ 155 156 #define MGAG200_LUT_SIZE 256 157 158 #define MGAG200_MAX_FB_HEIGHT 4096 159 #define MGAG200_MAX_FB_WIDTH 4096 160 161 struct mga_device; 162 163 /* 164 * Stores parameters for programming the PLLs 165 * 166 * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz) 167 * Fo: output frequency 168 * Fvco = Fref * (N / M) 169 * Fo = Fvco / P 170 * 171 * S = [0..3] 172 */ 173 struct mgag200_pll_values { 174 unsigned int m; 175 unsigned int n; 176 unsigned int p; 177 unsigned int s; 178 }; 179 180 struct mgag200_crtc_state { 181 struct drm_crtc_state base; 182 183 /* Primary-plane format; required for modesetting and color mgmt. */ 184 const struct drm_format_info *format; 185 186 struct mgag200_pll_values pixpllc; 187 188 bool set_vidrst; 189 }; 190 191 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base) 192 { 193 return container_of(base, struct mgag200_crtc_state, base); 194 } 195 196 enum mga_type { 197 G200_PCI, 198 G200_AGP, 199 G200_SE_A, 200 G200_SE_B, 201 G200_WB, 202 G200_EV, 203 G200_EH, 204 G200_EH3, 205 G200_EH5, 206 G200_ER, 207 G200_EW3, 208 }; 209 210 struct mgag200_device_info { 211 u16 max_hdisplay; 212 u16 max_vdisplay; 213 214 /* 215 * Maximum memory bandwidth (MiB/sec). Setting this to zero disables 216 * the rsp test during mode validation. 217 */ 218 unsigned long max_mem_bandwidth; 219 220 /* Synchronize scanout with BMC */ 221 bool sync_bmc:1; 222 223 struct { 224 unsigned data_bit:3; 225 unsigned clock_bit:3; 226 } i2c; 227 228 /* 229 * HW does not handle 'startadd' register correctly. Always set 230 * it's value to 0. 231 */ 232 bool bug_no_startadd:1; 233 }; 234 235 #define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \ 236 _sync_bmc, _i2c_data_bit, _i2c_clock_bit, \ 237 _bug_no_startadd) \ 238 { \ 239 .max_hdisplay = (_max_hdisplay), \ 240 .max_vdisplay = (_max_vdisplay), \ 241 .max_mem_bandwidth = (_max_mem_bandwidth), \ 242 .sync_bmc = (_sync_bmc), \ 243 .i2c = { \ 244 .data_bit = (_i2c_data_bit), \ 245 .clock_bit = (_i2c_clock_bit), \ 246 }, \ 247 .bug_no_startadd = (_bug_no_startadd), \ 248 } 249 250 struct mgag200_device_funcs { 251 /* 252 * Validate that the given state can be programmed into PIXPLLC. On 253 * success, the calculated parameters should be stored in the CRTC's 254 * state in struct @mgag200_crtc_state.pixpllc. 255 */ 256 int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state); 257 258 /* 259 * Program PIXPLLC from the CRTC state. The parameters should have been 260 * stored in struct @mgag200_crtc_state.pixpllc by the corresponding 261 * implementation of @pixpllc_atomic_check. 262 */ 263 void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 264 }; 265 266 struct mga_device { 267 struct drm_device base; 268 269 const struct mgag200_device_info *info; 270 const struct mgag200_device_funcs *funcs; 271 272 struct resource *rmmio_res; 273 void __iomem *rmmio; 274 struct mutex rmmio_lock; /* Protects access to rmmio */ 275 276 struct resource *vram_res; 277 void __iomem *vram; 278 resource_size_t vram_available; 279 280 struct drm_plane primary_plane; 281 struct drm_crtc crtc; 282 struct { 283 struct { 284 struct drm_encoder encoder; 285 struct drm_connector connector; 286 } vga; 287 } output; 288 }; 289 290 static inline struct mga_device *to_mga_device(struct drm_device *dev) 291 { 292 return container_of(dev, struct mga_device, base); 293 } 294 295 struct mgag200_g200_device { 296 struct mga_device base; 297 298 /* PLL constants */ 299 long ref_clk; 300 long pclk_min; 301 long pclk_max; 302 }; 303 304 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev) 305 { 306 return container_of(to_mga_device(dev), struct mgag200_g200_device, base); 307 } 308 309 struct mgag200_g200se_device { 310 struct mga_device base; 311 312 /* SE model number stored in reg 0x1e24 */ 313 u32 unique_rev_id; 314 }; 315 316 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev) 317 { 318 return container_of(to_mga_device(dev), struct mgag200_g200se_device, base); 319 } 320 321 /* mgag200_drv.c */ 322 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2); 323 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size); 324 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); 325 int mgag200_device_preinit(struct mga_device *mdev); 326 int mgag200_device_init(struct mga_device *mdev, 327 const struct mgag200_device_info *info, 328 const struct mgag200_device_funcs *funcs); 329 330 /* mgag200_<device type>.c */ 331 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 332 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 333 enum mga_type type); 334 void mgag200_g200wb_init_registers(struct mga_device *mdev); 335 void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 336 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 337 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv); 338 void mgag200_g200eh_init_registers(struct mga_device *mdev); 339 void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 340 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, 341 const struct drm_driver *drv); 342 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, 343 const struct drm_driver *drv); 344 struct mga_device *mgag200_g200eh5_device_create(struct pci_dev *pdev, 345 const struct drm_driver *drv); 346 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, 347 const struct drm_driver *drv); 348 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, 349 const struct drm_driver *drv); 350 351 /* 352 * mgag200_mode.c 353 */ 354 355 struct drm_crtc; 356 struct drm_crtc_state; 357 struct drm_display_mode; 358 struct drm_plane; 359 struct drm_atomic_state; 360 struct drm_scanout_buffer; 361 362 extern const uint32_t mgag200_primary_plane_formats[]; 363 extern const size_t mgag200_primary_plane_formats_size; 364 extern const uint64_t mgag200_primary_plane_fmtmods[]; 365 366 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 367 struct drm_atomic_state *new_state); 368 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 369 struct drm_atomic_state *old_state); 370 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, 371 struct drm_atomic_state *state); 372 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 373 struct drm_atomic_state *old_state); 374 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 375 struct drm_scanout_buffer *sb); 376 377 #define MGAG200_PRIMARY_PLANE_HELPER_FUNCS \ 378 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \ 379 .atomic_check = mgag200_primary_plane_helper_atomic_check, \ 380 .atomic_update = mgag200_primary_plane_helper_atomic_update, \ 381 .atomic_enable = mgag200_primary_plane_helper_atomic_enable, \ 382 .atomic_disable = mgag200_primary_plane_helper_atomic_disable, \ 383 .get_scanout_buffer = mgag200_primary_plane_helper_get_scanout_buffer 384 385 #define MGAG200_PRIMARY_PLANE_FUNCS \ 386 .update_plane = drm_atomic_helper_update_plane, \ 387 .disable_plane = drm_atomic_helper_disable_plane, \ 388 .destroy = drm_plane_cleanup, \ 389 DRM_GEM_SHADOW_PLANE_FUNCS 390 391 void mgag200_crtc_fill_gamma(struct mga_device *mdev, const struct drm_format_info *format); 392 void mgag200_crtc_load_gamma(struct mga_device *mdev, 393 const struct drm_format_info *format, 394 struct drm_color_lut *lut); 395 396 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 397 const struct drm_display_mode *mode); 398 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state); 399 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 400 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 401 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state); 402 403 #define MGAG200_CRTC_HELPER_FUNCS \ 404 .mode_valid = mgag200_crtc_helper_mode_valid, \ 405 .atomic_check = mgag200_crtc_helper_atomic_check, \ 406 .atomic_flush = mgag200_crtc_helper_atomic_flush, \ 407 .atomic_enable = mgag200_crtc_helper_atomic_enable, \ 408 .atomic_disable = mgag200_crtc_helper_atomic_disable 409 410 void mgag200_crtc_reset(struct drm_crtc *crtc); 411 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc); 412 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); 413 414 #define MGAG200_CRTC_FUNCS \ 415 .reset = mgag200_crtc_reset, \ 416 .destroy = drm_crtc_cleanup, \ 417 .set_config = drm_atomic_helper_set_config, \ 418 .page_flip = drm_atomic_helper_page_flip, \ 419 .atomic_duplicate_state = mgag200_crtc_atomic_duplicate_state, \ 420 .atomic_destroy_state = mgag200_crtc_atomic_destroy_state 421 422 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode, 423 bool set_vidrst); 424 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format); 425 void mgag200_enable_display(struct mga_device *mdev); 426 void mgag200_init_registers(struct mga_device *mdev); 427 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available); 428 429 /* mgag200_vga_bmc.c */ 430 int mgag200_vga_bmc_output_init(struct mga_device *mdev); 431 432 /* mgag200_vga.c */ 433 int mgag200_vga_output_init(struct mga_device *mdev); 434 435 /* mgag200_bmc.c */ 436 void mgag200_bmc_stop_scanout(struct mga_device *mdev); 437 void mgag200_bmc_start_scanout(struct mga_device *mdev); 438 439 #endif /* __MGAG200_DRV_H__ */ 440