1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 #ifndef __MGAG200_DRV_H__ 11 #define __MGAG200_DRV_H__ 12 13 #include <linux/i2c-algo-bit.h> 14 #include <linux/i2c.h> 15 16 #include <video/vga.h> 17 18 #include <drm/drm_encoder.h> 19 #include <drm/drm_fb_helper.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_shmem_helper.h> 22 #include <drm/drm_simple_kms_helper.h> 23 24 #include "mgag200_reg.h" 25 26 #define DRIVER_AUTHOR "Matthew Garrett" 27 28 #define DRIVER_NAME "mgag200" 29 #define DRIVER_DESC "MGA G200 SE" 30 #define DRIVER_DATE "20110418" 31 32 #define DRIVER_MAJOR 1 33 #define DRIVER_MINOR 0 34 #define DRIVER_PATCHLEVEL 0 35 36 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) 37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) 38 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) 39 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) 40 41 #define MGA_BIOS_OFFSET 0x7ffc 42 43 #define ATTR_INDEX 0x1fc0 44 #define ATTR_DATA 0x1fc1 45 46 #define WREG_MISC(v) \ 47 WREG8(MGA_MISC_OUT, v) 48 49 #define RREG_MISC(v) \ 50 ((v) = RREG8(MGA_MISC_IN)) 51 52 #define WREG_MISC_MASKED(v, mask) \ 53 do { \ 54 u8 misc_; \ 55 u8 mask_ = (mask); \ 56 RREG_MISC(misc_); \ 57 misc_ &= ~mask_; \ 58 misc_ |= ((v) & mask_); \ 59 WREG_MISC(misc_); \ 60 } while (0) 61 62 #define WREG_ATTR(reg, v) \ 63 do { \ 64 RREG8(0x1fda); \ 65 WREG8(ATTR_INDEX, reg); \ 66 WREG8(ATTR_DATA, v); \ 67 } while (0) \ 68 69 #define RREG_SEQ(reg, v) \ 70 do { \ 71 WREG8(MGAREG_SEQ_INDEX, reg); \ 72 v = RREG8(MGAREG_SEQ_DATA); \ 73 } while (0) \ 74 75 #define WREG_SEQ(reg, v) \ 76 do { \ 77 WREG8(MGAREG_SEQ_INDEX, reg); \ 78 WREG8(MGAREG_SEQ_DATA, v); \ 79 } while (0) \ 80 81 #define RREG_CRT(reg, v) \ 82 do { \ 83 WREG8(MGAREG_CRTC_INDEX, reg); \ 84 v = RREG8(MGAREG_CRTC_DATA); \ 85 } while (0) \ 86 87 #define WREG_CRT(reg, v) \ 88 do { \ 89 WREG8(MGAREG_CRTC_INDEX, reg); \ 90 WREG8(MGAREG_CRTC_DATA, v); \ 91 } while (0) \ 92 93 #define RREG_ECRT(reg, v) \ 94 do { \ 95 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 96 v = RREG8(MGAREG_CRTCEXT_DATA); \ 97 } while (0) \ 98 99 #define WREG_ECRT(reg, v) \ 100 do { \ 101 WREG8(MGAREG_CRTCEXT_INDEX, reg); \ 102 WREG8(MGAREG_CRTCEXT_DATA, v); \ 103 } while (0) \ 104 105 #define GFX_INDEX 0x1fce 106 #define GFX_DATA 0x1fcf 107 108 #define WREG_GFX(reg, v) \ 109 do { \ 110 WREG8(GFX_INDEX, reg); \ 111 WREG8(GFX_DATA, v); \ 112 } while (0) \ 113 114 #define DAC_INDEX 0x3c00 115 #define DAC_DATA 0x3c0a 116 117 #define WREG_DAC(reg, v) \ 118 do { \ 119 WREG8(DAC_INDEX, reg); \ 120 WREG8(DAC_DATA, v); \ 121 } while (0) \ 122 123 #define MGA_MISC_OUT 0x1fc2 124 #define MGA_MISC_IN 0x1fcc 125 126 #define MGAG200_MAX_FB_HEIGHT 4096 127 #define MGAG200_MAX_FB_WIDTH 4096 128 129 struct mga_device; 130 struct mgag200_pll; 131 132 /* 133 * Stores parameters for programming the PLLs 134 * 135 * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz) 136 * Fo: output frequency 137 * Fvco = Fref * (N / M) 138 * Fo = Fvco / P 139 * 140 * S = [0..3] 141 */ 142 struct mgag200_pll_values { 143 unsigned int m; 144 unsigned int n; 145 unsigned int p; 146 unsigned int s; 147 }; 148 149 struct mgag200_pll_funcs { 150 int (*compute)(struct mgag200_pll *pll, long clock, struct mgag200_pll_values *pllc); 151 void (*update)(struct mgag200_pll *pll, const struct mgag200_pll_values *pllc); 152 }; 153 154 struct mgag200_pll { 155 struct mga_device *mdev; 156 157 const struct mgag200_pll_funcs *funcs; 158 }; 159 160 struct mgag200_crtc_state { 161 struct drm_crtc_state base; 162 163 struct mgag200_pll_values pixpllc; 164 }; 165 166 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base) 167 { 168 return container_of(base, struct mgag200_crtc_state, base); 169 } 170 171 struct mga_i2c_chan { 172 struct i2c_adapter adapter; 173 struct drm_device *dev; 174 struct i2c_algo_bit_data bit; 175 int data, clock; 176 }; 177 178 enum mga_type { 179 G200_PCI, 180 G200_AGP, 181 G200_SE_A, 182 G200_SE_B, 183 G200_WB, 184 G200_EV, 185 G200_EH, 186 G200_EH3, 187 G200_ER, 188 G200_EW3, 189 }; 190 191 #define IS_G200_SE(mdev) (mdev->type == G200_SE_A || mdev->type == G200_SE_B) 192 193 struct mgag200_device_info { 194 u16 max_hdisplay; 195 u16 max_vdisplay; 196 197 /* 198 * Maximum memory bandwidth (MiB/sec). Setting this to zero disables 199 * the rsp test during mode validation. 200 */ 201 unsigned long max_mem_bandwidth; 202 203 /* HW has external source (e.g., BMC) to synchronize with */ 204 bool has_vidrst:1; 205 206 struct { 207 unsigned data_bit:3; 208 unsigned clock_bit:3; 209 } i2c; 210 211 /* 212 * HW does not handle 'startadd' register correctly. Always set 213 * it's value to 0. 214 */ 215 bool bug_no_startadd:1; 216 }; 217 218 #define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \ 219 _has_vidrst, _i2c_data_bit, _i2c_clock_bit, \ 220 _bug_no_startadd) \ 221 { \ 222 .max_hdisplay = (_max_hdisplay), \ 223 .max_vdisplay = (_max_vdisplay), \ 224 .max_mem_bandwidth = (_max_mem_bandwidth), \ 225 .has_vidrst = (_has_vidrst), \ 226 .i2c = { \ 227 .data_bit = (_i2c_data_bit), \ 228 .clock_bit = (_i2c_clock_bit), \ 229 }, \ 230 .bug_no_startadd = (_bug_no_startadd), \ 231 } 232 233 struct mga_device { 234 struct drm_device base; 235 236 const struct mgag200_device_info *info; 237 238 struct resource *rmmio_res; 239 void __iomem *rmmio; 240 struct mutex rmmio_lock; /* Protects access to rmmio */ 241 242 struct resource *vram_res; 243 void __iomem *vram; 244 resource_size_t vram_available; 245 246 enum mga_type type; 247 248 struct mgag200_pll pixpll; 249 struct mga_i2c_chan i2c; 250 struct drm_connector connector; 251 struct drm_simple_display_pipe display_pipe; 252 }; 253 254 static inline struct mga_device *to_mga_device(struct drm_device *dev) 255 { 256 return container_of(dev, struct mga_device, base); 257 } 258 259 struct mgag200_g200_device { 260 struct mga_device base; 261 262 /* PLL constants */ 263 long ref_clk; 264 long pclk_min; 265 long pclk_max; 266 }; 267 268 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev) 269 { 270 return container_of(to_mga_device(dev), struct mgag200_g200_device, base); 271 } 272 273 struct mgag200_g200se_device { 274 struct mga_device base; 275 276 /* SE model number stored in reg 0x1e24 */ 277 u32 unique_rev_id; 278 }; 279 280 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev) 281 { 282 return container_of(to_mga_device(dev), struct mgag200_g200se_device, base); 283 } 284 285 /* mgag200_drv.c */ 286 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2); 287 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size); 288 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); 289 int mgag200_device_preinit(struct mga_device *mdev); 290 int mgag200_device_init(struct mga_device *mdev, enum mga_type type, 291 const struct mgag200_device_info *info); 292 293 /* mgag200_<device type>.c */ 294 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 295 enum mga_type type); 296 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 297 enum mga_type type); 298 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 299 enum mga_type type); 300 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 301 enum mga_type type); 302 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 303 enum mga_type type); 304 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 305 enum mga_type type); 306 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 307 enum mga_type type); 308 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, const struct drm_driver *drv, 309 enum mga_type type); 310 311 /* mgag200_mode.c */ 312 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); 313 int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_fb_available); 314 315 /* mgag200_i2c.c */ 316 int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c); 317 318 /* mgag200_pll.c */ 319 int mgag200_pixpll_init(struct mgag200_pll *pixpll, struct mga_device *mdev); 320 321 #endif /* __MGAG200_DRV_H__ */ 322