1 /* 2 * Copyright (C) 2016 BayLibre, SAS 3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * Copyright (C) 2014 Endless Mobile 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Written by: 21 * Jasper St. Pierre <jstpierre@mecheye.net> 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/platform_device.h> 28 #include <drm/drmP.h> 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_plane_helper.h> 32 #include <drm/drm_gem_cma_helper.h> 33 #include <drm/drm_fb_cma_helper.h> 34 #include <drm/drm_rect.h> 35 36 #include "meson_plane.h" 37 #include "meson_vpp.h" 38 #include "meson_viu.h" 39 #include "meson_canvas.h" 40 #include "meson_registers.h" 41 42 struct meson_plane { 43 struct drm_plane base; 44 struct meson_drm *priv; 45 }; 46 #define to_meson_plane(x) container_of(x, struct meson_plane, base) 47 48 static int meson_plane_atomic_check(struct drm_plane *plane, 49 struct drm_plane_state *state) 50 { 51 struct drm_crtc_state *crtc_state; 52 struct drm_rect clip = { 0, }; 53 54 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 55 if (IS_ERR(crtc_state)) 56 return PTR_ERR(crtc_state); 57 58 clip.x2 = crtc_state->mode.hdisplay; 59 clip.y2 = crtc_state->mode.vdisplay; 60 61 return drm_plane_helper_check_state(state, &clip, 62 DRM_PLANE_HELPER_NO_SCALING, 63 DRM_PLANE_HELPER_NO_SCALING, 64 true, true); 65 } 66 67 /* Takes a fixed 16.16 number and converts it to integer. */ 68 static inline int64_t fixed16_to_int(int64_t value) 69 { 70 return value >> 16; 71 } 72 73 static void meson_plane_atomic_update(struct drm_plane *plane, 74 struct drm_plane_state *old_state) 75 { 76 struct meson_plane *meson_plane = to_meson_plane(plane); 77 struct drm_plane_state *state = plane->state; 78 struct drm_framebuffer *fb = state->fb; 79 struct meson_drm *priv = meson_plane->priv; 80 struct drm_gem_cma_object *gem; 81 struct drm_rect src = { 82 .x1 = (state->src_x), 83 .y1 = (state->src_y), 84 .x2 = (state->src_x + state->src_w), 85 .y2 = (state->src_y + state->src_h), 86 }; 87 struct drm_rect dest = { 88 .x1 = state->crtc_x, 89 .y1 = state->crtc_y, 90 .x2 = state->crtc_x + state->crtc_w, 91 .y2 = state->crtc_y + state->crtc_h, 92 }; 93 unsigned long flags; 94 95 /* 96 * Update Coordinates 97 * Update Formats 98 * Update Buffer 99 * Enable Plane 100 */ 101 spin_lock_irqsave(&priv->drm->event_lock, flags); 102 103 /* Enable OSD and BLK0, set max global alpha */ 104 priv->viu.osd1_ctrl_stat = OSD_ENABLE | 105 (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | 106 OSD_BLK0_ENABLE; 107 108 /* Set up BLK0 to point to the right canvas */ 109 priv->viu.osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) | 110 OSD_ENDIANNESS_LE); 111 112 /* On GXBB, Use the old non-HDR RGB2YUV converter */ 113 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 114 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; 115 116 switch (fb->pixel_format) { 117 case DRM_FORMAT_XRGB8888: 118 /* For XRGB, replace the pixel's alpha by 0xFF */ 119 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, 120 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 121 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 122 OSD_COLOR_MATRIX_32_ARGB; 123 break; 124 case DRM_FORMAT_ARGB8888: 125 /* For ARGB, use the pixel's alpha */ 126 writel_bits_relaxed(OSD_REPLACE_EN, 0, 127 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 128 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 129 OSD_COLOR_MATRIX_32_ARGB; 130 break; 131 case DRM_FORMAT_RGB888: 132 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | 133 OSD_COLOR_MATRIX_24_RGB; 134 break; 135 case DRM_FORMAT_RGB565: 136 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | 137 OSD_COLOR_MATRIX_16_RGB565; 138 break; 139 }; 140 141 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { 142 priv->viu.osd1_interlace = true; 143 144 dest.y1 /= 2; 145 dest.y2 /= 2; 146 } else 147 priv->viu.osd1_interlace = false; 148 149 /* 150 * The format of these registers is (x2 << 16 | x1), 151 * where x2 is exclusive. 152 * e.g. +30x1920 would be (1919 << 16) | 30 153 */ 154 priv->viu.osd1_blk0_cfg[1] = ((fixed16_to_int(src.x2) - 1) << 16) | 155 fixed16_to_int(src.x1); 156 priv->viu.osd1_blk0_cfg[2] = ((fixed16_to_int(src.y2) - 1) << 16) | 157 fixed16_to_int(src.y1); 158 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; 159 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; 160 161 /* Update Canvas with buffer address */ 162 gem = drm_fb_cma_get_gem_obj(fb, 0); 163 164 meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1, 165 gem->paddr, fb->pitches[0], 166 fb->height, MESON_CANVAS_WRAP_NONE, 167 MESON_CANVAS_BLKMODE_LINEAR); 168 169 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 170 } 171 172 static void meson_plane_atomic_disable(struct drm_plane *plane, 173 struct drm_plane_state *old_state) 174 { 175 struct meson_plane *meson_plane = to_meson_plane(plane); 176 struct meson_drm *priv = meson_plane->priv; 177 178 /* Disable OSD1 */ 179 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, 180 priv->io_base + _REG(VPP_MISC)); 181 182 } 183 184 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { 185 .atomic_check = meson_plane_atomic_check, 186 .atomic_disable = meson_plane_atomic_disable, 187 .atomic_update = meson_plane_atomic_update, 188 }; 189 190 static const struct drm_plane_funcs meson_plane_funcs = { 191 .update_plane = drm_atomic_helper_update_plane, 192 .disable_plane = drm_atomic_helper_disable_plane, 193 .destroy = drm_plane_cleanup, 194 .reset = drm_atomic_helper_plane_reset, 195 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 196 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 197 }; 198 199 static const uint32_t supported_drm_formats[] = { 200 DRM_FORMAT_ARGB8888, 201 DRM_FORMAT_XRGB8888, 202 DRM_FORMAT_RGB888, 203 DRM_FORMAT_RGB565, 204 }; 205 206 int meson_plane_create(struct meson_drm *priv) 207 { 208 struct meson_plane *meson_plane; 209 struct drm_plane *plane; 210 211 meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), 212 GFP_KERNEL); 213 if (!meson_plane) 214 return -ENOMEM; 215 216 meson_plane->priv = priv; 217 plane = &meson_plane->base; 218 219 drm_universal_plane_init(priv->drm, plane, 0xFF, 220 &meson_plane_funcs, 221 supported_drm_formats, 222 ARRAY_SIZE(supported_drm_formats), 223 DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); 224 225 drm_plane_helper_add(plane, &meson_plane_helper_funcs); 226 227 priv->primary_plane = plane; 228 229 return 0; 230 } 231