1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2021 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/of_graph.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 #include <linux/phy/phy.h> 16 #include <linux/bitfield.h> 17 18 #include <video/mipi_display.h> 19 20 #include <drm/bridge/dw_mipi_dsi.h> 21 #include <drm/drm_mipi_dsi.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_device.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_print.h> 27 28 #include "meson_drv.h" 29 #include "meson_dw_mipi_dsi.h" 30 #include "meson_registers.h" 31 #include "meson_venc.h" 32 33 #define DRIVER_NAME "meson-dw-mipi-dsi" 34 #define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver" 35 36 struct meson_dw_mipi_dsi { 37 struct meson_drm *priv; 38 struct device *dev; 39 void __iomem *base; 40 struct phy *phy; 41 union phy_configure_opts phy_opts; 42 struct dw_mipi_dsi *dmd; 43 struct dw_mipi_dsi_plat_data pdata; 44 struct mipi_dsi_device *dsi_device; 45 const struct drm_display_mode *mode; 46 struct clk *bit_clk; 47 struct clk *px_clk; 48 struct reset_control *top_rst; 49 }; 50 51 #define encoder_to_meson_dw_mipi_dsi(x) \ 52 container_of(x, struct meson_dw_mipi_dsi, encoder) 53 54 static void meson_dw_mipi_dsi_hw_init(struct meson_dw_mipi_dsi *mipi_dsi) 55 { 56 /* Software reset */ 57 writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR | 58 MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING, 59 MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR | 60 MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING, 61 mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); 62 writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR | 63 MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING, 64 0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); 65 66 /* Enable clocks */ 67 writel_bits_relaxed(MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN, 68 MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN, 69 mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL); 70 71 /* Take memory out of power down */ 72 writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD); 73 } 74 75 static int dw_mipi_dsi_phy_init(void *priv_data) 76 { 77 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 78 unsigned int dpi_data_format, venc_data_width; 79 int ret; 80 81 /* Set the bit clock rate to hs_clk_rate */ 82 ret = clk_set_rate(mipi_dsi->bit_clk, 83 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate); 84 if (ret) { 85 dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n", 86 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, ret); 87 return ret; 88 } 89 90 /* Make sure the rate of the bit clock is not modified by someone else */ 91 ret = clk_rate_exclusive_get(mipi_dsi->bit_clk); 92 if (ret) { 93 dev_err(mipi_dsi->dev, 94 "Failed to set the exclusivity on the bit clock rate (ret %d)\n", ret); 95 return ret; 96 } 97 98 clk_disable_unprepare(mipi_dsi->px_clk); 99 ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000); 100 101 if (ret) { 102 dev_err(mipi_dsi->dev, "Failed to set DSI Pixel clock rate %u (%d)\n", 103 mipi_dsi->mode->clock * 1000, ret); 104 return ret; 105 } 106 107 ret = clk_prepare_enable(mipi_dsi->px_clk); 108 if (ret) { 109 dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret); 110 return ret; 111 } 112 113 switch (mipi_dsi->dsi_device->format) { 114 case MIPI_DSI_FMT_RGB888: 115 dpi_data_format = DPI_COLOR_24BIT; 116 venc_data_width = VENC_IN_COLOR_24B; 117 break; 118 case MIPI_DSI_FMT_RGB666: 119 dpi_data_format = DPI_COLOR_18BIT_CFG_2; 120 venc_data_width = VENC_IN_COLOR_18B; 121 break; 122 case MIPI_DSI_FMT_RGB666_PACKED: 123 case MIPI_DSI_FMT_RGB565: 124 return -EINVAL; 125 } 126 127 /* Configure color format for DPI register */ 128 writel_relaxed(FIELD_PREP(MIPI_DSI_TOP_DPI_COLOR_MODE, dpi_data_format) | 129 FIELD_PREP(MIPI_DSI_TOP_IN_COLOR_MODE, venc_data_width) | 130 FIELD_PREP(MIPI_DSI_TOP_COMP2_SEL, 2) | 131 FIELD_PREP(MIPI_DSI_TOP_COMP1_SEL, 1) | 132 FIELD_PREP(MIPI_DSI_TOP_COMP0_SEL, 0), 133 mipi_dsi->base + MIPI_DSI_TOP_CNTL); 134 135 return phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts); 136 } 137 138 static void dw_mipi_dsi_phy_power_on(void *priv_data) 139 { 140 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 141 142 if (phy_power_on(mipi_dsi->phy)) 143 dev_warn(mipi_dsi->dev, "Failed to power on PHY\n"); 144 } 145 146 static void dw_mipi_dsi_phy_power_off(void *priv_data) 147 { 148 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 149 150 if (phy_power_off(mipi_dsi->phy)) 151 dev_warn(mipi_dsi->dev, "Failed to power off PHY\n"); 152 153 /* Remove the exclusivity on the bit clock rate */ 154 clk_rate_exclusive_put(mipi_dsi->bit_clk); 155 } 156 157 static int 158 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 159 unsigned long mode_flags, u32 lanes, u32 format, 160 unsigned int *lane_mbps) 161 { 162 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 163 int bpp; 164 165 mipi_dsi->mode = mode; 166 167 bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format); 168 169 phy_mipi_dphy_get_default_config(mode->clock * 1000, 170 bpp, mipi_dsi->dsi_device->lanes, 171 &mipi_dsi->phy_opts.mipi_dphy); 172 173 *lane_mbps = DIV_ROUND_UP(mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, USEC_PER_SEC); 174 175 return 0; 176 } 177 178 static int 179 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 180 struct dw_mipi_dsi_dphy_timing *timing) 181 { 182 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 183 184 switch (mipi_dsi->mode->hdisplay) { 185 case 240: 186 case 768: 187 case 1920: 188 case 2560: 189 timing->clk_lp2hs = 23; 190 timing->clk_hs2lp = 38; 191 timing->data_lp2hs = 15; 192 timing->data_hs2lp = 9; 193 break; 194 195 default: 196 timing->clk_lp2hs = 37; 197 timing->clk_hs2lp = 135; 198 timing->data_lp2hs = 50; 199 timing->data_hs2lp = 3; 200 } 201 202 return 0; 203 } 204 205 static int 206 dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate) 207 { 208 *esc_clk_rate = 4; /* Mhz */ 209 210 return 0; 211 } 212 213 static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = { 214 .init = dw_mipi_dsi_phy_init, 215 .power_on = dw_mipi_dsi_phy_power_on, 216 .power_off = dw_mipi_dsi_phy_power_off, 217 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 218 .get_timing = dw_mipi_dsi_phy_get_timing, 219 .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate, 220 }; 221 222 static int meson_dw_mipi_dsi_host_attach(void *priv_data, 223 struct mipi_dsi_device *device) 224 { 225 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 226 int ret; 227 228 mipi_dsi->dsi_device = device; 229 230 switch (device->format) { 231 case MIPI_DSI_FMT_RGB888: 232 break; 233 case MIPI_DSI_FMT_RGB666: 234 break; 235 case MIPI_DSI_FMT_RGB666_PACKED: 236 case MIPI_DSI_FMT_RGB565: 237 dev_err(mipi_dsi->dev, "invalid pixel format %d\n", device->format); 238 return -EINVAL; 239 } 240 241 ret = phy_init(mipi_dsi->phy); 242 if (ret) 243 return ret; 244 245 meson_dw_mipi_dsi_hw_init(mipi_dsi); 246 247 return 0; 248 } 249 250 static int meson_dw_mipi_dsi_host_detach(void *priv_data, 251 struct mipi_dsi_device *device) 252 { 253 struct meson_dw_mipi_dsi *mipi_dsi = priv_data; 254 255 if (device == mipi_dsi->dsi_device) 256 mipi_dsi->dsi_device = NULL; 257 else 258 return -EINVAL; 259 260 return phy_exit(mipi_dsi->phy); 261 } 262 263 static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = { 264 .attach = meson_dw_mipi_dsi_host_attach, 265 .detach = meson_dw_mipi_dsi_host_detach, 266 }; 267 268 static int meson_dw_mipi_dsi_probe(struct platform_device *pdev) 269 { 270 struct meson_dw_mipi_dsi *mipi_dsi; 271 struct device *dev = &pdev->dev; 272 273 mipi_dsi = devm_kzalloc(dev, sizeof(*mipi_dsi), GFP_KERNEL); 274 if (!mipi_dsi) 275 return -ENOMEM; 276 277 mipi_dsi->base = devm_platform_ioremap_resource(pdev, 0); 278 if (IS_ERR(mipi_dsi->base)) 279 return PTR_ERR(mipi_dsi->base); 280 281 mipi_dsi->phy = devm_phy_get(dev, "dphy"); 282 if (IS_ERR(mipi_dsi->phy)) 283 return dev_err_probe(dev, PTR_ERR(mipi_dsi->phy), 284 "failed to get mipi dphy\n"); 285 286 mipi_dsi->bit_clk = devm_clk_get_enabled(dev, "bit"); 287 if (IS_ERR(mipi_dsi->bit_clk)) { 288 int ret = PTR_ERR(mipi_dsi->bit_clk); 289 290 /* TOFIX GP0 on some platforms fails to lock in early boot, defer probe */ 291 if (ret == -EIO) 292 ret = -EPROBE_DEFER; 293 294 return dev_err_probe(dev, ret, "Unable to get enabled bit_clk\n"); 295 } 296 297 mipi_dsi->px_clk = devm_clk_get_enabled(dev, "px"); 298 if (IS_ERR(mipi_dsi->px_clk)) 299 return dev_err_probe(dev, PTR_ERR(mipi_dsi->px_clk), 300 "Unable to get enabled px_clk\n"); 301 302 /* 303 * We use a TOP reset signal because the APB reset signal 304 * is handled by the TOP control registers. 305 */ 306 mipi_dsi->top_rst = devm_reset_control_get_exclusive(dev, "top"); 307 if (IS_ERR(mipi_dsi->top_rst)) 308 return dev_err_probe(dev, PTR_ERR(mipi_dsi->top_rst), 309 "Unable to get reset control\n"); 310 311 reset_control_assert(mipi_dsi->top_rst); 312 usleep_range(10, 20); 313 reset_control_deassert(mipi_dsi->top_rst); 314 315 /* MIPI DSI Controller */ 316 317 mipi_dsi->dev = dev; 318 mipi_dsi->pdata.base = mipi_dsi->base; 319 mipi_dsi->pdata.max_data_lanes = 4; 320 mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops; 321 mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops; 322 mipi_dsi->pdata.priv_data = mipi_dsi; 323 platform_set_drvdata(pdev, mipi_dsi); 324 325 mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata); 326 if (IS_ERR(mipi_dsi->dmd)) 327 return dev_err_probe(dev, PTR_ERR(mipi_dsi->dmd), 328 "Failed to probe dw_mipi_dsi\n"); 329 330 return 0; 331 } 332 333 static void meson_dw_mipi_dsi_remove(struct platform_device *pdev) 334 { 335 struct meson_dw_mipi_dsi *mipi_dsi = platform_get_drvdata(pdev); 336 337 dw_mipi_dsi_remove(mipi_dsi->dmd); 338 } 339 340 static const struct of_device_id meson_dw_mipi_dsi_of_table[] = { 341 { .compatible = "amlogic,meson-g12a-dw-mipi-dsi", }, 342 { } 343 }; 344 MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table); 345 346 static struct platform_driver meson_dw_mipi_dsi_platform_driver = { 347 .probe = meson_dw_mipi_dsi_probe, 348 .remove_new = meson_dw_mipi_dsi_remove, 349 .driver = { 350 .name = DRIVER_NAME, 351 .of_match_table = meson_dw_mipi_dsi_of_table, 352 }, 353 }; 354 module_platform_driver(meson_dw_mipi_dsi_platform_driver); 355 356 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 357 MODULE_DESCRIPTION(DRIVER_DESC); 358 MODULE_LICENSE("GPL"); 359