11ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2bbbe775eSNeil Armstrong /* 3bbbe775eSNeil Armstrong * Copyright (C) 2016 BayLibre, SAS 4bbbe775eSNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 5bbbe775eSNeil Armstrong */ 6bbbe775eSNeil Armstrong 7bbbe775eSNeil Armstrong #ifndef __MESON_DRV_H 8bbbe775eSNeil Armstrong #define __MESON_DRV_H 9bbbe775eSNeil Armstrong 1066620f48SSam Ravnborg #include <linux/device.h> 11bbbe775eSNeil Armstrong #include <linux/of.h> 12528a25d0SJulien Masson #include <linux/of_device.h> 1366620f48SSam Ravnborg #include <linux/regmap.h> 1466620f48SSam Ravnborg 1566620f48SSam Ravnborg struct drm_crtc; 1666620f48SSam Ravnborg struct drm_device; 1766620f48SSam Ravnborg struct drm_plane; 1866620f48SSam Ravnborg struct meson_drm; 19*d1b5e41eSNeil Armstrong struct meson_afbcd_ops; 20bbbe775eSNeil Armstrong 21528a25d0SJulien Masson enum vpu_compatible { 22528a25d0SJulien Masson VPU_COMPATIBLE_GXBB = 0, 23528a25d0SJulien Masson VPU_COMPATIBLE_GXL = 1, 24528a25d0SJulien Masson VPU_COMPATIBLE_GXM = 2, 25528a25d0SJulien Masson VPU_COMPATIBLE_G12A = 3, 26528a25d0SJulien Masson }; 27528a25d0SJulien Masson 28*d1b5e41eSNeil Armstrong struct meson_drm_match_data { 29*d1b5e41eSNeil Armstrong enum vpu_compatible compat; 30*d1b5e41eSNeil Armstrong struct meson_afbcd_ops *afbcd_ops; 31*d1b5e41eSNeil Armstrong }; 32*d1b5e41eSNeil Armstrong 33bbbe775eSNeil Armstrong struct meson_drm { 34bbbe775eSNeil Armstrong struct device *dev; 35528a25d0SJulien Masson enum vpu_compatible compat; 36bbbe775eSNeil Armstrong void __iomem *io_base; 37bbbe775eSNeil Armstrong struct regmap *hhi; 38bbbe775eSNeil Armstrong int vsync_irq; 39bbbe775eSNeil Armstrong 4066cae477SMaxime Jourdan struct meson_canvas *canvas; 4166cae477SMaxime Jourdan u8 canvas_id_osd1; 42f9a23481SNeil Armstrong u8 canvas_id_vd1_0; 43f9a23481SNeil Armstrong u8 canvas_id_vd1_1; 44f9a23481SNeil Armstrong u8 canvas_id_vd1_2; 4566cae477SMaxime Jourdan 46bbbe775eSNeil Armstrong struct drm_device *drm; 47bbbe775eSNeil Armstrong struct drm_crtc *crtc; 48bbbe775eSNeil Armstrong struct drm_plane *primary_plane; 49f9a23481SNeil Armstrong struct drm_plane *overlay_plane; 50bbbe775eSNeil Armstrong 51bbbe775eSNeil Armstrong /* Components Data */ 52bbbe775eSNeil Armstrong struct { 53bbbe775eSNeil Armstrong bool osd1_enabled; 54bbbe775eSNeil Armstrong bool osd1_interlace; 55bbbe775eSNeil Armstrong bool osd1_commit; 56bbbe775eSNeil Armstrong uint32_t osd1_ctrl_stat; 57bbbe775eSNeil Armstrong uint32_t osd1_blk0_cfg[5]; 58e88230a3SNeil Armstrong uint32_t osd1_addr; 59e88230a3SNeil Armstrong uint32_t osd1_stride; 60e88230a3SNeil Armstrong uint32_t osd1_height; 61ce7cb472SNeil Armstrong uint32_t osd1_width; 6220d7fe03SNeil Armstrong uint32_t osd_sc_ctrl0; 6320d7fe03SNeil Armstrong uint32_t osd_sc_i_wh_m1; 6420d7fe03SNeil Armstrong uint32_t osd_sc_o_h_start_end; 6520d7fe03SNeil Armstrong uint32_t osd_sc_o_v_start_end; 6620d7fe03SNeil Armstrong uint32_t osd_sc_v_ini_phase; 6720d7fe03SNeil Armstrong uint32_t osd_sc_v_phase_step; 6820d7fe03SNeil Armstrong uint32_t osd_sc_h_ini_phase; 6920d7fe03SNeil Armstrong uint32_t osd_sc_h_phase_step; 7020d7fe03SNeil Armstrong uint32_t osd_sc_h_ctrl0; 7120d7fe03SNeil Armstrong uint32_t osd_sc_v_ctrl0; 7268679d41SNeil Armstrong uint32_t osd_blend_din0_scope_h; 7368679d41SNeil Armstrong uint32_t osd_blend_din0_scope_v; 7468679d41SNeil Armstrong uint32_t osb_blend0_size; 7568679d41SNeil Armstrong uint32_t osb_blend1_size; 76f9a23481SNeil Armstrong 77f9a23481SNeil Armstrong bool vd1_enabled; 78f9a23481SNeil Armstrong bool vd1_commit; 79f9a23481SNeil Armstrong unsigned int vd1_planes; 80f9a23481SNeil Armstrong uint32_t vd1_if0_gen_reg; 81f9a23481SNeil Armstrong uint32_t vd1_if0_luma_x0; 82f9a23481SNeil Armstrong uint32_t vd1_if0_luma_y0; 83f9a23481SNeil Armstrong uint32_t vd1_if0_chroma_x0; 84f9a23481SNeil Armstrong uint32_t vd1_if0_chroma_y0; 85f9a23481SNeil Armstrong uint32_t vd1_if0_repeat_loop; 86f9a23481SNeil Armstrong uint32_t vd1_if0_luma0_rpt_pat; 87f9a23481SNeil Armstrong uint32_t vd1_if0_chroma0_rpt_pat; 88f9a23481SNeil Armstrong uint32_t vd1_range_map_y; 89f9a23481SNeil Armstrong uint32_t vd1_range_map_cb; 90f9a23481SNeil Armstrong uint32_t vd1_range_map_cr; 91f9a23481SNeil Armstrong uint32_t viu_vd1_fmt_w; 92f9a23481SNeil Armstrong uint32_t vd1_if0_canvas0; 93f9a23481SNeil Armstrong uint32_t vd1_if0_gen_reg2; 94f9a23481SNeil Armstrong uint32_t viu_vd1_fmt_ctrl; 95f9a23481SNeil Armstrong uint32_t vd1_addr0; 96f9a23481SNeil Armstrong uint32_t vd1_addr1; 97f9a23481SNeil Armstrong uint32_t vd1_addr2; 98f9a23481SNeil Armstrong uint32_t vd1_stride0; 99f9a23481SNeil Armstrong uint32_t vd1_stride1; 100f9a23481SNeil Armstrong uint32_t vd1_stride2; 101f9a23481SNeil Armstrong uint32_t vd1_height0; 102f9a23481SNeil Armstrong uint32_t vd1_height1; 103f9a23481SNeil Armstrong uint32_t vd1_height2; 104f9a23481SNeil Armstrong uint32_t vpp_pic_in_height; 105f9a23481SNeil Armstrong uint32_t vpp_postblend_vd1_h_start_end; 106f9a23481SNeil Armstrong uint32_t vpp_postblend_vd1_v_start_end; 107f9a23481SNeil Armstrong uint32_t vpp_hsc_region12_startp; 108f9a23481SNeil Armstrong uint32_t vpp_hsc_region34_startp; 109f9a23481SNeil Armstrong uint32_t vpp_hsc_region4_endp; 110f9a23481SNeil Armstrong uint32_t vpp_hsc_start_phase_step; 111f9a23481SNeil Armstrong uint32_t vpp_hsc_region1_phase_slope; 112f9a23481SNeil Armstrong uint32_t vpp_hsc_region3_phase_slope; 113f9a23481SNeil Armstrong uint32_t vpp_line_in_length; 114f9a23481SNeil Armstrong uint32_t vpp_preblend_h_size; 115f9a23481SNeil Armstrong uint32_t vpp_vsc_region12_startp; 116f9a23481SNeil Armstrong uint32_t vpp_vsc_region34_startp; 117f9a23481SNeil Armstrong uint32_t vpp_vsc_region4_endp; 118f9a23481SNeil Armstrong uint32_t vpp_vsc_start_phase_step; 119f9a23481SNeil Armstrong uint32_t vpp_vsc_ini_phase; 120f9a23481SNeil Armstrong uint32_t vpp_vsc_phase_ctrl; 121f9a23481SNeil Armstrong uint32_t vpp_hsc_phase_ctrl; 122f9a23481SNeil Armstrong uint32_t vpp_blend_vd2_h_start_end; 123f9a23481SNeil Armstrong uint32_t vpp_blend_vd2_v_start_end; 124bbbe775eSNeil Armstrong } viu; 125bbbe775eSNeil Armstrong 126bbbe775eSNeil Armstrong struct { 127bbbe775eSNeil Armstrong unsigned int current_mode; 1283f68be7dSNeil Armstrong bool hdmi_repeat; 1293f68be7dSNeil Armstrong bool venc_repeat; 1303f68be7dSNeil Armstrong bool hdmi_use_enci; 131bbbe775eSNeil Armstrong } venc; 13263fba242SNeil Armstrong 13363fba242SNeil Armstrong struct { 13463fba242SNeil Armstrong dma_addr_t addr_phys; 13563fba242SNeil Armstrong uint32_t *addr; 13663fba242SNeil Armstrong unsigned int offset; 13763fba242SNeil Armstrong } rdma; 138*d1b5e41eSNeil Armstrong 139*d1b5e41eSNeil Armstrong struct { 140*d1b5e41eSNeil Armstrong struct meson_afbcd_ops *ops; 141*d1b5e41eSNeil Armstrong u64 modifier; 142*d1b5e41eSNeil Armstrong u32 format; 143*d1b5e41eSNeil Armstrong } afbcd; 144bbbe775eSNeil Armstrong }; 145bbbe775eSNeil Armstrong 146bbbe775eSNeil Armstrong static inline int meson_vpu_is_compatible(struct meson_drm *priv, 147528a25d0SJulien Masson enum vpu_compatible family) 148bbbe775eSNeil Armstrong { 149528a25d0SJulien Masson return priv->compat == family; 150bbbe775eSNeil Armstrong } 151bbbe775eSNeil Armstrong 152bbbe775eSNeil Armstrong #endif /* __MESON_DRV_H */ 153