1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek HDMI v2 IP driver 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Copyright (c) 2022 BayLibre, SAS 7 * Copyright (c) 2024 Collabora Ltd. 8 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/kernel.h> 20 #include <linux/mutex.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/suspend.h> 26 #include <linux/units.h> 27 #include <linux/phy/phy.h> 28 29 #include <drm/display/drm_hdmi_helper.h> 30 #include <drm/display/drm_hdmi_state_helper.h> 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_drv.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "mtk_hdmi_common.h" 38 #include "mtk_hdmi_regs_v2.h" 39 40 #define MTK_HDMI_V2_CLOCK_MIN 27000 41 #define MTK_HDMI_V2_CLOCK_MAX 594000 42 43 #define HPD_PORD_HWIRQS (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT) 44 45 enum mtk_hdmi_v2_clk_id { 46 MTK_HDMI_V2_CLK_HDCP_SEL, 47 MTK_HDMI_V2_CLK_HDCP_24M_SEL, 48 MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI, 49 MTK_HDMI_V2_CLK_HDMI_APB_SEL, 50 MTK_HDMI_V2_CLK_COUNT, 51 }; 52 53 const char *const mtk_hdmi_v2_clk_names[MTK_HDMI_V2_CLK_COUNT] = { 54 [MTK_HDMI_V2_CLK_HDMI_APB_SEL] = "bus", 55 [MTK_HDMI_V2_CLK_HDCP_SEL] = "hdcp", 56 [MTK_HDMI_V2_CLK_HDCP_24M_SEL] = "hdcp24m", 57 [MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split", 58 }; 59 60 static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi) 61 { 62 regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0); 63 regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0); 64 } 65 66 static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, bool enable) 67 { 68 if (enable) 69 regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); 70 else 71 regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); 72 } 73 74 static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enable) 75 { 76 if (enable) { 77 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); 78 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); 79 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); 80 } else { 81 regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); 82 regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); 83 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); 84 } 85 } 86 87 static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bool enable) 88 { 89 struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc; 90 91 if (enable) 92 regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); 93 else 94 regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); 95 96 if (scdc->supported) { 97 if (scdc->scrambling.supported) 98 drm_scdc_set_scrambling(hdmi->curr_conn, enable); 99 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable); 100 } 101 } 102 103 static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable) 104 { 105 /* If enabled, sends a black image */ 106 if (enable) 107 regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); 108 else 109 regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); 110 } 111 112 static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable) 113 { 114 u32 aip, val; 115 116 if (!enable) { 117 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN); 118 return; 119 } 120 121 regmap_read(hdmi->regs, AIP_CTRL, &aip); 122 123 val = AUD_MUTE_FIFO_EN; 124 if (aip & DSD_EN) 125 val |= DSD_MUTE_EN; 126 127 regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val); 128 } 129 130 static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi) 131 { 132 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); 133 udelay(5); 134 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); 135 } 136 137 static inline u32 mtk_hdmi_v2_format_hw_packet(const u8 *buffer, u8 len) 138 { 139 unsigned short i; 140 u32 val = 0; 141 142 for (i = 0; i < len; i++) 143 val |= buffer[i] << (i * 8); 144 145 return val; 146 } 147 148 static int mtk_hdmi_v2_hdmi_write_audio_infoframe(struct drm_bridge *bridge, 149 const u8 *buffer, size_t len) 150 { 151 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 152 153 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); 154 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); 155 156 regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); 157 regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 3)); 158 regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2)); 159 regmap_write(hdmi->regs, TOP_AIF_PKT02, 0); 160 regmap_write(hdmi->regs, TOP_AIF_PKT03, 0); 161 162 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); 163 regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); 164 165 return 0; 166 } 167 168 static int mtk_hdmi_v2_hdmi_write_avi_infoframe(struct drm_bridge *bridge, 169 const u8 *buffer, size_t len) 170 { 171 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 172 173 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); 174 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); 175 176 regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); 177 regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); 178 regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3)); 179 regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4)); 180 regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3)); 181 regmap_write(hdmi->regs, TOP_AVI_PKT04, 0); 182 regmap_write(hdmi->regs, TOP_AVI_PKT05, 0); 183 184 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); 185 regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); 186 187 return 0; 188 } 189 190 static int mtk_hdmi_v2_hdmi_write_spd_infoframe(struct drm_bridge *bridge, 191 const u8 *buffer, size_t len) 192 { 193 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 194 195 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); 196 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); 197 198 regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); 199 regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); 200 regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3)); 201 regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4)); 202 regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3)); 203 regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&buffer[17], 4)); 204 regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&buffer[21], 3)); 205 regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&buffer[24], 4)); 206 regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]); 207 208 regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); 209 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); 210 211 return 0; 212 } 213 214 static int mtk_hdmi_v2_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, 215 const u8 *buffer, size_t len) 216 { 217 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 218 219 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); 220 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); 221 222 regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); 223 regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); 224 regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2)); 225 regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0); 226 regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0); 227 regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0); 228 regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0); 229 regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0); 230 regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0); 231 232 regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); 233 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); 234 235 return 0; 236 } 237 238 static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enable) 239 { 240 u32 val; 241 242 regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val); 243 244 if (enable) { 245 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE); 246 247 val |= C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE; 248 val |= C422_C420_CONFIG_OUT_CB_OR_CR; 249 val &= ~C422_C420_CONFIG_BYPASS; 250 regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); 251 252 regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE); 253 } else { 254 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE); 255 256 val &= ~(C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE); 257 val &= ~C422_C420_CONFIG_OUT_CB_OR_CR; 258 val |= C422_C420_CONFIG_BYPASS; 259 regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); 260 261 regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE); 262 } 263 } 264 265 static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi) 266 { 267 struct hdmi_codec_params *params = &hdmi->aud_param.codec_params; 268 struct hdmi_audio_infoframe frame; 269 u8 buffer[14]; 270 ssize_t ret; 271 272 memcpy(&frame, ¶ms->cea, sizeof(frame)); 273 274 ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 275 if (ret < 0) 276 return ret; 277 278 mtk_hdmi_v2_hdmi_write_audio_infoframe(&hdmi->bridge, buffer, sizeof(buffer)); 279 280 return 0; 281 } 282 283 static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, bool mute) 284 { 285 u32 val; 286 287 regmap_read(hdmi->regs, TOP_CFG01, &val); 288 val &= ~(CP_CLR_MUTE_EN | CP_SET_MUTE_EN); 289 290 if (mute) { 291 val |= CP_SET_MUTE_EN; 292 val &= ~CP_CLR_MUTE_EN; 293 } else { 294 val |= CP_CLR_MUTE_EN; 295 val &= ~CP_SET_MUTE_EN; 296 } 297 regmap_write(hdmi->regs, TOP_CFG01, val); 298 299 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN); 300 regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR); 301 } 302 303 static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable) 304 { 305 if (enable) 306 regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); 307 else 308 regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); 309 } 310 311 static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi) 312 { 313 u8 *ch_status = hdmi->aud_param.codec_params.iec.status; 314 315 /* Only the first 5 to 7 bytes of Channel Status contain useful information */ 316 regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4)); 317 regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3)); 318 } 319 320 static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 321 unsigned int sample_rate, 322 unsigned int clock) 323 { 324 unsigned int n, cts; 325 326 mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts); 327 328 regmap_write(hdmi->regs, AIP_N_VAL, n); 329 regmap_write(hdmi->regs, AIP_CTS_SVAL, cts); 330 } 331 332 static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable) 333 { 334 if (enable) 335 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); 336 else 337 regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); 338 } 339 340 static u32 mtk_hdmi_v2_aud_output_channel_map(u8 sd0, u8 sd1, u8 sd2, u8 sd3, 341 u8 sd4, u8 sd5, u8 sd6, u8 sd7) 342 { 343 u32 val; 344 345 /* 346 * Each of the Output Channels (0-7) can be mapped to get their input 347 * from any of the available Input Channels (0-7): this function 348 * takes input channel numbers and formats a value that must then 349 * be written to the TOP_AUD_MAP hardware register by the caller. 350 */ 351 val = FIELD_PREP(SD0_MAP, sd0) | FIELD_PREP(SD1_MAP, sd1); 352 val |= FIELD_PREP(SD2_MAP, sd2) | FIELD_PREP(SD3_MAP, sd3); 353 val |= FIELD_PREP(SD4_MAP, sd4) | FIELD_PREP(SD5_MAP, sd5); 354 val |= FIELD_PREP(SD6_MAP, sd6) | FIELD_PREP(SD7_MAP, sd7); 355 356 return val; 357 } 358 359 static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi, 360 unsigned char chnum, bool dsd_bypass) 361 { 362 u32 channel_map; 363 364 regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN); 365 regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN); 366 367 if (dsd_bypass) 368 channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 2, 4, 6, 1, 3, 5, 7); 369 else 370 channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 5, 1, 0, 3, 2, 4, 0); 371 372 regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map); 373 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); 374 } 375 376 static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 fifo_mapping) 377 { 378 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, 379 FIFO0_MAP | FIFO1_MAP | FIFO2_MAP | FIFO3_MAP, fifo_mapping); 380 } 381 382 static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 chnum) 383 { 384 regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum)); 385 } 386 387 static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum, u8 mapping) 388 { 389 u32 fifo_map; 390 u8 bdata; 391 392 switch (chnum) { 393 default: 394 case 2: 395 bdata = 0x1; 396 break; 397 case 3: 398 bdata = 0x3; 399 break; 400 case 6: 401 if (mapping == 0x0e) { 402 bdata = 0xf; 403 break; 404 } 405 fallthrough; 406 case 5: 407 bdata = 0x7; 408 break; 409 case 7: 410 case 8: 411 bdata = 0xf; 412 break; 413 } 414 415 /* Assign default FIFO mapping: SD0 to FIFO0, SD1 to FIFO1, etc. */ 416 fifo_map = FIELD_PREP(FIFO0_MAP, 0) | FIELD_PREP(FIFO1_MAP, 1); 417 fifo_map |= FIELD_PREP(FIFO2_MAP, 2) | FIELD_PREP(FIFO3_MAP, 3); 418 mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_map); 419 mtk_hdmi_v2_hw_i2s_ch_number(hdmi, bdata); 420 421 /* 422 * Set HDMI Audio packet layout indicator: 423 * Layout 0 is for two channels 424 * Layout 1 is for up to eight channels 425 */ 426 if (chnum == 2) 427 regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); 428 else 429 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); 430 } 431 432 static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt) 433 { 434 u32 val; 435 436 regmap_read(hdmi->regs, AIP_I2S_CTRL, &val); 437 val &= ~(WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT); 438 439 switch (fmt) { 440 case HDMI_I2S_MODE_RJT_24BIT: 441 case HDMI_I2S_MODE_RJT_16BIT: 442 val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT); 443 break; 444 case HDMI_I2S_MODE_LJT_24BIT: 445 case HDMI_I2S_MODE_LJT_16BIT: 446 val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT); 447 break; 448 case HDMI_I2S_MODE_I2S_24BIT: 449 case HDMI_I2S_MODE_I2S_16BIT: 450 default: 451 break; 452 } 453 454 regmap_write(hdmi->regs, AIP_I2S_CTRL, val); 455 } 456 457 static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool rise) 458 { 459 if (rise) 460 regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); 461 else 462 regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); 463 } 464 465 static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned int cbit) 466 { 467 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit); 468 } 469 470 static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int vbit) 471 { 472 /* V bit: 0 for PCM, 1 for Compressed data */ 473 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit); 474 } 475 476 static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsigned int is_lsb) 477 { 478 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb); 479 } 480 481 static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsigned int spdif_i2s) 482 { 483 regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s)); 484 } 485 486 static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type) 487 { 488 switch (channel_type) { 489 case HDMI_AUD_CHAN_TYPE_1_1: 490 case HDMI_AUD_CHAN_TYPE_2_1: 491 return 0x01; 492 case HDMI_AUD_CHAN_TYPE_3_0: 493 return 0x02; 494 case HDMI_AUD_CHAN_TYPE_3_1: 495 return 0x03; 496 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 497 case HDMI_AUD_CHAN_TYPE_4_0: 498 return 0x08; 499 case HDMI_AUD_CHAN_TYPE_5_1: 500 return 0x0b; 501 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 502 case HDMI_AUD_CHAN_TYPE_6_0: 503 case HDMI_AUD_CHAN_TYPE_6_0_CS: 504 case HDMI_AUD_CHAN_TYPE_6_0_CH: 505 case HDMI_AUD_CHAN_TYPE_6_0_OH: 506 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 507 return 0x0e; 508 case HDMI_AUD_CHAN_TYPE_1_0: 509 case HDMI_AUD_CHAN_TYPE_2_0: 510 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 511 case HDMI_AUD_CHAN_TYPE_4_1: 512 case HDMI_AUD_CHAN_TYPE_5_0: 513 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 514 case HDMI_AUD_CHAN_TYPE_6_1: 515 case HDMI_AUD_CHAN_TYPE_6_1_CS: 516 case HDMI_AUD_CHAN_TYPE_6_1_CH: 517 case HDMI_AUD_CHAN_TYPE_6_1_OH: 518 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 519 case HDMI_AUD_CHAN_TYPE_7_0: 520 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 521 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 522 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 523 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 524 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 525 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 526 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 527 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 528 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 529 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 530 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 531 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 532 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 533 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 534 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 535 case HDMI_AUD_CHAN_TYPE_7_1: 536 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 537 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 538 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 539 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 540 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 541 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 542 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 543 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 544 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 545 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 546 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 547 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 548 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 549 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 550 default: 551 return 0; 552 } 553 554 return 0; 555 } 556 557 static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi) 558 { 559 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 560 FIELD_PREP(MAX_2UI_I2S_HI_WRITE, MAX_2UI_I2S_LFE_CC_SWAP)); 561 } 562 563 static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass) 564 { 565 const u32 hbr_mask = SPDIF_EN | DSD_EN | HBRA_ON; 566 567 if (dsd_bypass) { 568 regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON); 569 regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN); 570 } else { 571 regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN); 572 regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE); 573 regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF); 574 regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4); 575 } 576 } 577 578 static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi) 579 { 580 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK); 581 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE); 582 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK); 583 584 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE, 585 FIELD_PREP(MAX_1UI_WRITE, 4)); 586 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE, 587 FIELD_PREP(MAX_2UI_SPDIF_WRITE, 9)); 588 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH, 589 FIELD_PREP(AUD_ERR_THRESH, 4)); 590 591 regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); 592 } 593 594 static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi) 595 { 596 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 597 struct hdmi_codec_params *codec_params = &aud_param->codec_params; 598 u8 i2s_ch_map; 599 u32 out_ch_map; 600 601 /* Write the default output channel map. CH0 maps to SD0, CH1 maps to SD1, etc */ 602 out_ch_map = mtk_hdmi_v2_aud_output_channel_map(0, 1, 2, 3, 4, 5, 6, 7); 603 regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map); 604 605 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0); 606 regmap_clear_bits(hdmi->regs, AIP_CTRL, 607 SPDIF_EN | DSD_EN | HBRA_ON | CTS_CAL_N4 | 608 HBR_FROM_SPDIF | SPDIF_INTERNAL_MODULE); 609 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1); 610 611 if (aud_param->aud_input_type == HDMI_AUD_INPUT_I2S) { 612 switch (aud_param->aud_codec) { 613 case HDMI_AUDIO_CODING_TYPE_DTS_HD: 614 case HDMI_AUDIO_CODING_TYPE_MLP: 615 mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); 616 mtk_hdmi_hbr_config(hdmi, true); 617 break; 618 case HDMI_AUDIO_CODING_TYPE_DSD: 619 mtk_hdmi_audio_dsd_config(hdmi, codec_params->channels, 0); 620 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, 1); 621 break; 622 default: 623 mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); 624 mtk_hdmi_i2s_sck_edge_rise(hdmi, true); 625 mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME); 626 mtk_hdmi_i2s_vbit(hdmi, 0); /* PCM data */ 627 mtk_hdmi_i2s_data_direction(hdmi, 0); /* MSB first */ 628 mtk_hdmi_v2_hw_audio_type(hdmi, HDMI_AUD_INPUT_I2S); 629 i2s_ch_map = mtk_hdmi_v2_get_i2s_ch_mapping(hdmi, 630 aud_param->aud_input_chan_type); 631 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, i2s_ch_map); 632 mtk_hdmi_v2_hw_i2s_ch_swap(hdmi); 633 } 634 } else { 635 if (codec_params->sample_rate == 768000 && 636 (aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_DTS_HD || 637 aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_MLP)) { 638 mtk_hdmi_hbr_config(hdmi, false); 639 } else { 640 mtk_hdmi_v2_hw_spdif_config(hdmi); 641 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, 2, 0); 642 } 643 } 644 } 645 646 static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi, bool ena) 647 { 648 if (ena) 649 regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); 650 else 651 regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); 652 } 653 654 static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi) 655 { 656 regmap_set_bits(hdmi->regs, AIP_CTRL, 657 AUD_SEL_OWRT | NO_MCLK_CTSGEN_SEL | MCLK_EN | CTS_REQ_EN); 658 regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN); 659 } 660 661 static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset) 662 { 663 const u32 arst_bits = RST4AUDIO | RST4AUDIO_FIFO | RST4AUDIO_ACR; 664 665 if (reset) 666 regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits); 667 else 668 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits); 669 } 670 671 static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi, 672 struct drm_display_mode *display_mode) 673 { 674 /* Shut down and reset the HDMI Audio HW to avoid glitching */ 675 mtk_hdmi_v2_hw_aud_mute(hdmi, true); 676 mtk_hdmi_v2_hw_aud_enable(hdmi, false); 677 mtk_hdmi_v2_audio_reset(hdmi, true); 678 679 /* Configure the main hardware params and get out of reset */ 680 mtk_hdmi_v2_aip_ctrl_init(hdmi); 681 mtk_hdmi_v2_aud_set_input(hdmi); 682 mtk_hdmi_v2_hw_aud_set_channel_status(hdmi); 683 mtk_hdmi_v2_setup_audio_infoframe(hdmi); 684 mtk_hdmi_v2_hw_audio_input_enable(hdmi, true); 685 mtk_hdmi_v2_audio_reset(hdmi, false); 686 687 /* Ignore N/CTS packet transmission requests and configure */ 688 mtk_hdmi_v2_hw_ncts_enable(hdmi, false); 689 mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rate, 690 display_mode->clock); 691 692 /* Wait for the HW to apply settings */ 693 usleep_range(25, 50); 694 695 /* Hardware is fully configured: enable TX of N/CTS pkts and unmute */ 696 mtk_hdmi_v2_hw_ncts_enable(hdmi, true); 697 mtk_hdmi_v2_hw_aud_enable(hdmi, true); 698 mtk_hdmi_v2_hw_aud_mute(hdmi, false); 699 } 700 701 static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi, 702 struct drm_connector_state *conn_state) 703 { 704 mtk_hdmi_v2_hw_reset(hdmi); 705 mtk_hdmi_v2_set_sw_hpd(hdmi, true); 706 udelay(2); 707 708 regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0); 709 710 /* 711 * Enable HDCP reauthentication interrupt: the HW uses this internally 712 * for the HPD state machine even if HDCP encryption is not enabled. 713 */ 714 regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT); 715 716 /* Enable hotplug and pord interrupts */ 717 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); 718 719 /* Force enabling HDCP HPD */ 720 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); 721 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); 722 723 /* Set 8 bits per pixel */ 724 regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE, 725 FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP)); 726 /* Disable generating deepcolor packets */ 727 regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN); 728 /* Disable adding deepcolor information to the general packet */ 729 regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD); 730 731 if (hdmi->curr_conn->display_info.is_hdmi) 732 regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); 733 else 734 regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); 735 736 udelay(5); 737 mtk_hdmi_v2_hw_vid_mute(hdmi, true); 738 mtk_hdmi_v2_hw_aud_mute(hdmi, true); 739 mtk_hdmi_v2_hw_gcp_avmute(hdmi, false); 740 741 regmap_update_bits(hdmi->regs, TOP_CFG01, 742 NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN); 743 usleep_range(100, 150); 744 745 /* Enable scrambling if tmds clock is 340MHz or more */ 746 mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO); 747 748 switch (conn_state->hdmi.output_format) { 749 default: 750 case HDMI_COLORSPACE_RGB: 751 case HDMI_COLORSPACE_YUV444: 752 /* Disable YUV420 downsampling for RGB and YUV444 */ 753 mtk_hdmi_yuv420_downsampling(hdmi, false); 754 break; 755 case HDMI_COLORSPACE_YUV422: 756 /* 757 * YUV420 downsampling is special and needs a bit of setup 758 * so we disable everything there before doing anything else. 759 * 760 * YUV422 downsampling instead just needs one bit to be set. 761 */ 762 mtk_hdmi_yuv420_downsampling(hdmi, false); 763 regmap_set_bits(hdmi->regs, VID_DOWNSAMPLE_CONFIG, 764 C444_C422_CONFIG_ENABLE); 765 break; 766 case HDMI_COLORSPACE_YUV420: 767 mtk_hdmi_yuv420_downsampling(hdmi, true); 768 break; 769 } 770 } 771 772 static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi, 773 struct drm_connector_state *conn_state, 774 struct drm_display_mode *mode) 775 { 776 union phy_configure_opts opts = { 777 .dp = { .link_rate = hdmi->mode.clock * KILO } 778 }; 779 int ret; 780 781 ret = phy_configure(hdmi->phy, &opts); 782 if (ret) 783 dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret); 784 785 mtk_hdmi_v2_change_video_resolution(hdmi, conn_state); 786 mtk_hdmi_v2_aud_output_config(hdmi, mode); 787 } 788 789 static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi) 790 { 791 int ret; 792 793 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); 794 if (ret) 795 return ret; 796 797 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); 798 if (ret) 799 goto disable_hdcp_clk; 800 801 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); 802 if (ret) 803 goto disable_hdcp_24m_clk; 804 805 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); 806 if (ret) 807 goto disable_bus_clk; 808 809 return 0; 810 811 disable_bus_clk: 812 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); 813 disable_hdcp_24m_clk: 814 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); 815 disable_hdcp_clk: 816 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); 817 818 return ret; 819 } 820 821 static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi) 822 { 823 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); 824 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); 825 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); 826 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); 827 } 828 829 static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi) 830 { 831 u8 hpd_pin_sta, pord_pin_sta; 832 u32 hpd_status; 833 834 regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status); 835 hpd_pin_sta = FIELD_GET(HPD_PIN_STA, hpd_status); 836 pord_pin_sta = FIELD_GET(PORD_PIN_STA, hpd_status); 837 838 /* 839 * Inform that the cable is plugged in (hpd_pin_sta) so that the 840 * sink can be powered on by switching the 5V VBUS as required by 841 * the HDMI spec for reading EDID and for HDMI Audio registers to 842 * be accessible. 843 * 844 * PORD detection succeeds only when the cable is plugged in and 845 * the sink is powered on: reaching that state means that the 846 * communication with the sink can be started. 847 * 848 * Please note that when the cable is plugged out the HPD pin will 849 * be the first one to fall, while PORD may still be in rise state 850 * for a few more milliseconds, so we decide HDMI_PLUG_OUT without 851 * checking PORD at all (we check only HPD falling for that). 852 */ 853 if (hpd_pin_sta && pord_pin_sta) 854 return HDMI_PLUG_IN_AND_SINK_POWER_ON; 855 else if (hpd_pin_sta) 856 return HDMI_PLUG_IN_ONLY; 857 else 858 return HDMI_PLUG_OUT; 859 } 860 861 static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg) 862 { 863 struct mtk_hdmi *hdmi = arg; 864 unsigned int irq_sta; 865 int ret = IRQ_HANDLED; 866 867 regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta); 868 869 /* Handle Hotplug Detection interrupts */ 870 if (irq_sta & HPD_PORD_HWIRQS) { 871 /* 872 * Disable the HPD/PORD IRQs now and until thread done to 873 * avoid interrupt storm that could happen with bad cables 874 */ 875 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false); 876 ret = IRQ_WAKE_THREAD; 877 878 /* Clear HPD/PORD irqs to avoid unwanted retriggering */ 879 regmap_write(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS); 880 regmap_write(hdmi->regs, TOP_INT_CLR00, 0); 881 } 882 883 return ret; 884 } 885 886 static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi) 887 { 888 enum hdmi_hpd_state hpd; 889 890 hpd = mtk_hdmi_v2_hpd_pord_status(hdmi); 891 if (hpd != hdmi->hpd) { 892 struct drm_encoder *encoder = hdmi->bridge.encoder; 893 894 hdmi->hpd = hpd; 895 896 if (encoder && encoder->dev) 897 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 898 } 899 900 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); 901 return IRQ_HANDLED; 902 } 903 904 static irqreturn_t mtk_hdmi_v2_isr_thread(int irq, void *arg) 905 { 906 struct mtk_hdmi *hdmi = arg; 907 908 /* 909 * Debounce HDMI monitor HPD status. 910 * Empirical testing shows that 30ms is enough wait 911 */ 912 msleep(30); 913 914 return __mtk_hdmi_v2_isr_thread(hdmi); 915 } 916 917 static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi) 918 { 919 bool was_active = pm_runtime_active(hdmi->dev); 920 int ret; 921 922 ret = pm_runtime_resume_and_get(hdmi->dev); 923 if (ret) { 924 dev_err(hdmi->dev, "Cannot resume HDMI\n"); 925 return ret; 926 } 927 928 ret = mtk_hdmi_v2_clk_enable(hdmi); 929 if (ret) { 930 pm_runtime_put(hdmi->dev); 931 return ret; 932 } 933 934 if (!was_active) { 935 mtk_hdmi_v2_hw_reset(hdmi); 936 mtk_hdmi_v2_set_sw_hpd(hdmi, true); 937 } 938 939 return 0; 940 } 941 942 static void mtk_hdmi_v2_disable(struct mtk_hdmi *hdmi) 943 { 944 mtk_hdmi_v2_clk_disable(hdmi); 945 pm_runtime_put_sync(hdmi->dev); 946 } 947 948 /* 949 * Bridge callbacks 950 */ 951 952 static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge, 953 struct drm_encoder *encoder, 954 enum drm_bridge_attach_flags flags) 955 { 956 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 957 int ret; 958 959 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { 960 DRM_ERROR("The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n"); 961 return -EINVAL; 962 } 963 if (hdmi->bridge.next_bridge) { 964 ret = drm_bridge_attach(encoder, hdmi->bridge.next_bridge, bridge, flags); 965 if (ret) 966 return ret; 967 } 968 969 ret = mtk_hdmi_v2_enable(hdmi); 970 if (ret) 971 return ret; 972 973 /* Enable Hotplug and Pord pins internal debouncing */ 974 regmap_set_bits(hdmi->regs, HPD_DDC_CTRL, 975 HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN); 976 977 irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN); 978 enable_irq(hdmi->irq); 979 980 /* 981 * Check if any HDMI monitor was connected before probing this driver 982 * and/or attaching the bridge, without debouncing: if so, we want to 983 * notify the DRM so that we start outputting an image ASAP. 984 * Note that calling the ISR thread function will also perform a HW 985 * registers write that enables both the HPD and Pord interrupts. 986 */ 987 __mtk_hdmi_v2_isr_thread(hdmi); 988 989 mtk_hdmi_v2_disable(hdmi); 990 991 return 0; 992 } 993 994 static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge) 995 { 996 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 997 998 WARN_ON(pm_runtime_active(hdmi->dev)); 999 1000 /* The controller is already powered off, just disable irq here */ 1001 disable_irq(hdmi->irq); 1002 } 1003 1004 static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged) 1005 { 1006 mutex_lock(&hdmi->update_plugged_status_lock); 1007 if (hdmi->plugged_cb && hdmi->codec_dev) 1008 hdmi->plugged_cb(hdmi->codec_dev, plugged); 1009 mutex_unlock(&hdmi->update_plugged_status_lock); 1010 } 1011 1012 static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge, 1013 struct drm_atomic_state *state) 1014 { 1015 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1016 struct drm_connector_state *conn_state; 1017 union phy_configure_opts opts = { 1018 .dp = { .link_rate = hdmi->mode.clock * KILO } 1019 }; 1020 int ret; 1021 1022 /* Power on the controller before trying to write to registers */ 1023 ret = mtk_hdmi_v2_enable(hdmi); 1024 if (WARN_ON(ret)) 1025 return; 1026 1027 /* Retrieve the connector through the atomic state */ 1028 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 1029 1030 conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn); 1031 if (WARN_ON(!conn_state)) 1032 return; 1033 1034 /* 1035 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable 1036 * stage to make sure that this IP is ready and clocked before the 1037 * mtk_dpi gets powered on and before it enables the output. 1038 */ 1039 mtk_hdmi_v2_output_set_display_mode(hdmi, conn_state, &hdmi->mode); 1040 1041 /* Reconfigure phy clock link with appropriate rate */ 1042 phy_configure(hdmi->phy, &opts); 1043 1044 /* Power on the PHY here to make sure that DPI_HDMI is clocked */ 1045 phy_power_on(hdmi->phy); 1046 1047 hdmi->powered = true; 1048 } 1049 1050 static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge, 1051 struct drm_atomic_state *state) 1052 { 1053 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1054 int ret; 1055 1056 if (WARN_ON(!hdmi->powered)) 1057 return; 1058 1059 ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state); 1060 if (ret) 1061 dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret); 1062 1063 mtk_hdmi_v2_hw_vid_mute(hdmi, false); 1064 1065 /* signal the connect event to audio codec */ 1066 mtk_hdmi_v2_handle_plugged_change(hdmi, true); 1067 1068 hdmi->enabled = true; 1069 } 1070 1071 static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge, 1072 struct drm_atomic_state *state) 1073 { 1074 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1075 1076 if (!hdmi->enabled) 1077 return; 1078 1079 mtk_hdmi_v2_hw_gcp_avmute(hdmi, true); 1080 msleep(50); 1081 mtk_hdmi_v2_hw_vid_mute(hdmi, true); 1082 mtk_hdmi_v2_hw_aud_mute(hdmi, true); 1083 msleep(50); 1084 1085 hdmi->enabled = false; 1086 } 1087 1088 static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge, 1089 struct drm_atomic_state *state) 1090 { 1091 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1092 1093 if (!hdmi->powered) 1094 return; 1095 1096 phy_power_off(hdmi->phy); 1097 hdmi->powered = false; 1098 1099 /* signal the disconnect event to audio codec */ 1100 mtk_hdmi_v2_handle_plugged_change(hdmi, false); 1101 1102 /* Power off */ 1103 mtk_hdmi_v2_disable(hdmi); 1104 } 1105 1106 static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_bridge *bridge, 1107 struct drm_connector *connector) 1108 { 1109 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1110 1111 return hdmi->hpd != HDMI_PLUG_OUT ? 1112 connector_status_connected : connector_status_disconnected; 1113 } 1114 1115 static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_bridge *bridge, 1116 struct drm_connector *connector) 1117 { 1118 return drm_edid_read(connector); 1119 } 1120 1121 static void mtk_hdmi_v2_hpd_enable(struct drm_bridge *bridge) 1122 { 1123 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1124 int ret; 1125 1126 ret = mtk_hdmi_v2_enable(hdmi); 1127 if (ret) { 1128 dev_err(hdmi->dev, "Cannot power on controller for HPD: %d\n", ret); 1129 return; 1130 } 1131 1132 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); 1133 } 1134 1135 static void mtk_hdmi_v2_hpd_disable(struct drm_bridge *bridge) 1136 { 1137 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1138 1139 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false); 1140 mtk_hdmi_v2_disable(hdmi); 1141 } 1142 1143 static enum drm_mode_status 1144 mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, 1145 const struct drm_display_mode *mode, 1146 unsigned long long tmds_rate) 1147 { 1148 if (mode->clock < MTK_HDMI_V2_CLOCK_MIN) 1149 return MODE_CLOCK_LOW; 1150 else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX) 1151 return MODE_CLOCK_HIGH; 1152 else 1153 return MODE_OK; 1154 } 1155 1156 static int mtk_hdmi_v2_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) 1157 { 1158 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1159 1160 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN_WR | AUD_EN); 1161 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); 1162 1163 return 0; 1164 } 1165 1166 static int mtk_hdmi_v2_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) 1167 { 1168 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1169 1170 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); 1171 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); 1172 1173 return 0; 1174 } 1175 1176 static int mtk_hdmi_v2_hdmi_clear_spd_infoframe(struct drm_bridge *bridge) 1177 { 1178 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1179 1180 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); 1181 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); 1182 1183 return 0; 1184 } 1185 1186 static int mtk_hdmi_v2_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) 1187 { 1188 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1189 1190 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); 1191 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); 1192 1193 return 0; 1194 } 1195 1196 static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable) 1197 { 1198 struct drm_display_mode *mode = &hdmi->mode; 1199 int abist_format = -EINVAL; 1200 bool interlaced; 1201 1202 if (!enable) { 1203 regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); 1204 return 0; 1205 } 1206 1207 if (!mode->hdisplay || !mode->vdisplay) 1208 return -EINVAL; 1209 1210 interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1211 1212 switch (mode->hdisplay) { 1213 case 720: 1214 if (mode->vdisplay == 480) 1215 abist_format = 2; 1216 else if (mode->vdisplay == 576) 1217 abist_format = 11; 1218 break; 1219 case 1280: 1220 if (mode->vdisplay == 720) 1221 abist_format = 3; 1222 break; 1223 case 1440: 1224 if (mode->vdisplay == 480) 1225 abist_format = interlaced ? 5 : 9; 1226 else if (mode->vdisplay == 576) 1227 abist_format = interlaced ? 14 : 18; 1228 break; 1229 case 1920: 1230 if (mode->vdisplay == 1080) 1231 abist_format = interlaced ? 4 : 10; 1232 break; 1233 case 3840: 1234 if (mode->vdisplay == 2160) 1235 abist_format = 25; 1236 break; 1237 case 4096: 1238 if (mode->vdisplay == 2160) 1239 abist_format = 26; 1240 break; 1241 default: 1242 break; 1243 } 1244 if (abist_format < 0) 1245 return abist_format; 1246 1247 regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT, 1248 FIELD_PREP(HDMI_ABIST_VIDEO_FORMAT, abist_format)); 1249 regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); 1250 return 0; 1251 } 1252 1253 static int mtk_hdmi_v2_debug_abist_show(struct seq_file *m, void *arg) 1254 { 1255 struct mtk_hdmi *hdmi = m->private; 1256 bool en; 1257 u32 val; 1258 int ret; 1259 1260 if (!hdmi) 1261 return -EINVAL; 1262 1263 ret = regmap_read(hdmi->regs, TOP_CFG00, &val); 1264 if (ret) 1265 return ret; 1266 1267 en = FIELD_GET(HDMI_ABIST_ENABLE, val); 1268 1269 seq_printf(m, "HDMI Automated Built-In Self Test: %s\n", 1270 en ? "Enabled" : "Disabled"); 1271 1272 return 0; 1273 } 1274 1275 static ssize_t mtk_hdmi_v2_debug_abist_write(struct file *file, 1276 const char __user *ubuf, 1277 size_t len, loff_t *offp) 1278 { 1279 struct seq_file *m = file->private_data; 1280 int ret; 1281 u32 en; 1282 1283 if (!m || !m->private || *offp) 1284 return -EINVAL; 1285 1286 ret = kstrtouint_from_user(ubuf, len, 0, &en); 1287 if (ret) 1288 return ret; 1289 1290 if (en < 0 || en > 1) 1291 return -EINVAL; 1292 1293 mtk_hdmi_v2_set_abist((struct mtk_hdmi *)m->private, en); 1294 return len; 1295 } 1296 1297 static int mtk_hdmi_v2_debug_abist_open(struct inode *inode, struct file *file) 1298 { 1299 return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private); 1300 } 1301 1302 static const struct file_operations mtk_hdmi_debug_abist_fops = { 1303 .owner = THIS_MODULE, 1304 .open = mtk_hdmi_v2_debug_abist_open, 1305 .read = seq_read, 1306 .write = mtk_hdmi_v2_debug_abist_write, 1307 .llseek = seq_lseek, 1308 .release = single_release, 1309 }; 1310 1311 static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 1312 { 1313 struct mtk_hdmi *dpi = hdmi_ctx_from_bridge(bridge); 1314 1315 debugfs_create_file("hdmi_abist", 0640, root, dpi, &mtk_hdmi_debug_abist_fops); 1316 } 1317 1318 static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = { 1319 .attach = mtk_hdmi_v2_bridge_attach, 1320 .detach = mtk_hdmi_v2_bridge_detach, 1321 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1322 .mode_set = mtk_hdmi_bridge_mode_set, 1323 .atomic_pre_enable = mtk_hdmi_v2_bridge_pre_enable, 1324 .atomic_enable = mtk_hdmi_v2_bridge_enable, 1325 .atomic_disable = mtk_hdmi_v2_bridge_disable, 1326 .atomic_post_disable = mtk_hdmi_v2_bridge_post_disable, 1327 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1328 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1329 .atomic_reset = drm_atomic_helper_bridge_reset, 1330 .detect = mtk_hdmi_v2_bridge_detect, 1331 .edid_read = mtk_hdmi_v2_bridge_edid_read, 1332 .hpd_enable = mtk_hdmi_v2_hpd_enable, 1333 .hpd_disable = mtk_hdmi_v2_hpd_disable, 1334 .hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid, 1335 .hdmi_clear_audio_infoframe = mtk_hdmi_v2_hdmi_clear_audio_infoframe, 1336 .hdmi_write_audio_infoframe = mtk_hdmi_v2_hdmi_write_audio_infoframe, 1337 .hdmi_clear_avi_infoframe = mtk_hdmi_v2_hdmi_clear_avi_infoframe, 1338 .hdmi_write_avi_infoframe = mtk_hdmi_v2_hdmi_write_avi_infoframe, 1339 .hdmi_clear_spd_infoframe = mtk_hdmi_v2_hdmi_clear_spd_infoframe, 1340 .hdmi_write_spd_infoframe = mtk_hdmi_v2_hdmi_write_spd_infoframe, 1341 .hdmi_clear_hdmi_infoframe = mtk_hdmi_v2_hdmi_clear_hdmi_infoframe, 1342 .hdmi_write_hdmi_infoframe = mtk_hdmi_v2_hdmi_write_hdmi_infoframe, 1343 .debugfs_init = mtk_hdmi_v2_debugfs_init, 1344 }; 1345 1346 /* 1347 * HDMI audio codec callbacks 1348 */ 1349 static int mtk_hdmi_v2_audio_hook_plugged_cb(struct device *dev, void *data, 1350 hdmi_codec_plugged_cb fn, 1351 struct device *codec_dev) 1352 { 1353 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1354 bool plugged; 1355 1356 if (!hdmi) 1357 return -ENODEV; 1358 1359 mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev); 1360 plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON); 1361 mtk_hdmi_v2_handle_plugged_change(hdmi, plugged); 1362 1363 return 0; 1364 } 1365 1366 static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data, 1367 struct hdmi_codec_daifmt *daifmt, 1368 struct hdmi_codec_params *params) 1369 { 1370 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1371 1372 if (hdmi->audio_enable) { 1373 mtk_hdmi_audio_params(hdmi, daifmt, params); 1374 mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode); 1375 } 1376 return 0; 1377 } 1378 1379 static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data) 1380 { 1381 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1382 1383 mtk_hdmi_v2_hw_aud_enable(hdmi, true); 1384 hdmi->audio_enable = true; 1385 1386 return 0; 1387 } 1388 1389 static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data) 1390 { 1391 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1392 1393 hdmi->audio_enable = false; 1394 mtk_hdmi_v2_hw_aud_enable(hdmi, false); 1395 } 1396 1397 static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, bool enable, int dir) 1398 { 1399 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1400 1401 mtk_hdmi_v2_hw_aud_mute(hdmi, enable); 1402 1403 return 0; 1404 } 1405 1406 static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops = { 1407 .hw_params = mtk_hdmi_v2_audio_hw_params, 1408 .audio_startup = mtk_hdmi_v2_audio_startup, 1409 .audio_shutdown = mtk_hdmi_v2_audio_shutdown, 1410 .mute_stream = mtk_hdmi_v2_audio_mute, 1411 .get_eld = mtk_hdmi_audio_get_eld, 1412 .hook_plugged_cb = mtk_hdmi_v2_audio_hook_plugged_cb, 1413 }; 1414 1415 static __maybe_unused int mtk_hdmi_v2_suspend(struct device *dev) 1416 { 1417 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1418 1419 mtk_hdmi_v2_disable(hdmi); 1420 1421 return 0; 1422 } 1423 1424 static __maybe_unused int mtk_hdmi_v2_resume(struct device *dev) 1425 { 1426 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1427 1428 return mtk_hdmi_v2_enable(hdmi); 1429 } 1430 1431 static SIMPLE_DEV_PM_OPS(mtk_hdmi_v2_pm_ops, mtk_hdmi_v2_suspend, mtk_hdmi_v2_resume); 1432 1433 static const struct mtk_hdmi_ver_conf mtk_hdmi_conf_v2 = { 1434 .bridge_funcs = &mtk_v2_hdmi_bridge_funcs, 1435 .codec_ops = &mtk_hdmi_v2_audio_codec_ops, 1436 .mtk_hdmi_clock_names = mtk_hdmi_v2_clk_names, 1437 .num_clocks = MTK_HDMI_V2_CLK_COUNT, 1438 .interlace_allowed = true, 1439 }; 1440 1441 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8188 = { 1442 .ver_conf = &mtk_hdmi_conf_v2, 1443 .reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8188 1444 }; 1445 1446 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 = { 1447 .ver_conf = &mtk_hdmi_conf_v2, 1448 .reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8195 1449 }; 1450 1451 static int mtk_hdmi_v2_probe(struct platform_device *pdev) 1452 { 1453 struct mtk_hdmi *hdmi; 1454 int ret; 1455 1456 /* Populate HDMI sub-devices if present */ 1457 ret = devm_of_platform_populate(&pdev->dev); 1458 if (ret) 1459 return ret; 1460 1461 hdmi = mtk_hdmi_common_probe(pdev); 1462 if (IS_ERR(hdmi)) 1463 return PTR_ERR(hdmi); 1464 1465 hdmi->hpd = HDMI_PLUG_OUT; 1466 1467 /* Disable all HW interrupts at probe stage */ 1468 mtk_hdmi_v2_hwirq_disable(hdmi); 1469 1470 /* 1471 * In case bootloader leaves HDMI enabled before booting, make 1472 * sure that any interrupt that was left is cleared by setting 1473 * all bits in the INT_CLR registers for all 32+19 interrupts. 1474 */ 1475 regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0)); 1476 regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0)); 1477 1478 /* Restore interrupt clearing registers to zero */ 1479 regmap_write(hdmi->regs, TOP_INT_CLR00, 0); 1480 regmap_write(hdmi->regs, TOP_INT_CLR01, 0); 1481 1482 /* 1483 * Install the ISR but keep it disabled: as the interrupts are 1484 * being set up in the .bridge_attach() callback which will 1485 * enable both the right HW IRQs and the ISR. 1486 */ 1487 irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN); 1488 ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr, 1489 mtk_hdmi_v2_isr_thread, 1490 IRQ_TYPE_LEVEL_HIGH, 1491 dev_name(&pdev->dev), hdmi); 1492 if (ret) 1493 return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n"); 1494 1495 ret = devm_pm_runtime_enable(&pdev->dev); 1496 if (ret) 1497 return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n"); 1498 1499 return 0; 1500 } 1501 1502 static void mtk_hdmi_v2_remove(struct platform_device *pdev) 1503 { 1504 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1505 1506 i2c_put_adapter(hdmi->ddc_adpt); 1507 } 1508 1509 static const struct of_device_id mtk_drm_hdmi_v2_of_ids[] = { 1510 { .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 }, 1511 { .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 }, 1512 { /* sentinel */ } 1513 }; 1514 MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_v2_of_ids); 1515 1516 static struct platform_driver mtk_hdmi_v2_driver = { 1517 .probe = mtk_hdmi_v2_probe, 1518 .remove = mtk_hdmi_v2_remove, 1519 .driver = { 1520 .name = "mediatek-drm-hdmi-v2", 1521 .of_match_table = mtk_drm_hdmi_v2_of_ids, 1522 .pm = &mtk_hdmi_v2_pm_ops, 1523 }, 1524 }; 1525 module_platform_driver(mtk_hdmi_v2_driver); 1526 1527 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>>"); 1528 MODULE_DESCRIPTION("MediaTek HDMIv2 Driver"); 1529 MODULE_LICENSE("GPL"); 1530 MODULE_IMPORT_NS("DRM_MTK_HDMI"); 1531