1*8f83f268SJie Qiu /* 2*8f83f268SJie Qiu * Copyright (c) 2014 MediaTek Inc. 3*8f83f268SJie Qiu * Author: Jie Qiu <jie.qiu@mediatek.com> 4*8f83f268SJie Qiu * 5*8f83f268SJie Qiu * This program is free software; you can redistribute it and/or modify 6*8f83f268SJie Qiu * it under the terms of the GNU General Public License version 2 as 7*8f83f268SJie Qiu * published by the Free Software Foundation. 8*8f83f268SJie Qiu * 9*8f83f268SJie Qiu * This program is distributed in the hope that it will be useful, 10*8f83f268SJie Qiu * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*8f83f268SJie Qiu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*8f83f268SJie Qiu * GNU General Public License for more details. 13*8f83f268SJie Qiu */ 14*8f83f268SJie Qiu #ifndef _MTK_HDMI_REGS_H 15*8f83f268SJie Qiu #define _MTK_HDMI_REGS_H 16*8f83f268SJie Qiu 17*8f83f268SJie Qiu #define GRL_INT_MASK 0x18 18*8f83f268SJie Qiu #define GRL_IFM_PORT 0x188 19*8f83f268SJie Qiu #define GRL_CH_SWAP 0x198 20*8f83f268SJie Qiu #define LR_SWAP BIT(0) 21*8f83f268SJie Qiu #define LFE_CC_SWAP BIT(1) 22*8f83f268SJie Qiu #define LSRS_SWAP BIT(2) 23*8f83f268SJie Qiu #define RLS_RRS_SWAP BIT(3) 24*8f83f268SJie Qiu #define LR_STATUS_SWAP BIT(4) 25*8f83f268SJie Qiu #define GRL_I2S_C_STA0 0x140 26*8f83f268SJie Qiu #define GRL_I2S_C_STA1 0x144 27*8f83f268SJie Qiu #define GRL_I2S_C_STA2 0x148 28*8f83f268SJie Qiu #define GRL_I2S_C_STA3 0x14C 29*8f83f268SJie Qiu #define GRL_I2S_C_STA4 0x150 30*8f83f268SJie Qiu #define GRL_I2S_UV 0x154 31*8f83f268SJie Qiu #define I2S_UV_V BIT(0) 32*8f83f268SJie Qiu #define I2S_UV_U BIT(1) 33*8f83f268SJie Qiu #define I2S_UV_CH_EN_MASK 0x3c 34*8f83f268SJie Qiu #define I2S_UV_CH_EN(x) BIT((x) + 2) 35*8f83f268SJie Qiu #define I2S_UV_TMDS_DEBUG BIT(6) 36*8f83f268SJie Qiu #define I2S_UV_NORMAL_INFO_INV BIT(7) 37*8f83f268SJie Qiu #define GRL_ACP_ISRC_CTRL 0x158 38*8f83f268SJie Qiu #define VS_EN BIT(0) 39*8f83f268SJie Qiu #define ACP_EN BIT(1) 40*8f83f268SJie Qiu #define ISRC1_EN BIT(2) 41*8f83f268SJie Qiu #define ISRC2_EN BIT(3) 42*8f83f268SJie Qiu #define GAMUT_EN BIT(4) 43*8f83f268SJie Qiu #define GRL_CTS_CTRL 0x160 44*8f83f268SJie Qiu #define CTS_CTRL_SOFT BIT(0) 45*8f83f268SJie Qiu #define GRL_INT 0x14 46*8f83f268SJie Qiu #define INT_MDI BIT(0) 47*8f83f268SJie Qiu #define INT_HDCP BIT(1) 48*8f83f268SJie Qiu #define INT_FIFO_O BIT(2) 49*8f83f268SJie Qiu #define INT_FIFO_U BIT(3) 50*8f83f268SJie Qiu #define INT_IFM_ERR BIT(4) 51*8f83f268SJie Qiu #define INT_INF_DONE BIT(5) 52*8f83f268SJie Qiu #define INT_NCTS_DONE BIT(6) 53*8f83f268SJie Qiu #define INT_CTRL_PKT_DONE BIT(7) 54*8f83f268SJie Qiu #define GRL_INT_MASK 0x18 55*8f83f268SJie Qiu #define GRL_CTRL 0x1C 56*8f83f268SJie Qiu #define CTRL_GEN_EN BIT(2) 57*8f83f268SJie Qiu #define CTRL_SPD_EN BIT(3) 58*8f83f268SJie Qiu #define CTRL_MPEG_EN BIT(4) 59*8f83f268SJie Qiu #define CTRL_AUDIO_EN BIT(5) 60*8f83f268SJie Qiu #define CTRL_AVI_EN BIT(6) 61*8f83f268SJie Qiu #define CTRL_AVMUTE BIT(7) 62*8f83f268SJie Qiu #define GRL_STATUS 0x20 63*8f83f268SJie Qiu #define STATUS_HTPLG BIT(0) 64*8f83f268SJie Qiu #define STATUS_PORD BIT(1) 65*8f83f268SJie Qiu #define GRL_DIVN 0x170 66*8f83f268SJie Qiu #define NCTS_WRI_ANYTIME BIT(6) 67*8f83f268SJie Qiu #define GRL_AUDIO_CFG 0x17C 68*8f83f268SJie Qiu #define AUDIO_ZERO BIT(0) 69*8f83f268SJie Qiu #define HIGH_BIT_RATE BIT(1) 70*8f83f268SJie Qiu #define SACD_DST BIT(2) 71*8f83f268SJie Qiu #define DST_NORMAL_DOUBLE BIT(3) 72*8f83f268SJie Qiu #define DSD_INV BIT(4) 73*8f83f268SJie Qiu #define LR_INV BIT(5) 74*8f83f268SJie Qiu #define LR_MIX BIT(6) 75*8f83f268SJie Qiu #define DSD_SEL BIT(7) 76*8f83f268SJie Qiu #define GRL_NCTS 0x184 77*8f83f268SJie Qiu #define GRL_CH_SW0 0x18C 78*8f83f268SJie Qiu #define GRL_CH_SW1 0x190 79*8f83f268SJie Qiu #define GRL_CH_SW2 0x194 80*8f83f268SJie Qiu #define CH_SWITCH(from, to) ((from) << ((to) * 3)) 81*8f83f268SJie Qiu #define GRL_INFOFRM_VER 0x19C 82*8f83f268SJie Qiu #define GRL_INFOFRM_TYPE 0x1A0 83*8f83f268SJie Qiu #define GRL_INFOFRM_LNG 0x1A4 84*8f83f268SJie Qiu #define GRL_MIX_CTRL 0x1B4 85*8f83f268SJie Qiu #define MIX_CTRL_SRC_EN BIT(0) 86*8f83f268SJie Qiu #define BYPASS_VOLUME BIT(1) 87*8f83f268SJie Qiu #define MIX_CTRL_FLAT BIT(7) 88*8f83f268SJie Qiu #define GRL_AOUT_CFG 0x1C4 89*8f83f268SJie Qiu #define AOUT_BNUM_SEL_MASK 0x03 90*8f83f268SJie Qiu #define AOUT_24BIT 0x00 91*8f83f268SJie Qiu #define AOUT_20BIT 0x02 92*8f83f268SJie Qiu #define AOUT_16BIT 0x03 93*8f83f268SJie Qiu #define AOUT_FIFO_ADAP_CTRL BIT(6) 94*8f83f268SJie Qiu #define AOUT_BURST_PREAMBLE_EN BIT(7) 95*8f83f268SJie Qiu #define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \ 96*8f83f268SJie Qiu AOUT_FIFO_ADAP_CTRL) 97*8f83f268SJie Qiu #define GRL_SHIFT_L1 0x1C0 98*8f83f268SJie Qiu #define GRL_SHIFT_R2 0x1B0 99*8f83f268SJie Qiu #define AUDIO_PACKET_OFF BIT(6) 100*8f83f268SJie Qiu #define GRL_CFG0 0x24 101*8f83f268SJie Qiu #define CFG0_I2S_MODE_MASK 0x3 102*8f83f268SJie Qiu #define CFG0_I2S_MODE_RTJ 0x1 103*8f83f268SJie Qiu #define CFG0_I2S_MODE_LTJ 0x0 104*8f83f268SJie Qiu #define CFG0_I2S_MODE_I2S 0x2 105*8f83f268SJie Qiu #define CFG0_W_LENGTH_MASK 0x30 106*8f83f268SJie Qiu #define CFG0_W_LENGTH_24BIT 0x00 107*8f83f268SJie Qiu #define CFG0_W_LENGTH_16BIT 0x10 108*8f83f268SJie Qiu #define GRL_CFG1 0x28 109*8f83f268SJie Qiu #define CFG1_EDG_SEL BIT(0) 110*8f83f268SJie Qiu #define CFG1_SPDIF BIT(1) 111*8f83f268SJie Qiu #define CFG1_DVI BIT(2) 112*8f83f268SJie Qiu #define CFG1_HDCP_DEBUG BIT(3) 113*8f83f268SJie Qiu #define GRL_CFG2 0x2c 114*8f83f268SJie Qiu #define CFG2_MHL_DE_SEL BIT(3) 115*8f83f268SJie Qiu #define CFG2_MHL_FAKE_DE_SEL BIT(4) 116*8f83f268SJie Qiu #define CFG2_MHL_DATA_REMAP BIT(5) 117*8f83f268SJie Qiu #define CFG2_NOTICE_EN BIT(6) 118*8f83f268SJie Qiu #define CFG2_ACLK_INV BIT(7) 119*8f83f268SJie Qiu #define GRL_CFG3 0x30 120*8f83f268SJie Qiu #define CFG3_AES_KEY_INDEX_MASK 0x3f 121*8f83f268SJie Qiu #define CFG3_CONTROL_PACKET_DELAY BIT(6) 122*8f83f268SJie Qiu #define CFG3_KSV_LOAD_START BIT(7) 123*8f83f268SJie Qiu #define GRL_CFG4 0x34 124*8f83f268SJie Qiu #define CFG4_AES_KEY_LOAD BIT(4) 125*8f83f268SJie Qiu #define CFG4_AV_UNMUTE_EN BIT(5) 126*8f83f268SJie Qiu #define CFG4_AV_UNMUTE_SET BIT(6) 127*8f83f268SJie Qiu #define CFG4_MHL_MODE BIT(7) 128*8f83f268SJie Qiu #define GRL_CFG5 0x38 129*8f83f268SJie Qiu #define CFG5_CD_RATIO_MASK 0x8F 130*8f83f268SJie Qiu #define CFG5_FS128 (0x1 << 4) 131*8f83f268SJie Qiu #define CFG5_FS256 (0x2 << 4) 132*8f83f268SJie Qiu #define CFG5_FS384 (0x3 << 4) 133*8f83f268SJie Qiu #define CFG5_FS512 (0x4 << 4) 134*8f83f268SJie Qiu #define CFG5_FS768 (0x6 << 4) 135*8f83f268SJie Qiu #define DUMMY_304 0x304 136*8f83f268SJie Qiu #define CHMO_SEL (0x3 << 2) 137*8f83f268SJie Qiu #define CHM1_SEL (0x3 << 4) 138*8f83f268SJie Qiu #define CHM2_SEL (0x3 << 6) 139*8f83f268SJie Qiu #define AUDIO_I2S_NCTS_SEL BIT(1) 140*8f83f268SJie Qiu #define AUDIO_I2S_NCTS_SEL_64 (1 << 1) 141*8f83f268SJie Qiu #define AUDIO_I2S_NCTS_SEL_128 (0 << 1) 142*8f83f268SJie Qiu #define NEW_GCP_CTRL BIT(0) 143*8f83f268SJie Qiu #define NEW_GCP_CTRL_MERGE BIT(0) 144*8f83f268SJie Qiu #define GRL_L_STATUS_0 0x200 145*8f83f268SJie Qiu #define GRL_L_STATUS_1 0x204 146*8f83f268SJie Qiu #define GRL_L_STATUS_2 0x208 147*8f83f268SJie Qiu #define GRL_L_STATUS_3 0x20c 148*8f83f268SJie Qiu #define GRL_L_STATUS_4 0x210 149*8f83f268SJie Qiu #define GRL_L_STATUS_5 0x214 150*8f83f268SJie Qiu #define GRL_L_STATUS_6 0x218 151*8f83f268SJie Qiu #define GRL_L_STATUS_7 0x21c 152*8f83f268SJie Qiu #define GRL_L_STATUS_8 0x220 153*8f83f268SJie Qiu #define GRL_L_STATUS_9 0x224 154*8f83f268SJie Qiu #define GRL_L_STATUS_10 0x228 155*8f83f268SJie Qiu #define GRL_L_STATUS_11 0x22c 156*8f83f268SJie Qiu #define GRL_L_STATUS_12 0x230 157*8f83f268SJie Qiu #define GRL_L_STATUS_13 0x234 158*8f83f268SJie Qiu #define GRL_L_STATUS_14 0x238 159*8f83f268SJie Qiu #define GRL_L_STATUS_15 0x23c 160*8f83f268SJie Qiu #define GRL_L_STATUS_16 0x240 161*8f83f268SJie Qiu #define GRL_L_STATUS_17 0x244 162*8f83f268SJie Qiu #define GRL_L_STATUS_18 0x248 163*8f83f268SJie Qiu #define GRL_L_STATUS_19 0x24c 164*8f83f268SJie Qiu #define GRL_L_STATUS_20 0x250 165*8f83f268SJie Qiu #define GRL_L_STATUS_21 0x254 166*8f83f268SJie Qiu #define GRL_L_STATUS_22 0x258 167*8f83f268SJie Qiu #define GRL_L_STATUS_23 0x25c 168*8f83f268SJie Qiu #define GRL_R_STATUS_0 0x260 169*8f83f268SJie Qiu #define GRL_R_STATUS_1 0x264 170*8f83f268SJie Qiu #define GRL_R_STATUS_2 0x268 171*8f83f268SJie Qiu #define GRL_R_STATUS_3 0x26c 172*8f83f268SJie Qiu #define GRL_R_STATUS_4 0x270 173*8f83f268SJie Qiu #define GRL_R_STATUS_5 0x274 174*8f83f268SJie Qiu #define GRL_R_STATUS_6 0x278 175*8f83f268SJie Qiu #define GRL_R_STATUS_7 0x27c 176*8f83f268SJie Qiu #define GRL_R_STATUS_8 0x280 177*8f83f268SJie Qiu #define GRL_R_STATUS_9 0x284 178*8f83f268SJie Qiu #define GRL_R_STATUS_10 0x288 179*8f83f268SJie Qiu #define GRL_R_STATUS_11 0x28c 180*8f83f268SJie Qiu #define GRL_R_STATUS_12 0x290 181*8f83f268SJie Qiu #define GRL_R_STATUS_13 0x294 182*8f83f268SJie Qiu #define GRL_R_STATUS_14 0x298 183*8f83f268SJie Qiu #define GRL_R_STATUS_15 0x29c 184*8f83f268SJie Qiu #define GRL_R_STATUS_16 0x2a0 185*8f83f268SJie Qiu #define GRL_R_STATUS_17 0x2a4 186*8f83f268SJie Qiu #define GRL_R_STATUS_18 0x2a8 187*8f83f268SJie Qiu #define GRL_R_STATUS_19 0x2ac 188*8f83f268SJie Qiu #define GRL_R_STATUS_20 0x2b0 189*8f83f268SJie Qiu #define GRL_R_STATUS_21 0x2b4 190*8f83f268SJie Qiu #define GRL_R_STATUS_22 0x2b8 191*8f83f268SJie Qiu #define GRL_R_STATUS_23 0x2bc 192*8f83f268SJie Qiu #define GRL_ABIST_CTRL0 0x2D4 193*8f83f268SJie Qiu #define GRL_ABIST_CTRL1 0x2D8 194*8f83f268SJie Qiu #define ABIST_EN BIT(7) 195*8f83f268SJie Qiu #define ABIST_DATA_FMT (0x7 << 0) 196*8f83f268SJie Qiu #define VIDEO_CFG_0 0x380 197*8f83f268SJie Qiu #define VIDEO_CFG_1 0x384 198*8f83f268SJie Qiu #define VIDEO_CFG_2 0x388 199*8f83f268SJie Qiu #define VIDEO_CFG_3 0x38c 200*8f83f268SJie Qiu #define VIDEO_CFG_4 0x390 201*8f83f268SJie Qiu #define VIDEO_SOURCE_SEL BIT(7) 202*8f83f268SJie Qiu #define NORMAL_PATH (1 << 7) 203*8f83f268SJie Qiu #define GEN_RGB (0 << 7) 204*8f83f268SJie Qiu 205*8f83f268SJie Qiu #define HDMI_SYS_CFG1C 0x000 206*8f83f268SJie Qiu #define HDMI_ON BIT(0) 207*8f83f268SJie Qiu #define HDMI_RST BIT(1) 208*8f83f268SJie Qiu #define ANLG_ON BIT(2) 209*8f83f268SJie Qiu #define CFG10_DVI BIT(3) 210*8f83f268SJie Qiu #define HDMI_TST BIT(3) 211*8f83f268SJie Qiu #define SYS_KEYMASK1 (0xff << 8) 212*8f83f268SJie Qiu #define SYS_KEYMASK2 (0xff << 16) 213*8f83f268SJie Qiu #define AUD_OUTSYNC_EN BIT(24) 214*8f83f268SJie Qiu #define AUD_OUTSYNC_PRE_EN BIT(25) 215*8f83f268SJie Qiu #define I2CM_ON BIT(26) 216*8f83f268SJie Qiu #define E2PROM_TYPE_8BIT BIT(27) 217*8f83f268SJie Qiu #define MCM_E2PROM_ON BIT(28) 218*8f83f268SJie Qiu #define EXT_E2PROM_ON BIT(29) 219*8f83f268SJie Qiu #define HTPLG_PIN_SEL_OFF BIT(30) 220*8f83f268SJie Qiu #define AES_EFUSE_ENABLE BIT(31) 221*8f83f268SJie Qiu #define HDMI_SYS_CFG20 0x004 222*8f83f268SJie Qiu #define DEEP_COLOR_MODE_MASK (3 << 1) 223*8f83f268SJie Qiu #define COLOR_8BIT_MODE (0 << 1) 224*8f83f268SJie Qiu #define COLOR_10BIT_MODE (1 << 1) 225*8f83f268SJie Qiu #define COLOR_12BIT_MODE (2 << 1) 226*8f83f268SJie Qiu #define COLOR_16BIT_MODE (3 << 1) 227*8f83f268SJie Qiu #define DEEP_COLOR_EN BIT(0) 228*8f83f268SJie Qiu #define HDMI_AUDIO_TEST_SEL BIT(8) 229*8f83f268SJie Qiu #define HDMI2P0_EN BIT(11) 230*8f83f268SJie Qiu #define HDMI_OUT_FIFO_EN BIT(16) 231*8f83f268SJie Qiu #define HDMI_OUT_FIFO_CLK_INV BIT(17) 232*8f83f268SJie Qiu #define MHL_MODE_ON BIT(28) 233*8f83f268SJie Qiu #define MHL_PP_MODE BIT(29) 234*8f83f268SJie Qiu #define MHL_SYNC_AUTO_EN BIT(30) 235*8f83f268SJie Qiu #define HDMI_PCLK_FREE_RUN BIT(31) 236*8f83f268SJie Qiu 237*8f83f268SJie Qiu #endif 238