1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/i2c.h> 9 #include <linux/time.h> 10 #include <linux/delay.h> 11 #include <linux/errno.h> 12 #include <linux/err.h> 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/slab.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 22 #include "mtk_drm_drv.h" 23 24 #define SIF1_CLOK (288) 25 #define DDC_DDCMCTL0 (0x0) 26 #define DDCM_ODRAIN BIT(31) 27 #define DDCM_CLK_DIV_OFFSET (16) 28 #define DDCM_CLK_DIV_MASK (0xfff << 16) 29 #define DDCM_CS_STATUS BIT(4) 30 #define DDCM_SCL_STATE BIT(3) 31 #define DDCM_SDA_STATE BIT(2) 32 #define DDCM_SM0EN BIT(1) 33 #define DDCM_SCL_STRECH BIT(0) 34 #define DDC_DDCMCTL1 (0x4) 35 #define DDCM_ACK_OFFSET (16) 36 #define DDCM_ACK_MASK (0xff << 16) 37 #define DDCM_PGLEN_OFFSET (8) 38 #define DDCM_PGLEN_MASK (0x7 << 8) 39 #define DDCM_SIF_MODE_OFFSET (4) 40 #define DDCM_SIF_MODE_MASK (0x7 << 4) 41 #define DDCM_START (0x1) 42 #define DDCM_WRITE_DATA (0x2) 43 #define DDCM_STOP (0x3) 44 #define DDCM_READ_DATA_NO_ACK (0x4) 45 #define DDCM_READ_DATA_ACK (0x5) 46 #define DDCM_TRI BIT(0) 47 #define DDC_DDCMD0 (0x8) 48 #define DDCM_DATA3 (0xff << 24) 49 #define DDCM_DATA2 (0xff << 16) 50 #define DDCM_DATA1 (0xff << 8) 51 #define DDCM_DATA0 (0xff << 0) 52 #define DDC_DDCMD1 (0xc) 53 #define DDCM_DATA7 (0xff << 24) 54 #define DDCM_DATA6 (0xff << 16) 55 #define DDCM_DATA5 (0xff << 8) 56 #define DDCM_DATA4 (0xff << 0) 57 58 struct mtk_hdmi_ddc { 59 struct i2c_adapter adap; 60 struct clk *clk; 61 void __iomem *regs; 62 }; 63 64 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, 65 unsigned int val) 66 { 67 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); 68 } 69 70 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, 71 unsigned int val) 72 { 73 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); 74 } 75 76 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, 77 unsigned int val) 78 { 79 return (readl(ddc->regs + offset) & val) == val; 80 } 81 82 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, 83 unsigned int mask, unsigned int shift, 84 unsigned int val) 85 { 86 unsigned int tmp; 87 88 tmp = readl(ddc->regs + offset); 89 tmp &= ~mask; 90 tmp |= (val << shift) & mask; 91 writel(tmp, ddc->regs + offset); 92 } 93 94 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc, 95 unsigned int offset, unsigned int mask, 96 unsigned int shift) 97 { 98 return (readl(ddc->regs + offset) & mask) >> shift; 99 } 100 101 static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode) 102 { 103 u32 val; 104 105 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK, 106 DDCM_SIF_MODE_OFFSET, mode); 107 sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI); 108 readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val, 109 (val & DDCM_TRI) != DDCM_TRI, 4, 20000); 110 } 111 112 static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg) 113 { 114 struct device *dev = ddc->adap.dev.parent; 115 u32 remain_count, ack_count, ack_final, read_count, temp_count; 116 u32 index = 0; 117 u32 ack; 118 int i; 119 120 ddcm_trigger_mode(ddc, DDCM_START); 121 sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01); 122 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, 123 0x00); 124 ddcm_trigger_mode(ddc, DDCM_WRITE_DATA); 125 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); 126 dev_dbg(dev, "ack = 0x%x\n", ack); 127 if (ack != 0x01) { 128 dev_err(dev, "i2c ack err!\n"); 129 return -ENXIO; 130 } 131 132 remain_count = msg->len; 133 ack_count = (msg->len - 1) / 8; 134 ack_final = 0; 135 136 while (remain_count > 0) { 137 if (ack_count > 0) { 138 read_count = 8; 139 ack_final = 0; 140 ack_count--; 141 } else { 142 read_count = remain_count; 143 ack_final = 1; 144 } 145 146 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, 147 DDCM_PGLEN_OFFSET, read_count - 1); 148 ddcm_trigger_mode(ddc, (ack_final == 1) ? 149 DDCM_READ_DATA_NO_ACK : 150 DDCM_READ_DATA_ACK); 151 152 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, 153 DDCM_ACK_OFFSET); 154 temp_count = 0; 155 while (((ack & (1 << temp_count)) != 0) && (temp_count < 8)) 156 temp_count++; 157 if (((ack_final == 1) && (temp_count != (read_count - 1))) || 158 ((ack_final == 0) && (temp_count != read_count))) { 159 dev_err(dev, "Address NACK! ACK(0x%x)\n", ack); 160 break; 161 } 162 163 for (i = read_count; i >= 1; i--) { 164 int shift; 165 int offset; 166 167 if (i > 4) { 168 offset = DDC_DDCMD1; 169 shift = (i - 5) * 8; 170 } else { 171 offset = DDC_DDCMD0; 172 shift = (i - 1) * 8; 173 } 174 175 msg->buf[index + i - 1] = sif_read_mask(ddc, offset, 176 0xff << shift, 177 shift); 178 } 179 180 remain_count -= read_count; 181 index += read_count; 182 } 183 184 return 0; 185 } 186 187 static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg) 188 { 189 struct device *dev = ddc->adap.dev.parent; 190 u32 ack; 191 192 ddcm_trigger_mode(ddc, DDCM_START); 193 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1); 194 sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]); 195 sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET, 196 0x1); 197 ddcm_trigger_mode(ddc, DDCM_WRITE_DATA); 198 199 ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET); 200 dev_dbg(dev, "ack = %d\n", ack); 201 202 if (ack != 0x03) { 203 dev_err(dev, "i2c ack err!\n"); 204 return -EIO; 205 } 206 207 return 0; 208 } 209 210 static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter, 211 struct i2c_msg *msgs, int num) 212 { 213 struct mtk_hdmi_ddc *ddc = adapter->algo_data; 214 struct device *dev = adapter->dev.parent; 215 int ret; 216 int i; 217 218 if (!ddc) { 219 dev_err(dev, "invalid arguments\n"); 220 return -EINVAL; 221 } 222 223 sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH); 224 sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN); 225 sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN); 226 227 if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) { 228 dev_err(dev, "ddc line is busy!\n"); 229 return -EBUSY; 230 } 231 232 sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK, 233 DDCM_CLK_DIV_OFFSET, SIF1_CLOK); 234 235 for (i = 0; i < num; i++) { 236 struct i2c_msg *msg = &msgs[i]; 237 238 dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n", 239 msg->addr, msg->flags, msg->len); 240 241 if (msg->flags & I2C_M_RD) 242 ret = mtk_hdmi_ddc_read_msg(ddc, msg); 243 else 244 ret = mtk_hdmi_ddc_write_msg(ddc, msg); 245 if (ret < 0) 246 goto xfer_end; 247 } 248 249 ddcm_trigger_mode(ddc, DDCM_STOP); 250 251 return i; 252 253 xfer_end: 254 ddcm_trigger_mode(ddc, DDCM_STOP); 255 dev_err(dev, "ddc failed!\n"); 256 return ret; 257 } 258 259 static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter) 260 { 261 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 262 } 263 264 static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = { 265 .master_xfer = mtk_hdmi_ddc_xfer, 266 .functionality = mtk_hdmi_ddc_func, 267 }; 268 269 static int mtk_hdmi_ddc_probe(struct platform_device *pdev) 270 { 271 struct device *dev = &pdev->dev; 272 struct mtk_hdmi_ddc *ddc; 273 struct resource *mem; 274 int ret; 275 276 ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL); 277 if (!ddc) 278 return -ENOMEM; 279 280 ddc->clk = devm_clk_get(dev, "ddc-i2c"); 281 if (IS_ERR(ddc->clk)) 282 return dev_err_probe(dev, PTR_ERR(ddc->clk), 283 "get ddc_clk failed\n"); 284 285 ddc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 286 if (IS_ERR(ddc->regs)) 287 return PTR_ERR(ddc->regs); 288 289 ret = clk_prepare_enable(ddc->clk); 290 if (ret) 291 return dev_err_probe(dev, ret, "enable ddc clk failed!\n"); 292 293 strscpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name)); 294 ddc->adap.owner = THIS_MODULE; 295 ddc->adap.algo = &mtk_hdmi_ddc_algorithm; 296 ddc->adap.retries = 3; 297 ddc->adap.dev.of_node = dev->of_node; 298 ddc->adap.algo_data = ddc; 299 ddc->adap.dev.parent = &pdev->dev; 300 301 ret = i2c_add_adapter(&ddc->adap); 302 if (ret < 0) { 303 clk_disable_unprepare(ddc->clk); 304 return dev_err_probe(dev, ret, "failed to add bus to i2c core\n"); 305 } 306 307 platform_set_drvdata(pdev, ddc); 308 309 dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap); 310 dev_dbg(dev, "ddc->clk: %p\n", ddc->clk); 311 dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start, 312 &mem->end); 313 314 return 0; 315 } 316 317 static void mtk_hdmi_ddc_remove(struct platform_device *pdev) 318 { 319 struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev); 320 321 i2c_del_adapter(&ddc->adap); 322 clk_disable_unprepare(ddc->clk); 323 } 324 325 static const struct of_device_id mtk_hdmi_ddc_match[] = { 326 { .compatible = "mediatek,mt8173-hdmi-ddc", }, 327 {}, 328 }; 329 MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_match); 330 331 struct platform_driver mtk_hdmi_ddc_driver = { 332 .probe = mtk_hdmi_ddc_probe, 333 .remove = mtk_hdmi_ddc_remove, 334 .driver = { 335 .name = "mediatek-hdmi-ddc", 336 .of_match_table = mtk_hdmi_ddc_match, 337 }, 338 }; 339 module_platform_driver(mtk_hdmi_ddc_driver); 340 341 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 342 MODULE_DESCRIPTION("MediaTek HDMI DDC Driver"); 343 MODULE_LICENSE("GPL v2"); 344