1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 */ 5 6 #include <drm/drm_blend.h> 7 #include <drm/drm_fourcc.h> 8 #include <drm/drm_framebuffer.h> 9 #include <linux/clk.h> 10 #include <linux/component.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 #include <linux/soc/mediatek/mtk-cmdq.h> 16 #include <linux/soc/mediatek/mtk-mmsys.h> 17 18 #include "mtk_crtc.h" 19 #include "mtk_ddp_comp.h" 20 #include "mtk_drm_drv.h" 21 #include "mtk_ethdr.h" 22 23 #define MIX_INTEN 0x4 24 #define MIX_FME_CPL_INTEN BIT(1) 25 #define MIX_INTSTA 0x8 26 #define MIX_EN 0xc 27 #define MIX_RST 0x14 28 #define MIX_ROI_SIZE 0x18 29 #define MIX_DATAPATH_CON 0x1c 30 #define OUTPUT_NO_RND BIT(3) 31 #define SOURCE_RGB_SEL BIT(7) 32 #define BACKGROUND_RELAY (4 << 9) 33 #define MIX_ROI_BGCLR 0x20 34 #define BGCLR_BLACK 0xff000000 35 #define MIX_SRC_CON 0x24 36 #define MIX_SRC_L0_EN BIT(0) 37 #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) 38 #define NON_PREMULTI_SOURCE (2 << 12) 39 #define PREMULTI_SOURCE (3 << 12) 40 #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) 41 #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) 42 #define MIX_FUNC_DCM0 0x120 43 #define MIX_FUNC_DCM1 0x124 44 #define MIX_FUNC_DCM_ENABLE 0xffffffff 45 46 #define HDR_VDO_FE_0804_HDR_DM_FE 0x804 47 #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd 48 #define HDR_GFX_FE_0204_GFX_HDR_FE 0x204 49 #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd 50 #define HDR_VDO_BE_0204_VDO_DM_BE 0x204 51 #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e 52 53 #define MIXER_INX_MODE_BYPASS 0 54 #define MIXER_INX_MODE_EVEN_EXTEND 1 55 #define MIXER_ALPHA_AEN BIT(8) 56 #define MIXER_ALPHA 0xff 57 #define ETHDR_CLK_NUM 13 58 59 enum mtk_ethdr_comp_id { 60 ETHDR_MIXER, 61 ETHDR_VDO_FE0, 62 ETHDR_VDO_FE1, 63 ETHDR_GFX_FE0, 64 ETHDR_GFX_FE1, 65 ETHDR_VDO_BE, 66 ETHDR_ADL_DS, 67 ETHDR_ID_MAX 68 }; 69 70 struct mtk_ethdr_comp { 71 struct device *dev; 72 void __iomem *regs; 73 struct cmdq_client_reg cmdq_base; 74 }; 75 76 struct mtk_ethdr { 77 struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX]; 78 struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM]; 79 struct device *mmsys_dev; 80 void (*vblank_cb)(void *data); 81 void *vblank_cb_data; 82 int irq; 83 struct reset_control *reset_ctl; 84 }; 85 86 static const char * const ethdr_clk_str[] = { 87 "ethdr_top", 88 "mixer", 89 "vdo_fe0", 90 "vdo_fe1", 91 "gfx_fe0", 92 "gfx_fe1", 93 "vdo_be", 94 "adl_ds", 95 "vdo_fe0_async", 96 "vdo_fe1_async", 97 "gfx_fe0_async", 98 "gfx_fe1_async", 99 "vdo_be_async", 100 }; 101 102 void mtk_ethdr_register_vblank_cb(struct device *dev, 103 void (*vblank_cb)(void *), 104 void *vblank_cb_data) 105 { 106 struct mtk_ethdr *priv = dev_get_drvdata(dev); 107 108 priv->vblank_cb = vblank_cb; 109 priv->vblank_cb_data = vblank_cb_data; 110 } 111 112 void mtk_ethdr_unregister_vblank_cb(struct device *dev) 113 { 114 struct mtk_ethdr *priv = dev_get_drvdata(dev); 115 116 priv->vblank_cb = NULL; 117 priv->vblank_cb_data = NULL; 118 } 119 120 void mtk_ethdr_enable_vblank(struct device *dev) 121 { 122 struct mtk_ethdr *priv = dev_get_drvdata(dev); 123 124 writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); 125 } 126 127 void mtk_ethdr_disable_vblank(struct device *dev) 128 { 129 struct mtk_ethdr *priv = dev_get_drvdata(dev); 130 131 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN); 132 } 133 134 static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id) 135 { 136 struct mtk_ethdr *priv = dev_id; 137 138 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA); 139 140 if (!priv->vblank_cb) 141 return IRQ_NONE; 142 143 priv->vblank_cb(priv->vblank_cb_data); 144 145 return IRQ_HANDLED; 146 } 147 148 void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, 149 struct mtk_plane_state *state, 150 struct cmdq_pkt *cmdq_pkt) 151 { 152 struct mtk_ethdr *priv = dev_get_drvdata(dev); 153 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; 154 struct mtk_plane_pending_state *pending = &state->pending; 155 unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x; 156 unsigned int align_width = ALIGN_DOWN(pending->width, 2); 157 unsigned int alpha_con = 0; 158 bool replace_src_a = false; 159 160 dev_dbg(dev, "%s+ idx:%d", __func__, idx); 161 162 if (idx >= 4) 163 return; 164 165 if (!pending->enable || !pending->width || !pending->height) { 166 /* 167 * instead of disabling layer with MIX_SRC_CON directly 168 * set the size to 0 to avoid screen shift due to mixer 169 * mode switch (hardware behavior) 170 */ 171 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); 172 return; 173 } 174 175 if (state->base.fb) { 176 alpha_con |= MIXER_ALPHA_AEN; 177 alpha_con |= state->base.alpha & MIXER_ALPHA; 178 } 179 180 if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) 181 alpha_con |= PREMULTI_SOURCE; 182 else 183 alpha_con |= NON_PREMULTI_SOURCE; 184 185 if ((state->base.fb && !state->base.fb->format->has_alpha) || 186 state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) { 187 /* 188 * Mixer doesn't support CONST_BLD mode, 189 * use a trick to make the output equivalent 190 */ 191 replace_src_a = true; 192 } 193 194 mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, 195 MIXER_ALPHA, 196 pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : 197 MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); 198 199 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, 200 mixer->regs, MIX_L_SRC_SIZE(idx)); 201 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); 202 mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); 203 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, 204 BIT(idx)); 205 } 206 207 void mtk_ethdr_config(struct device *dev, unsigned int w, 208 unsigned int h, unsigned int vrefresh, 209 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 210 { 211 struct mtk_ethdr *priv = dev_get_drvdata(dev); 212 struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0]; 213 struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1]; 214 struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0]; 215 struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1]; 216 struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE]; 217 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; 218 219 dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h); 220 221 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, 222 vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE); 223 224 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, 225 vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE); 226 227 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, 228 gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE); 229 230 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, 231 gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE); 232 233 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base, 234 vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE); 235 236 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0); 237 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1); 238 mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE); 239 mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR); 240 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, 241 MIX_L_SRC_CON(0)); 242 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, 243 MIX_L_SRC_CON(1)); 244 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, 245 MIX_L_SRC_CON(2)); 246 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, 247 MIX_L_SRC_CON(3)); 248 mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0)); 249 mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY, 250 &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON); 251 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs, 252 MIX_SRC_CON, MIX_SRC_L0_EN); 253 254 mtk_mmsys_hdr_config(priv->mmsys_dev, w / 2, h, cmdq_pkt); 255 mtk_mmsys_mixer_in_channel_swap(priv->mmsys_dev, 4, 0, cmdq_pkt); 256 } 257 258 void mtk_ethdr_start(struct device *dev) 259 { 260 struct mtk_ethdr *priv = dev_get_drvdata(dev); 261 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; 262 263 writel(1, mixer->regs + MIX_EN); 264 } 265 266 void mtk_ethdr_stop(struct device *dev) 267 { 268 struct mtk_ethdr *priv = dev_get_drvdata(dev); 269 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER]; 270 271 writel(0, mixer->regs + MIX_EN); 272 writel(1, mixer->regs + MIX_RST); 273 reset_control_reset(priv->reset_ctl); 274 writel(0, mixer->regs + MIX_RST); 275 } 276 277 int mtk_ethdr_clk_enable(struct device *dev) 278 { 279 int ret; 280 struct mtk_ethdr *priv = dev_get_drvdata(dev); 281 282 ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk); 283 if (ret) 284 dev_err(dev, 285 "ethdr_clk prepare enable failed\n"); 286 return ret; 287 } 288 289 void mtk_ethdr_clk_disable(struct device *dev) 290 { 291 struct mtk_ethdr *priv = dev_get_drvdata(dev); 292 293 clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk); 294 } 295 296 static int mtk_ethdr_bind(struct device *dev, struct device *master, 297 void *data) 298 { 299 struct mtk_ethdr *priv = dev_get_drvdata(dev); 300 301 priv->mmsys_dev = data; 302 return 0; 303 } 304 305 static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data) 306 { 307 } 308 309 static const struct component_ops mtk_ethdr_component_ops = { 310 .bind = mtk_ethdr_bind, 311 .unbind = mtk_ethdr_unbind, 312 }; 313 314 static int mtk_ethdr_probe(struct platform_device *pdev) 315 { 316 struct device *dev = &pdev->dev; 317 struct mtk_ethdr *priv; 318 int ret; 319 int i; 320 321 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 322 if (!priv) 323 return -ENOMEM; 324 325 for (i = 0; i < ETHDR_ID_MAX; i++) { 326 priv->ethdr_comp[i].dev = dev; 327 priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i); 328 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 329 ret = cmdq_dev_get_client_reg(dev, 330 &priv->ethdr_comp[i].cmdq_base, i); 331 if (ret) 332 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 333 #endif 334 dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i); 335 } 336 337 for (i = 0; i < ETHDR_CLK_NUM; i++) 338 priv->ethdr_clk[i].id = ethdr_clk_str[i]; 339 ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk); 340 if (ret) 341 return ret; 342 343 priv->irq = platform_get_irq(pdev, 0); 344 if (priv->irq < 0) 345 priv->irq = 0; 346 347 if (priv->irq) { 348 ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler, 349 IRQF_TRIGGER_NONE, dev_name(dev), priv); 350 if (ret < 0) 351 return dev_err_probe(dev, ret, 352 "Failed to request irq %d\n", 353 priv->irq); 354 } 355 356 priv->reset_ctl = devm_reset_control_array_get_optional_exclusive(dev); 357 if (IS_ERR(priv->reset_ctl)) 358 return dev_err_probe(dev, PTR_ERR(priv->reset_ctl), 359 "cannot get ethdr reset control\n"); 360 361 platform_set_drvdata(pdev, priv); 362 363 ret = component_add(dev, &mtk_ethdr_component_ops); 364 if (ret) 365 return dev_err_probe(dev, ret, "Failed to add component\n"); 366 367 return 0; 368 } 369 370 static void mtk_ethdr_remove(struct platform_device *pdev) 371 { 372 component_del(&pdev->dev, &mtk_ethdr_component_ops); 373 } 374 375 static const struct of_device_id mtk_ethdr_driver_dt_match[] = { 376 { .compatible = "mediatek,mt8195-disp-ethdr"}, 377 {}, 378 }; 379 380 MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match); 381 382 struct platform_driver mtk_ethdr_driver = { 383 .probe = mtk_ethdr_probe, 384 .remove_new = mtk_ethdr_remove, 385 .driver = { 386 .name = "mediatek-disp-ethdr", 387 .of_match_table = mtk_ethdr_driver_dt_match, 388 }, 389 }; 390