1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/iopoll.h> 10 #include <linux/irq.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/phy/phy.h> 14 #include <linux/platform_device.h> 15 #include <linux/reset.h> 16 #include <linux/units.h> 17 18 #include <video/mipi_display.h> 19 #include <video/videomode.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_bridge_connector.h> 24 #include <drm/drm_mipi_dsi.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_probe_helper.h> 29 #include <drm/drm_simple_kms_helper.h> 30 31 #include "mtk_ddp_comp.h" 32 #include "mtk_disp_drv.h" 33 #include "mtk_drm_drv.h" 34 35 #define DSI_START 0x00 36 37 #define DSI_INTEN 0x08 38 39 #define DSI_INTSTA 0x0c 40 #define LPRX_RD_RDY_INT_FLAG BIT(0) 41 #define CMD_DONE_INT_FLAG BIT(1) 42 #define TE_RDY_INT_FLAG BIT(2) 43 #define VM_DONE_INT_FLAG BIT(3) 44 #define EXT_TE_RDY_INT_FLAG BIT(4) 45 #define DSI_BUSY BIT(31) 46 47 #define DSI_CON_CTRL 0x10 48 #define DSI_RESET BIT(0) 49 #define DSI_EN BIT(1) 50 #define DPHY_RESET BIT(2) 51 52 #define DSI_MODE_CTRL 0x14 53 #define MODE (3) 54 #define CMD_MODE 0 55 #define SYNC_PULSE_MODE 1 56 #define SYNC_EVENT_MODE 2 57 #define BURST_MODE 3 58 #define FRM_MODE BIT(16) 59 #define MIX_MODE BIT(17) 60 61 #define DSI_TXRX_CTRL 0x18 62 #define VC_NUM BIT(1) 63 #define LANE_NUM GENMASK(5, 2) 64 #define DIS_EOT BIT(6) 65 #define NULL_EN BIT(7) 66 #define TE_FREERUN BIT(8) 67 #define EXT_TE_EN BIT(9) 68 #define EXT_TE_EDGE BIT(10) 69 #define MAX_RTN_SIZE GENMASK(15, 12) 70 #define HSTX_CKLP_EN BIT(16) 71 72 #define DSI_PSCTRL 0x1c 73 #define DSI_PS_WC GENMASK(13, 0) 74 #define DSI_PS_SEL GENMASK(17, 16) 75 #define PACKED_PS_16BIT_RGB565 0 76 #define PACKED_PS_18BIT_RGB666 1 77 #define LOOSELY_PS_24BIT_RGB666 2 78 #define PACKED_PS_24BIT_RGB888 3 79 80 #define DSI_VSA_NL 0x20 81 #define DSI_VBP_NL 0x24 82 #define DSI_VFP_NL 0x28 83 #define DSI_VACT_NL 0x2C 84 #define VACT_NL GENMASK(14, 0) 85 #define DSI_SIZE_CON 0x38 86 #define DSI_HEIGHT GENMASK(30, 16) 87 #define DSI_WIDTH GENMASK(14, 0) 88 #define DSI_HSA_WC 0x50 89 #define DSI_HBP_WC 0x54 90 #define DSI_HFP_WC 0x58 91 92 #define DSI_CMDQ_SIZE 0x60 93 #define CMDQ_SIZE 0x3f 94 #define CMDQ_SIZE_SEL BIT(15) 95 96 #define DSI_HSTX_CKL_WC 0x64 97 98 #define DSI_RX_DATA0 0x74 99 #define DSI_RX_DATA1 0x78 100 #define DSI_RX_DATA2 0x7c 101 #define DSI_RX_DATA3 0x80 102 103 #define DSI_RACK 0x84 104 #define RACK BIT(0) 105 106 #define DSI_PHY_LCCON 0x104 107 #define LC_HS_TX_EN BIT(0) 108 #define LC_ULPM_EN BIT(1) 109 #define LC_WAKEUP_EN BIT(2) 110 111 #define DSI_PHY_LD0CON 0x108 112 #define LD0_HS_TX_EN BIT(0) 113 #define LD0_ULPM_EN BIT(1) 114 #define LD0_WAKEUP_EN BIT(2) 115 116 #define DSI_PHY_TIMECON0 0x110 117 #define LPX GENMASK(7, 0) 118 #define HS_PREP GENMASK(15, 8) 119 #define HS_ZERO GENMASK(23, 16) 120 #define HS_TRAIL GENMASK(31, 24) 121 122 #define DSI_PHY_TIMECON1 0x114 123 #define TA_GO GENMASK(7, 0) 124 #define TA_SURE GENMASK(15, 8) 125 #define TA_GET GENMASK(23, 16) 126 #define DA_HS_EXIT GENMASK(31, 24) 127 128 #define DSI_PHY_TIMECON2 0x118 129 #define CONT_DET GENMASK(7, 0) 130 #define DA_HS_SYNC GENMASK(15, 8) 131 #define CLK_ZERO GENMASK(23, 16) 132 #define CLK_TRAIL GENMASK(31, 24) 133 134 #define DSI_PHY_TIMECON3 0x11c 135 #define CLK_HS_PREP GENMASK(7, 0) 136 #define CLK_HS_POST GENMASK(15, 8) 137 #define CLK_HS_EXIT GENMASK(23, 16) 138 139 #define DSI_VM_CMD_CON 0x130 140 #define VM_CMD_EN BIT(0) 141 #define TS_VFP_EN BIT(5) 142 143 #define DSI_SHADOW_DEBUG 0x190U 144 #define FORCE_COMMIT BIT(0) 145 #define BYPASS_SHADOW BIT(1) 146 147 /* CMDQ related bits */ 148 #define CONFIG GENMASK(7, 0) 149 #define SHORT_PACKET 0 150 #define LONG_PACKET 2 151 #define BTA BIT(2) 152 #define DATA_ID GENMASK(15, 8) 153 #define DATA_0 GENMASK(23, 16) 154 #define DATA_1 GENMASK(31, 24) 155 156 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) 157 158 #define MTK_DSI_HOST_IS_READ(type) \ 159 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 160 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 161 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 162 (type == MIPI_DSI_DCS_READ)) 163 164 struct mtk_phy_timing { 165 u32 lpx; 166 u32 da_hs_prepare; 167 u32 da_hs_zero; 168 u32 da_hs_trail; 169 170 u32 ta_go; 171 u32 ta_sure; 172 u32 ta_get; 173 u32 da_hs_exit; 174 175 u32 clk_hs_zero; 176 u32 clk_hs_trail; 177 178 u32 clk_hs_prepare; 179 u32 clk_hs_post; 180 u32 clk_hs_exit; 181 }; 182 183 struct phy; 184 185 struct mtk_dsi_driver_data { 186 const u32 reg_cmdq_off; 187 bool has_shadow_ctl; 188 bool has_size_ctl; 189 bool cmdq_long_packet_ctl; 190 }; 191 192 struct mtk_dsi { 193 struct device *dev; 194 struct mipi_dsi_host host; 195 struct drm_encoder encoder; 196 struct drm_bridge bridge; 197 struct drm_bridge *next_bridge; 198 struct drm_connector *connector; 199 struct phy *phy; 200 201 void __iomem *regs; 202 203 struct clk *engine_clk; 204 struct clk *digital_clk; 205 struct clk *hs_clk; 206 207 u32 data_rate; 208 209 unsigned long mode_flags; 210 enum mipi_dsi_pixel_format format; 211 unsigned int lanes; 212 struct videomode vm; 213 struct mtk_phy_timing phy_timing; 214 int refcount; 215 bool enabled; 216 bool lanes_ready; 217 u32 irq_data; 218 wait_queue_head_t irq_wait_queue; 219 const struct mtk_dsi_driver_data *driver_data; 220 }; 221 222 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b) 223 { 224 return container_of(b, struct mtk_dsi, bridge); 225 } 226 227 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h) 228 { 229 return container_of(h, struct mtk_dsi, host); 230 } 231 232 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) 233 { 234 u32 temp = readl(dsi->regs + offset); 235 236 writel((temp & ~mask) | (data & mask), dsi->regs + offset); 237 } 238 239 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) 240 { 241 u32 timcon0, timcon1, timcon2, timcon3; 242 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); 243 struct mtk_phy_timing *timing = &dsi->phy_timing; 244 245 timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; 246 timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1; 247 timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 - 248 timing->da_hs_prepare; 249 timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1; 250 251 timing->ta_go = 4 * timing->lpx; 252 timing->ta_sure = 3 * timing->lpx / 2; 253 timing->ta_get = 5 * timing->lpx; 254 timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; 255 256 timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1; 257 timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + 1; 258 timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1; 259 timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 - 260 timing->clk_hs_prepare; 261 timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; 262 263 timcon0 = FIELD_PREP(LPX, timing->lpx) | 264 FIELD_PREP(HS_PREP, timing->da_hs_prepare) | 265 FIELD_PREP(HS_ZERO, timing->da_hs_zero) | 266 FIELD_PREP(HS_TRAIL, timing->da_hs_trail); 267 268 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) | 269 FIELD_PREP(TA_SURE, timing->ta_sure) | 270 FIELD_PREP(TA_GET, timing->ta_get) | 271 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit); 272 273 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) | 274 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) | 275 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail); 276 277 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) | 278 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) | 279 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit); 280 281 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); 282 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); 283 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); 284 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); 285 } 286 287 static void mtk_dsi_enable(struct mtk_dsi *dsi) 288 { 289 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN); 290 } 291 292 static void mtk_dsi_disable(struct mtk_dsi *dsi) 293 { 294 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0); 295 } 296 297 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi) 298 { 299 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET); 300 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0); 301 } 302 303 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi) 304 { 305 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET); 306 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0); 307 } 308 309 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi) 310 { 311 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 312 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 313 } 314 315 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi) 316 { 317 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0); 318 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN); 319 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0); 320 } 321 322 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi) 323 { 324 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0); 325 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 326 } 327 328 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi) 329 { 330 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0); 331 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN); 332 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0); 333 } 334 335 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi) 336 { 337 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN; 338 } 339 340 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter) 341 { 342 if (enter && !mtk_dsi_clk_hs_state(dsi)) 343 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN); 344 else if (!enter && mtk_dsi_clk_hs_state(dsi)) 345 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0); 346 } 347 348 static void mtk_dsi_set_mode(struct mtk_dsi *dsi) 349 { 350 u32 vid_mode = CMD_MODE; 351 352 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 353 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 354 vid_mode = BURST_MODE; 355 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 356 vid_mode = SYNC_PULSE_MODE; 357 else 358 vid_mode = SYNC_EVENT_MODE; 359 } 360 361 writel(vid_mode, dsi->regs + DSI_MODE_CTRL); 362 } 363 364 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) 365 { 366 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN); 367 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); 368 } 369 370 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) 371 { 372 u32 regval, tmp_reg = 0; 373 u8 i; 374 375 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */ 376 for (i = 0; i < dsi->lanes; i++) 377 tmp_reg |= BIT(i); 378 379 regval = FIELD_PREP(LANE_NUM, tmp_reg); 380 381 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 382 regval |= HSTX_CKLP_EN; 383 384 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 385 regval |= DIS_EOT; 386 387 writel(regval, dsi->regs + DSI_TXRX_CTRL); 388 } 389 390 static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) 391 { 392 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl; 393 394 if (dsi->format == MIPI_DSI_FMT_RGB565) 395 dsi_buf_bpp = 2; 396 else 397 dsi_buf_bpp = 3; 398 399 /* Word count */ 400 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp); 401 ps_val = ps_wc; 402 403 /* Pixel Stream type */ 404 switch (dsi->format) { 405 default: 406 fallthrough; 407 case MIPI_DSI_FMT_RGB888: 408 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888); 409 break; 410 case MIPI_DSI_FMT_RGB666: 411 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666); 412 break; 413 case MIPI_DSI_FMT_RGB666_PACKED: 414 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666); 415 break; 416 case MIPI_DSI_FMT_RGB565: 417 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565); 418 break; 419 } 420 421 if (config_vact) { 422 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive); 423 writel(vact_nl, dsi->regs + DSI_VACT_NL); 424 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); 425 } 426 writel(ps_val, dsi->regs + DSI_PSCTRL); 427 } 428 429 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) 430 { 431 u32 horizontal_sync_active_byte; 432 u32 horizontal_backporch_byte; 433 u32 horizontal_frontporch_byte; 434 u32 horizontal_front_back_byte; 435 u32 data_phy_cycles_byte; 436 u32 dsi_tmp_buf_bpp, data_phy_cycles; 437 u32 delta; 438 struct mtk_phy_timing *timing = &dsi->phy_timing; 439 440 struct videomode *vm = &dsi->vm; 441 442 if (dsi->format == MIPI_DSI_FMT_RGB565) 443 dsi_tmp_buf_bpp = 2; 444 else 445 dsi_tmp_buf_bpp = 3; 446 447 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL); 448 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL); 449 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); 450 writel(vm->vactive, dsi->regs + DSI_VACT_NL); 451 452 if (dsi->driver_data->has_size_ctl) 453 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) | 454 FIELD_PREP(DSI_WIDTH, vm->hactive), 455 dsi->regs + DSI_SIZE_CON); 456 457 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); 458 459 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 460 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10; 461 else 462 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * 463 dsi_tmp_buf_bpp - 10; 464 465 data_phy_cycles = timing->lpx + timing->da_hs_prepare + 466 timing->da_hs_zero + timing->da_hs_exit + 3; 467 468 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; 469 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2; 470 471 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp; 472 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte; 473 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta; 474 475 if (horizontal_front_back_byte > data_phy_cycles_byte) { 476 horizontal_frontporch_byte -= data_phy_cycles_byte * 477 horizontal_frontporch_byte / 478 horizontal_front_back_byte; 479 480 horizontal_backporch_byte -= data_phy_cycles_byte * 481 horizontal_backporch_byte / 482 horizontal_front_back_byte; 483 } else { 484 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); 485 } 486 487 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) && 488 (dsi->lanes == 4)) { 489 horizontal_sync_active_byte = 490 roundup(horizontal_sync_active_byte, dsi->lanes) - 2; 491 horizontal_frontporch_byte = 492 roundup(horizontal_frontporch_byte, dsi->lanes) - 2; 493 horizontal_backporch_byte = 494 roundup(horizontal_backporch_byte, dsi->lanes) - 2; 495 horizontal_backporch_byte -= 496 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; 497 } 498 499 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); 500 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 501 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); 502 503 mtk_dsi_ps_control(dsi, false); 504 } 505 506 static void mtk_dsi_start(struct mtk_dsi *dsi) 507 { 508 writel(0, dsi->regs + DSI_START); 509 writel(1, dsi->regs + DSI_START); 510 } 511 512 static void mtk_dsi_stop(struct mtk_dsi *dsi) 513 { 514 writel(0, dsi->regs + DSI_START); 515 } 516 517 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) 518 { 519 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL); 520 } 521 522 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) 523 { 524 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 525 526 writel(inten, dsi->regs + DSI_INTEN); 527 } 528 529 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) 530 { 531 dsi->irq_data |= irq_bit; 532 } 533 534 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit) 535 { 536 dsi->irq_data &= ~irq_bit; 537 } 538 539 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag, 540 unsigned int timeout) 541 { 542 s32 ret = 0; 543 unsigned long jiffies = msecs_to_jiffies(timeout); 544 545 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue, 546 dsi->irq_data & irq_flag, 547 jiffies); 548 if (ret == 0) { 549 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag); 550 551 mtk_dsi_enable(dsi); 552 mtk_dsi_reset_engine(dsi); 553 } 554 555 return ret; 556 } 557 558 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) 559 { 560 struct mtk_dsi *dsi = dev_id; 561 u32 status, tmp; 562 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; 563 564 status = readl(dsi->regs + DSI_INTSTA) & flag; 565 566 if (status) { 567 do { 568 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); 569 tmp = readl(dsi->regs + DSI_INTSTA); 570 } while (tmp & DSI_BUSY); 571 572 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); 573 mtk_dsi_irq_data_set(dsi, status); 574 wake_up_interruptible(&dsi->irq_wait_queue); 575 } 576 577 return IRQ_HANDLED; 578 } 579 580 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) 581 { 582 mtk_dsi_irq_data_clear(dsi, irq_flag); 583 mtk_dsi_set_cmd_mode(dsi); 584 585 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { 586 DRM_ERROR("failed to switch cmd mode\n"); 587 return -ETIME; 588 } else { 589 return 0; 590 } 591 } 592 593 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 594 { 595 struct device *dev = dsi->host.dev; 596 int ret; 597 u32 bit_per_pixel; 598 599 if (++dsi->refcount != 1) 600 return 0; 601 602 ret = mipi_dsi_pixel_format_to_bpp(dsi->format); 603 if (ret < 0) { 604 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format); 605 return ret; 606 } 607 bit_per_pixel = ret; 608 609 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel, 610 dsi->lanes); 611 612 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); 613 if (ret < 0) { 614 dev_err(dev, "Failed to set data rate: %d\n", ret); 615 goto err_refcount; 616 } 617 618 phy_power_on(dsi->phy); 619 620 ret = clk_prepare_enable(dsi->engine_clk); 621 if (ret < 0) { 622 dev_err(dev, "Failed to enable engine clock: %d\n", ret); 623 goto err_phy_power_off; 624 } 625 626 ret = clk_prepare_enable(dsi->digital_clk); 627 if (ret < 0) { 628 dev_err(dev, "Failed to enable digital clock: %d\n", ret); 629 goto err_disable_engine_clk; 630 } 631 632 mtk_dsi_enable(dsi); 633 634 if (dsi->driver_data->has_shadow_ctl) 635 writel(FORCE_COMMIT | BYPASS_SHADOW, 636 dsi->regs + DSI_SHADOW_DEBUG); 637 638 mtk_dsi_reset_engine(dsi); 639 mtk_dsi_phy_timconfig(dsi); 640 641 mtk_dsi_ps_control(dsi, true); 642 mtk_dsi_set_vm_cmd(dsi); 643 mtk_dsi_config_vdo_timing(dsi); 644 mtk_dsi_set_interrupt_enable(dsi); 645 646 return 0; 647 err_disable_engine_clk: 648 clk_disable_unprepare(dsi->engine_clk); 649 err_phy_power_off: 650 phy_power_off(dsi->phy); 651 err_refcount: 652 dsi->refcount--; 653 return ret; 654 } 655 656 static void mtk_dsi_poweroff(struct mtk_dsi *dsi) 657 { 658 if (WARN_ON(dsi->refcount == 0)) 659 return; 660 661 if (--dsi->refcount != 0) 662 return; 663 664 /* 665 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since 666 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(), 667 * which needs irq for vblank, and mtk_dsi_stop() will disable irq. 668 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), 669 * after dsi is fully set. 670 */ 671 mtk_dsi_stop(dsi); 672 673 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 674 mtk_dsi_reset_engine(dsi); 675 mtk_dsi_lane0_ulp_mode_enter(dsi); 676 mtk_dsi_clk_ulp_mode_enter(dsi); 677 /* set the lane number as 0 to pull down mipi */ 678 writel(0, dsi->regs + DSI_TXRX_CTRL); 679 680 mtk_dsi_disable(dsi); 681 682 clk_disable_unprepare(dsi->engine_clk); 683 clk_disable_unprepare(dsi->digital_clk); 684 685 phy_power_off(dsi->phy); 686 687 dsi->lanes_ready = false; 688 } 689 690 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 691 { 692 if (!dsi->lanes_ready) { 693 dsi->lanes_ready = true; 694 mtk_dsi_rxtx_control(dsi); 695 usleep_range(30, 100); 696 mtk_dsi_reset_dphy(dsi); 697 mtk_dsi_clk_ulp_mode_leave(dsi); 698 mtk_dsi_lane0_ulp_mode_leave(dsi); 699 mtk_dsi_clk_hs_mode(dsi, 0); 700 usleep_range(1000, 3000); 701 /* The reaction time after pulling up the mipi signal for dsi_rx */ 702 } 703 } 704 705 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 706 { 707 if (dsi->enabled) 708 return; 709 710 mtk_dsi_lane_ready(dsi); 711 mtk_dsi_set_mode(dsi); 712 mtk_dsi_clk_hs_mode(dsi, 1); 713 714 mtk_dsi_start(dsi); 715 716 dsi->enabled = true; 717 } 718 719 static void mtk_output_dsi_disable(struct mtk_dsi *dsi) 720 { 721 if (!dsi->enabled) 722 return; 723 724 dsi->enabled = false; 725 } 726 727 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge, 728 enum drm_bridge_attach_flags flags) 729 { 730 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 731 732 /* Attach the panel or bridge to the dsi bridge */ 733 return drm_bridge_attach(bridge->encoder, dsi->next_bridge, 734 &dsi->bridge, flags); 735 } 736 737 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge, 738 const struct drm_display_mode *mode, 739 const struct drm_display_mode *adjusted) 740 { 741 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 742 743 drm_display_mode_to_videomode(adjusted, &dsi->vm); 744 } 745 746 static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge, 747 struct drm_bridge_state *old_bridge_state) 748 { 749 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 750 751 mtk_output_dsi_disable(dsi); 752 } 753 754 static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 755 struct drm_bridge_state *old_bridge_state) 756 { 757 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 758 759 if (dsi->refcount == 0) 760 return; 761 762 mtk_output_dsi_enable(dsi); 763 } 764 765 static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 766 struct drm_bridge_state *old_bridge_state) 767 { 768 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 769 int ret; 770 771 ret = mtk_dsi_poweron(dsi); 772 if (ret < 0) 773 DRM_ERROR("failed to power on dsi\n"); 774 } 775 776 static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge, 777 struct drm_bridge_state *old_bridge_state) 778 { 779 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 780 781 mtk_dsi_poweroff(dsi); 782 } 783 784 static enum drm_mode_status 785 mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge, 786 const struct drm_display_info *info, 787 const struct drm_display_mode *mode) 788 { 789 struct mtk_dsi *dsi = bridge_to_dsi(bridge); 790 int bpp; 791 792 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 793 if (bpp < 0) 794 return MODE_ERROR; 795 796 if (mode->clock * bpp / dsi->lanes > 1500000) 797 return MODE_CLOCK_HIGH; 798 799 return MODE_OK; 800 } 801 802 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { 803 .attach = mtk_dsi_bridge_attach, 804 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 805 .atomic_disable = mtk_dsi_bridge_atomic_disable, 806 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 807 .atomic_enable = mtk_dsi_bridge_atomic_enable, 808 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable, 809 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable, 810 .atomic_reset = drm_atomic_helper_bridge_reset, 811 .mode_valid = mtk_dsi_bridge_mode_valid, 812 .mode_set = mtk_dsi_bridge_mode_set, 813 }; 814 815 void mtk_dsi_ddp_start(struct device *dev) 816 { 817 struct mtk_dsi *dsi = dev_get_drvdata(dev); 818 819 mtk_dsi_poweron(dsi); 820 } 821 822 void mtk_dsi_ddp_stop(struct device *dev) 823 { 824 struct mtk_dsi *dsi = dev_get_drvdata(dev); 825 826 mtk_dsi_poweroff(dsi); 827 } 828 829 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) 830 { 831 int ret; 832 833 ret = drm_simple_encoder_init(drm, &dsi->encoder, 834 DRM_MODE_ENCODER_DSI); 835 if (ret) { 836 DRM_ERROR("Failed to encoder init to drm\n"); 837 return ret; 838 } 839 840 ret = mtk_find_possible_crtcs(drm, dsi->host.dev); 841 if (ret < 0) 842 goto err_cleanup_encoder; 843 dsi->encoder.possible_crtcs = ret; 844 845 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 846 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 847 if (ret) 848 goto err_cleanup_encoder; 849 850 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder); 851 if (IS_ERR(dsi->connector)) { 852 DRM_ERROR("Unable to create bridge connector\n"); 853 ret = PTR_ERR(dsi->connector); 854 goto err_cleanup_encoder; 855 } 856 drm_connector_attach_encoder(dsi->connector, &dsi->encoder); 857 858 return 0; 859 860 err_cleanup_encoder: 861 drm_encoder_cleanup(&dsi->encoder); 862 return ret; 863 } 864 865 unsigned int mtk_dsi_encoder_index(struct device *dev) 866 { 867 struct mtk_dsi *dsi = dev_get_drvdata(dev); 868 unsigned int encoder_index = drm_encoder_index(&dsi->encoder); 869 870 dev_dbg(dev, "encoder index:%d\n", encoder_index); 871 return encoder_index; 872 } 873 874 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) 875 { 876 int ret; 877 struct drm_device *drm = data; 878 struct mtk_dsi *dsi = dev_get_drvdata(dev); 879 880 ret = mtk_dsi_encoder_init(drm, dsi); 881 if (ret) 882 return ret; 883 884 return device_reset_optional(dev); 885 } 886 887 static void mtk_dsi_unbind(struct device *dev, struct device *master, 888 void *data) 889 { 890 struct mtk_dsi *dsi = dev_get_drvdata(dev); 891 892 drm_encoder_cleanup(&dsi->encoder); 893 } 894 895 static const struct component_ops mtk_dsi_component_ops = { 896 .bind = mtk_dsi_bind, 897 .unbind = mtk_dsi_unbind, 898 }; 899 900 static int mtk_dsi_host_attach(struct mipi_dsi_host *host, 901 struct mipi_dsi_device *device) 902 { 903 struct mtk_dsi *dsi = host_to_dsi(host); 904 struct device *dev = host->dev; 905 int ret; 906 907 dsi->lanes = device->lanes; 908 dsi->format = device->format; 909 dsi->mode_flags = device->mode_flags; 910 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0); 911 if (IS_ERR(dsi->next_bridge)) 912 return PTR_ERR(dsi->next_bridge); 913 914 drm_bridge_add(&dsi->bridge); 915 916 ret = component_add(host->dev, &mtk_dsi_component_ops); 917 if (ret) { 918 DRM_ERROR("failed to add dsi_host component: %d\n", ret); 919 drm_bridge_remove(&dsi->bridge); 920 return ret; 921 } 922 923 return 0; 924 } 925 926 static int mtk_dsi_host_detach(struct mipi_dsi_host *host, 927 struct mipi_dsi_device *device) 928 { 929 struct mtk_dsi *dsi = host_to_dsi(host); 930 931 component_del(host->dev, &mtk_dsi_component_ops); 932 drm_bridge_remove(&dsi->bridge); 933 return 0; 934 } 935 936 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi) 937 { 938 int ret; 939 u32 val; 940 941 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY), 942 4, 2000000); 943 if (ret) { 944 DRM_WARN("polling dsi wait not busy timeout!\n"); 945 946 mtk_dsi_enable(dsi); 947 mtk_dsi_reset_engine(dsi); 948 } 949 } 950 951 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data) 952 { 953 switch (type) { 954 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 955 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 956 return 1; 957 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 958 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 959 return 2; 960 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 961 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 962 return read_data[1] + read_data[2] * 16; 963 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 964 DRM_INFO("type is 0x02, try again\n"); 965 break; 966 default: 967 DRM_INFO("type(0x%x) not recognized\n", type); 968 break; 969 } 970 971 return 0; 972 } 973 974 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg) 975 { 976 const char *tx_buf = msg->tx_buf; 977 u8 config, cmdq_size, cmdq_off, type = msg->type; 978 u32 reg_val, cmdq_mask, i; 979 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off; 980 981 if (MTK_DSI_HOST_IS_READ(type)) 982 config = BTA; 983 else 984 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; 985 986 if (msg->tx_len > 2) { 987 cmdq_size = 1 + (msg->tx_len + 3) / 4; 988 cmdq_off = 4; 989 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; 990 reg_val = (msg->tx_len << 16) | (type << 8) | config; 991 } else { 992 cmdq_size = 1; 993 cmdq_off = 2; 994 cmdq_mask = CONFIG | DATA_ID; 995 reg_val = (type << 8) | config; 996 } 997 998 for (i = 0; i < msg->tx_len; i++) 999 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U), 1000 (0xffUL << (((i + cmdq_off) & 3U) * 8U)), 1001 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U)); 1002 1003 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); 1004 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); 1005 if (dsi->driver_data->cmdq_long_packet_ctl) { 1006 /* Disable setting cmdq_size automatically for long packets */ 1007 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL); 1008 } 1009 } 1010 1011 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, 1012 const struct mipi_dsi_msg *msg, u8 flag) 1013 { 1014 mtk_dsi_wait_for_idle(dsi); 1015 mtk_dsi_irq_data_clear(dsi, flag); 1016 mtk_dsi_cmdq(dsi, msg); 1017 mtk_dsi_start(dsi); 1018 1019 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000)) 1020 return -ETIME; 1021 else 1022 return 0; 1023 } 1024 1025 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, 1026 const struct mipi_dsi_msg *msg) 1027 { 1028 struct mtk_dsi *dsi = host_to_dsi(host); 1029 u32 recv_cnt, i; 1030 u8 read_data[16]; 1031 void *src_addr; 1032 u8 irq_flag = CMD_DONE_INT_FLAG; 1033 u32 dsi_mode; 1034 int ret; 1035 1036 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL); 1037 if (dsi_mode & MODE) { 1038 mtk_dsi_stop(dsi); 1039 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); 1040 if (ret) 1041 goto restore_dsi_mode; 1042 } 1043 1044 if (MTK_DSI_HOST_IS_READ(msg->type)) 1045 irq_flag |= LPRX_RD_RDY_INT_FLAG; 1046 1047 mtk_dsi_lane_ready(dsi); 1048 1049 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag); 1050 if (ret) 1051 goto restore_dsi_mode; 1052 1053 if (!MTK_DSI_HOST_IS_READ(msg->type)) { 1054 recv_cnt = 0; 1055 goto restore_dsi_mode; 1056 } 1057 1058 if (!msg->rx_buf) { 1059 DRM_ERROR("dsi receive buffer size may be NULL\n"); 1060 ret = -EINVAL; 1061 goto restore_dsi_mode; 1062 } 1063 1064 for (i = 0; i < 16; i++) 1065 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i); 1066 1067 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data); 1068 1069 if (recv_cnt > 2) 1070 src_addr = &read_data[4]; 1071 else 1072 src_addr = &read_data[1]; 1073 1074 if (recv_cnt > 10) 1075 recv_cnt = 10; 1076 1077 if (recv_cnt > msg->rx_len) 1078 recv_cnt = msg->rx_len; 1079 1080 if (recv_cnt) 1081 memcpy(msg->rx_buf, src_addr, recv_cnt); 1082 1083 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", 1084 recv_cnt, *((u8 *)(msg->tx_buf))); 1085 1086 restore_dsi_mode: 1087 if (dsi_mode & MODE) { 1088 mtk_dsi_set_mode(dsi); 1089 mtk_dsi_start(dsi); 1090 } 1091 1092 return ret < 0 ? ret : recv_cnt; 1093 } 1094 1095 static const struct mipi_dsi_host_ops mtk_dsi_ops = { 1096 .attach = mtk_dsi_host_attach, 1097 .detach = mtk_dsi_host_detach, 1098 .transfer = mtk_dsi_host_transfer, 1099 }; 1100 1101 static int mtk_dsi_probe(struct platform_device *pdev) 1102 { 1103 struct mtk_dsi *dsi; 1104 struct device *dev = &pdev->dev; 1105 struct resource *regs; 1106 int irq_num; 1107 int ret; 1108 1109 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1110 if (!dsi) 1111 return -ENOMEM; 1112 1113 dsi->driver_data = of_device_get_match_data(dev); 1114 1115 dsi->engine_clk = devm_clk_get(dev, "engine"); 1116 if (IS_ERR(dsi->engine_clk)) 1117 return dev_err_probe(dev, PTR_ERR(dsi->engine_clk), 1118 "Failed to get engine clock\n"); 1119 1120 1121 dsi->digital_clk = devm_clk_get(dev, "digital"); 1122 if (IS_ERR(dsi->digital_clk)) 1123 return dev_err_probe(dev, PTR_ERR(dsi->digital_clk), 1124 "Failed to get digital clock\n"); 1125 1126 dsi->hs_clk = devm_clk_get(dev, "hs"); 1127 if (IS_ERR(dsi->hs_clk)) 1128 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n"); 1129 1130 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1131 dsi->regs = devm_ioremap_resource(dev, regs); 1132 if (IS_ERR(dsi->regs)) 1133 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n"); 1134 1135 dsi->phy = devm_phy_get(dev, "dphy"); 1136 if (IS_ERR(dsi->phy)) 1137 return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n"); 1138 1139 irq_num = platform_get_irq(pdev, 0); 1140 if (irq_num < 0) 1141 return irq_num; 1142 1143 dsi->host.ops = &mtk_dsi_ops; 1144 dsi->host.dev = dev; 1145 ret = mipi_dsi_host_register(&dsi->host); 1146 if (ret < 0) 1147 return dev_err_probe(dev, ret, "Failed to register DSI host\n"); 1148 1149 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, 1150 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi); 1151 if (ret) { 1152 mipi_dsi_host_unregister(&dsi->host); 1153 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n"); 1154 } 1155 1156 init_waitqueue_head(&dsi->irq_wait_queue); 1157 1158 platform_set_drvdata(pdev, dsi); 1159 1160 dsi->bridge.funcs = &mtk_dsi_bridge_funcs; 1161 dsi->bridge.of_node = dev->of_node; 1162 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1163 1164 return 0; 1165 } 1166 1167 static void mtk_dsi_remove(struct platform_device *pdev) 1168 { 1169 struct mtk_dsi *dsi = platform_get_drvdata(pdev); 1170 1171 mtk_output_dsi_disable(dsi); 1172 mipi_dsi_host_unregister(&dsi->host); 1173 } 1174 1175 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { 1176 .reg_cmdq_off = 0x200, 1177 }; 1178 1179 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = { 1180 .reg_cmdq_off = 0x180, 1181 }; 1182 1183 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = { 1184 .reg_cmdq_off = 0x200, 1185 .has_shadow_ctl = true, 1186 .has_size_ctl = true, 1187 }; 1188 1189 static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = { 1190 .reg_cmdq_off = 0xd00, 1191 .has_shadow_ctl = true, 1192 .has_size_ctl = true, 1193 }; 1194 1195 static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { 1196 .reg_cmdq_off = 0xd00, 1197 .has_shadow_ctl = true, 1198 .has_size_ctl = true, 1199 .cmdq_long_packet_ctl = true, 1200 }; 1201 1202 static const struct of_device_id mtk_dsi_of_match[] = { 1203 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data }, 1204 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data }, 1205 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data }, 1206 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data }, 1207 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data }, 1208 { /* sentinel */ } 1209 }; 1210 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match); 1211 1212 struct platform_driver mtk_dsi_driver = { 1213 .probe = mtk_dsi_probe, 1214 .remove_new = mtk_dsi_remove, 1215 .driver = { 1216 .name = "mtk-dsi", 1217 .of_match_table = mtk_dsi_of_match, 1218 }, 1219 }; 1220