1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/clients/drm_client_setup.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_dma_helper.h> 23 #include <drm/drm_gem_framebuffer_helper.h> 24 #include <drm/drm_ioctl.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "mtk_crtc.h" 30 #include "mtk_ddp_comp.h" 31 #include "mtk_disp_drv.h" 32 #include "mtk_drm_drv.h" 33 34 #define DRIVER_NAME "mediatek" 35 #define DRIVER_DESC "Mediatek SoC DRM" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_format_info *info, 47 const struct drm_mode_fb_cmd2 *cmd) 48 { 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, info, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const unsigned int mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const unsigned int mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const unsigned int mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const unsigned int mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const unsigned int mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const unsigned int mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const unsigned int mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static unsigned int mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER0, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const unsigned int mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const unsigned int mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const unsigned int mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER0, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const unsigned int mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const unsigned int mt8186_mtk_ddp_main[] = { 162 DDP_COMPONENT_OVL0, 163 DDP_COMPONENT_RDMA0, 164 DDP_COMPONENT_COLOR0, 165 DDP_COMPONENT_CCORR, 166 DDP_COMPONENT_AAL0, 167 DDP_COMPONENT_GAMMA, 168 DDP_COMPONENT_POSTMASK0, 169 DDP_COMPONENT_DITHER0, 170 DDP_COMPONENT_DSI0, 171 }; 172 173 static const unsigned int mt8186_mtk_ddp_ext[] = { 174 DDP_COMPONENT_OVL_2L0, 175 DDP_COMPONENT_RDMA1, 176 DDP_COMPONENT_DPI0, 177 }; 178 179 static const unsigned int mt8188_mtk_ddp_main[] = { 180 DDP_COMPONENT_OVL0, 181 DDP_COMPONENT_RDMA0, 182 DDP_COMPONENT_COLOR0, 183 DDP_COMPONENT_CCORR, 184 DDP_COMPONENT_AAL0, 185 DDP_COMPONENT_GAMMA, 186 DDP_COMPONENT_POSTMASK0, 187 DDP_COMPONENT_DITHER0, 188 }; 189 190 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 191 {0, DDP_COMPONENT_DP_INTF0}, 192 {0, DDP_COMPONENT_DSI0}, 193 }; 194 195 static const unsigned int mt8192_mtk_ddp_main[] = { 196 DDP_COMPONENT_OVL0, 197 DDP_COMPONENT_OVL_2L0, 198 DDP_COMPONENT_RDMA0, 199 DDP_COMPONENT_COLOR0, 200 DDP_COMPONENT_CCORR, 201 DDP_COMPONENT_AAL0, 202 DDP_COMPONENT_GAMMA, 203 DDP_COMPONENT_POSTMASK0, 204 DDP_COMPONENT_DITHER0, 205 DDP_COMPONENT_DSI0, 206 }; 207 208 static const unsigned int mt8192_mtk_ddp_ext[] = { 209 DDP_COMPONENT_OVL_2L2, 210 DDP_COMPONENT_RDMA4, 211 DDP_COMPONENT_DPI0, 212 }; 213 214 static const unsigned int mt8195_mtk_ddp_main[] = { 215 DDP_COMPONENT_OVL0, 216 DDP_COMPONENT_RDMA0, 217 DDP_COMPONENT_COLOR0, 218 DDP_COMPONENT_CCORR, 219 DDP_COMPONENT_AAL0, 220 DDP_COMPONENT_GAMMA, 221 DDP_COMPONENT_DITHER0, 222 DDP_COMPONENT_DSC0, 223 DDP_COMPONENT_MERGE0, 224 DDP_COMPONENT_DP_INTF0, 225 }; 226 227 static const unsigned int mt8195_mtk_ddp_ext[] = { 228 DDP_COMPONENT_DRM_OVL_ADAPTOR, 229 DDP_COMPONENT_MERGE5, 230 DDP_COMPONENT_DP_INTF1, 231 }; 232 233 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 234 .main_path = mt2701_mtk_ddp_main, 235 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 236 .ext_path = mt2701_mtk_ddp_ext, 237 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 238 .shadow_register = true, 239 .mmsys_dev_num = 1, 240 }; 241 242 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 243 .main_path = mt7623_mtk_ddp_main, 244 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 245 .ext_path = mt7623_mtk_ddp_ext, 246 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 247 .shadow_register = true, 248 .mmsys_dev_num = 1, 249 }; 250 251 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 252 .main_path = mt2712_mtk_ddp_main, 253 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 254 .ext_path = mt2712_mtk_ddp_ext, 255 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 256 .third_path = mt2712_mtk_ddp_third, 257 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 258 .mmsys_dev_num = 1, 259 }; 260 261 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 262 .main_path = mt8167_mtk_ddp_main, 263 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 264 .mmsys_dev_num = 1, 265 }; 266 267 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 268 .main_path = mt8173_mtk_ddp_main, 269 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 270 .ext_path = mt8173_mtk_ddp_ext, 271 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 272 .mmsys_dev_num = 1, 273 }; 274 275 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 276 .main_path = mt8183_mtk_ddp_main, 277 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 278 .ext_path = mt8183_mtk_ddp_ext, 279 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 280 .mmsys_dev_num = 1, 281 }; 282 283 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 284 .main_path = mt8186_mtk_ddp_main, 285 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 286 .ext_path = mt8186_mtk_ddp_ext, 287 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 288 .mmsys_dev_num = 1, 289 }; 290 291 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 292 .main_path = mt8188_mtk_ddp_main, 293 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 294 .conn_routes = mt8188_mtk_ddp_main_routes, 295 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 296 .mmsys_dev_num = 2, 297 .max_width = 8191, 298 .min_width = 1, 299 .min_height = 1, 300 }; 301 302 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 303 .main_path = mt8192_mtk_ddp_main, 304 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 305 .ext_path = mt8192_mtk_ddp_ext, 306 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 307 .mmsys_dev_num = 1, 308 }; 309 310 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 311 .main_path = mt8195_mtk_ddp_main, 312 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 313 .mmsys_dev_num = 2, 314 .max_width = 8191, 315 .min_width = 1, 316 .min_height = 1, 317 }; 318 319 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 320 .ext_path = mt8195_mtk_ddp_ext, 321 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 322 .mmsys_id = 1, 323 .mmsys_dev_num = 2, 324 .max_width = 8191, 325 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 326 .min_height = 1, 327 }; 328 329 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 330 .mmsys_dev_num = 1, 331 }; 332 333 static const struct of_device_id mtk_drm_of_ids[] = { 334 { .compatible = "mediatek,mt2701-mmsys", 335 .data = &mt2701_mmsys_driver_data}, 336 { .compatible = "mediatek,mt7623-mmsys", 337 .data = &mt7623_mmsys_driver_data}, 338 { .compatible = "mediatek,mt2712-mmsys", 339 .data = &mt2712_mmsys_driver_data}, 340 { .compatible = "mediatek,mt8167-mmsys", 341 .data = &mt8167_mmsys_driver_data}, 342 { .compatible = "mediatek,mt8173-mmsys", 343 .data = &mt8173_mmsys_driver_data}, 344 { .compatible = "mediatek,mt8183-mmsys", 345 .data = &mt8183_mmsys_driver_data}, 346 { .compatible = "mediatek,mt8186-mmsys", 347 .data = &mt8186_mmsys_driver_data}, 348 { .compatible = "mediatek,mt8188-vdosys0", 349 .data = &mt8188_vdosys0_driver_data}, 350 { .compatible = "mediatek,mt8188-vdosys1", 351 .data = &mt8195_vdosys1_driver_data}, 352 { .compatible = "mediatek,mt8192-mmsys", 353 .data = &mt8192_mmsys_driver_data}, 354 { .compatible = "mediatek,mt8195-mmsys", 355 .data = &mt8195_vdosys0_driver_data}, 356 { .compatible = "mediatek,mt8195-vdosys0", 357 .data = &mt8195_vdosys0_driver_data}, 358 { .compatible = "mediatek,mt8195-vdosys1", 359 .data = &mt8195_vdosys1_driver_data}, 360 { .compatible = "mediatek,mt8365-mmsys", 361 .data = &mt8365_mmsys_driver_data}, 362 { } 363 }; 364 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 365 366 static int mtk_drm_match(struct device *dev, const void *data) 367 { 368 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 369 return true; 370 return false; 371 } 372 373 static bool mtk_drm_get_all_drm_priv(struct device *dev) 374 { 375 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 376 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 377 struct mtk_drm_private *temp_drm_priv; 378 struct device_node *phandle = dev->parent->of_node; 379 const struct of_device_id *of_id; 380 struct device_node *node; 381 struct device *drm_dev; 382 unsigned int cnt = 0; 383 int i, j; 384 385 for_each_child_of_node(phandle->parent, node) { 386 struct platform_device *pdev; 387 388 of_id = of_match_node(mtk_drm_of_ids, node); 389 if (!of_id) 390 continue; 391 392 pdev = of_find_device_by_node(node); 393 if (!pdev) 394 continue; 395 396 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 397 put_device(&pdev->dev); 398 if (!drm_dev) 399 continue; 400 401 temp_drm_priv = dev_get_drvdata(drm_dev); 402 put_device(drm_dev); 403 if (!temp_drm_priv) 404 continue; 405 406 if (temp_drm_priv->data->main_len) 407 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 408 else if (temp_drm_priv->data->ext_len) 409 all_drm_priv[CRTC_EXT] = temp_drm_priv; 410 else if (temp_drm_priv->data->third_len) 411 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 412 413 if (temp_drm_priv->mtk_drm_bound) 414 cnt++; 415 416 if (cnt == MAX_CRTC) { 417 of_node_put(node); 418 break; 419 } 420 } 421 422 if (drm_priv->data->mmsys_dev_num == cnt) { 423 for (i = 0; i < cnt; i++) 424 for (j = 0; j < cnt; j++) 425 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 426 427 return true; 428 } 429 430 return false; 431 } 432 433 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 434 { 435 const struct mtk_mmsys_driver_data *drv_data = private->data; 436 int i; 437 438 if (drv_data->main_path) 439 for (i = 0; i < drv_data->main_len; i++) 440 if (drv_data->main_path[i] == comp_id) 441 return true; 442 443 if (drv_data->ext_path) 444 for (i = 0; i < drv_data->ext_len; i++) 445 if (drv_data->ext_path[i] == comp_id) 446 return true; 447 448 if (drv_data->third_path) 449 for (i = 0; i < drv_data->third_len; i++) 450 if (drv_data->third_path[i] == comp_id) 451 return true; 452 453 if (drv_data->num_conn_routes) 454 for (i = 0; i < drv_data->num_conn_routes; i++) 455 if (drv_data->conn_routes[i].route_ddp == comp_id) 456 return true; 457 458 return false; 459 } 460 461 static int mtk_drm_kms_init(struct drm_device *drm) 462 { 463 struct mtk_drm_private *private = drm->dev_private; 464 struct mtk_drm_private *priv_n; 465 struct device *dma_dev = NULL; 466 struct drm_crtc *crtc; 467 int ret, i, j; 468 469 if (drm_firmware_drivers_only()) 470 return -ENODEV; 471 472 ret = drmm_mode_config_init(drm); 473 if (ret) 474 return ret; 475 476 drm->mode_config.min_width = 64; 477 drm->mode_config.min_height = 64; 478 479 /* 480 * set max width and height as default value(4096x4096). 481 * this value would be used to check framebuffer size limitation 482 * at drm_mode_addfb(). 483 */ 484 drm->mode_config.max_width = 4096; 485 drm->mode_config.max_height = 4096; 486 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 487 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 488 489 for (i = 0; i < private->data->mmsys_dev_num; i++) { 490 drm->dev_private = private->all_drm_private[i]; 491 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 492 if (ret) { 493 while (--i >= 0) 494 component_unbind_all(private->all_drm_private[i]->dev, drm); 495 return ret; 496 } 497 } 498 499 /* 500 * Ensure internal panels are at the top of the connector list before 501 * crtc creation. 502 */ 503 drm_helper_move_panel_connectors_to_head(drm); 504 505 /* 506 * 1. We currently support two fixed data streams, each optional, 507 * and each statically assigned to a crtc: 508 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 509 * 2. For multi mmsys architecture, crtc path data are located in 510 * different drm private data structures. Loop through crtc index to 511 * create crtc from the main path and then ext_path and finally the 512 * third path. 513 */ 514 for (i = 0; i < MAX_CRTC; i++) { 515 for (j = 0; j < private->data->mmsys_dev_num; j++) { 516 priv_n = private->all_drm_private[j]; 517 518 if (priv_n->data->max_width) 519 drm->mode_config.max_width = priv_n->data->max_width; 520 521 if (priv_n->data->min_width) 522 drm->mode_config.min_width = priv_n->data->min_width; 523 524 if (priv_n->data->min_height) 525 drm->mode_config.min_height = priv_n->data->min_height; 526 527 if (i == CRTC_MAIN && priv_n->data->main_len) { 528 ret = mtk_crtc_create(drm, priv_n->data->main_path, 529 priv_n->data->main_len, j, 530 priv_n->data->conn_routes, 531 priv_n->data->num_conn_routes); 532 if (ret) 533 goto err_component_unbind; 534 535 continue; 536 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 537 ret = mtk_crtc_create(drm, priv_n->data->ext_path, 538 priv_n->data->ext_len, j, NULL, 0); 539 if (ret) 540 goto err_component_unbind; 541 542 continue; 543 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 544 ret = mtk_crtc_create(drm, priv_n->data->third_path, 545 priv_n->data->third_len, j, NULL, 0); 546 if (ret) 547 goto err_component_unbind; 548 549 continue; 550 } 551 } 552 } 553 554 /* IGT will check if the cursor size is configured */ 555 drm->mode_config.cursor_width = 512; 556 drm->mode_config.cursor_height = 512; 557 558 /* Use OVL device for all DMA memory allocations */ 559 crtc = drm_crtc_from_index(drm, 0); 560 if (crtc) 561 dma_dev = mtk_crtc_dma_dev_get(crtc); 562 if (!dma_dev) { 563 ret = -ENODEV; 564 dev_err(drm->dev, "Need at least one OVL device\n"); 565 goto err_component_unbind; 566 } 567 568 drm_dev_set_dma_dev(drm, dma_dev); 569 570 /* 571 * Configure the DMA segment size to make sure we get contiguous IOVA 572 * when importing PRIME buffers. 573 */ 574 dma_set_max_seg_size(dma_dev, UINT_MAX); 575 576 ret = drm_vblank_init(drm, MAX_CRTC); 577 if (ret < 0) 578 goto err_component_unbind; 579 580 drm_kms_helper_poll_init(drm); 581 drm_mode_config_reset(drm); 582 583 return 0; 584 585 err_component_unbind: 586 for (i = 0; i < private->data->mmsys_dev_num; i++) 587 component_unbind_all(private->all_drm_private[i]->dev, drm); 588 589 return ret; 590 } 591 592 static void mtk_drm_kms_deinit(struct drm_device *drm) 593 { 594 drm_kms_helper_poll_fini(drm); 595 drm_atomic_helper_shutdown(drm); 596 597 component_unbind_all(drm->dev, drm); 598 } 599 600 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 601 602 static const struct drm_driver mtk_drm_driver = { 603 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 604 605 DRM_GEM_DMA_DRIVER_OPS, 606 DRM_FBDEV_DMA_DRIVER_OPS, 607 608 .fops = &mtk_drm_fops, 609 610 .name = DRIVER_NAME, 611 .desc = DRIVER_DESC, 612 .major = DRIVER_MAJOR, 613 .minor = DRIVER_MINOR, 614 }; 615 616 static int compare_dev(struct device *dev, void *data) 617 { 618 return dev == (struct device *)data; 619 } 620 621 static int mtk_drm_bind(struct device *dev) 622 { 623 struct mtk_drm_private *private = dev_get_drvdata(dev); 624 struct platform_device *pdev; 625 struct drm_device *drm; 626 int ret, i; 627 628 pdev = of_find_device_by_node(private->mutex_node); 629 if (!pdev) { 630 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 631 private->mutex_node); 632 of_node_put(private->mutex_node); 633 return -EPROBE_DEFER; 634 } 635 636 private->mutex_dev = &pdev->dev; 637 private->mtk_drm_bound = true; 638 private->dev = dev; 639 640 if (!mtk_drm_get_all_drm_priv(dev)) 641 return 0; 642 643 drm = drm_dev_alloc(&mtk_drm_driver, dev); 644 if (IS_ERR(drm)) { 645 ret = PTR_ERR(drm); 646 goto err_put_dev; 647 } 648 649 private->drm_master = true; 650 drm->dev_private = private; 651 for (i = 0; i < private->data->mmsys_dev_num; i++) 652 private->all_drm_private[i]->drm = drm; 653 654 ret = mtk_drm_kms_init(drm); 655 if (ret < 0) 656 goto err_free; 657 658 ret = drm_dev_register(drm, 0); 659 if (ret < 0) 660 goto err_deinit; 661 662 drm_client_setup(drm, NULL); 663 664 return 0; 665 666 err_deinit: 667 mtk_drm_kms_deinit(drm); 668 err_free: 669 private->drm = NULL; 670 drm_dev_put(drm); 671 for (i = 0; i < private->data->mmsys_dev_num; i++) 672 private->all_drm_private[i]->drm = NULL; 673 err_put_dev: 674 put_device(private->mutex_dev); 675 return ret; 676 } 677 678 static void mtk_drm_unbind(struct device *dev) 679 { 680 struct mtk_drm_private *private = dev_get_drvdata(dev); 681 682 /* for multi mmsys dev, unregister drm dev in mmsys master */ 683 if (private->drm_master) { 684 drm_dev_unregister(private->drm); 685 mtk_drm_kms_deinit(private->drm); 686 drm_dev_put(private->drm); 687 put_device(private->mutex_dev); 688 } 689 private->mtk_drm_bound = false; 690 private->drm_master = false; 691 private->drm = NULL; 692 } 693 694 static const struct component_master_ops mtk_drm_ops = { 695 .bind = mtk_drm_bind, 696 .unbind = mtk_drm_unbind, 697 }; 698 699 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 700 { .compatible = "mediatek,mt8167-disp-aal", 701 .data = (void *)MTK_DISP_AAL}, 702 { .compatible = "mediatek,mt8173-disp-aal", 703 .data = (void *)MTK_DISP_AAL}, 704 { .compatible = "mediatek,mt8183-disp-aal", 705 .data = (void *)MTK_DISP_AAL}, 706 { .compatible = "mediatek,mt8192-disp-aal", 707 .data = (void *)MTK_DISP_AAL}, 708 { .compatible = "mediatek,mt8167-disp-ccorr", 709 .data = (void *)MTK_DISP_CCORR }, 710 { .compatible = "mediatek,mt8183-disp-ccorr", 711 .data = (void *)MTK_DISP_CCORR }, 712 { .compatible = "mediatek,mt8192-disp-ccorr", 713 .data = (void *)MTK_DISP_CCORR }, 714 { .compatible = "mediatek,mt2701-disp-color", 715 .data = (void *)MTK_DISP_COLOR }, 716 { .compatible = "mediatek,mt8167-disp-color", 717 .data = (void *)MTK_DISP_COLOR }, 718 { .compatible = "mediatek,mt8173-disp-color", 719 .data = (void *)MTK_DISP_COLOR }, 720 { .compatible = "mediatek,mt8167-disp-dither", 721 .data = (void *)MTK_DISP_DITHER }, 722 { .compatible = "mediatek,mt8183-disp-dither", 723 .data = (void *)MTK_DISP_DITHER }, 724 { .compatible = "mediatek,mt8195-disp-dsc", 725 .data = (void *)MTK_DISP_DSC }, 726 { .compatible = "mediatek,mt8167-disp-gamma", 727 .data = (void *)MTK_DISP_GAMMA, }, 728 { .compatible = "mediatek,mt8173-disp-gamma", 729 .data = (void *)MTK_DISP_GAMMA, }, 730 { .compatible = "mediatek,mt8183-disp-gamma", 731 .data = (void *)MTK_DISP_GAMMA, }, 732 { .compatible = "mediatek,mt8195-disp-gamma", 733 .data = (void *)MTK_DISP_GAMMA, }, 734 { .compatible = "mediatek,mt8195-disp-merge", 735 .data = (void *)MTK_DISP_MERGE }, 736 { .compatible = "mediatek,mt2701-disp-mutex", 737 .data = (void *)MTK_DISP_MUTEX }, 738 { .compatible = "mediatek,mt2712-disp-mutex", 739 .data = (void *)MTK_DISP_MUTEX }, 740 { .compatible = "mediatek,mt8167-disp-mutex", 741 .data = (void *)MTK_DISP_MUTEX }, 742 { .compatible = "mediatek,mt8173-disp-mutex", 743 .data = (void *)MTK_DISP_MUTEX }, 744 { .compatible = "mediatek,mt8183-disp-mutex", 745 .data = (void *)MTK_DISP_MUTEX }, 746 { .compatible = "mediatek,mt8186-disp-mutex", 747 .data = (void *)MTK_DISP_MUTEX }, 748 { .compatible = "mediatek,mt8188-disp-mutex", 749 .data = (void *)MTK_DISP_MUTEX }, 750 { .compatible = "mediatek,mt8192-disp-mutex", 751 .data = (void *)MTK_DISP_MUTEX }, 752 { .compatible = "mediatek,mt8195-disp-mutex", 753 .data = (void *)MTK_DISP_MUTEX }, 754 { .compatible = "mediatek,mt8365-disp-mutex", 755 .data = (void *)MTK_DISP_MUTEX }, 756 { .compatible = "mediatek,mt8173-disp-od", 757 .data = (void *)MTK_DISP_OD }, 758 { .compatible = "mediatek,mt2701-disp-ovl", 759 .data = (void *)MTK_DISP_OVL }, 760 { .compatible = "mediatek,mt8167-disp-ovl", 761 .data = (void *)MTK_DISP_OVL }, 762 { .compatible = "mediatek,mt8173-disp-ovl", 763 .data = (void *)MTK_DISP_OVL }, 764 { .compatible = "mediatek,mt8183-disp-ovl", 765 .data = (void *)MTK_DISP_OVL }, 766 { .compatible = "mediatek,mt8192-disp-ovl", 767 .data = (void *)MTK_DISP_OVL }, 768 { .compatible = "mediatek,mt8195-disp-ovl", 769 .data = (void *)MTK_DISP_OVL }, 770 { .compatible = "mediatek,mt8183-disp-ovl-2l", 771 .data = (void *)MTK_DISP_OVL_2L }, 772 { .compatible = "mediatek,mt8192-disp-ovl-2l", 773 .data = (void *)MTK_DISP_OVL_2L }, 774 { .compatible = "mediatek,mt8192-disp-postmask", 775 .data = (void *)MTK_DISP_POSTMASK }, 776 { .compatible = "mediatek,mt2701-disp-pwm", 777 .data = (void *)MTK_DISP_BLS }, 778 { .compatible = "mediatek,mt8167-disp-pwm", 779 .data = (void *)MTK_DISP_PWM }, 780 { .compatible = "mediatek,mt8173-disp-pwm", 781 .data = (void *)MTK_DISP_PWM }, 782 { .compatible = "mediatek,mt2701-disp-rdma", 783 .data = (void *)MTK_DISP_RDMA }, 784 { .compatible = "mediatek,mt8167-disp-rdma", 785 .data = (void *)MTK_DISP_RDMA }, 786 { .compatible = "mediatek,mt8173-disp-rdma", 787 .data = (void *)MTK_DISP_RDMA }, 788 { .compatible = "mediatek,mt8183-disp-rdma", 789 .data = (void *)MTK_DISP_RDMA }, 790 { .compatible = "mediatek,mt8195-disp-rdma", 791 .data = (void *)MTK_DISP_RDMA }, 792 { .compatible = "mediatek,mt8173-disp-ufoe", 793 .data = (void *)MTK_DISP_UFOE }, 794 { .compatible = "mediatek,mt8173-disp-wdma", 795 .data = (void *)MTK_DISP_WDMA }, 796 { .compatible = "mediatek,mt2701-dpi", 797 .data = (void *)MTK_DPI }, 798 { .compatible = "mediatek,mt8167-dsi", 799 .data = (void *)MTK_DSI }, 800 { .compatible = "mediatek,mt8173-dpi", 801 .data = (void *)MTK_DPI }, 802 { .compatible = "mediatek,mt8183-dpi", 803 .data = (void *)MTK_DPI }, 804 { .compatible = "mediatek,mt8186-dpi", 805 .data = (void *)MTK_DPI }, 806 { .compatible = "mediatek,mt8188-dp-intf", 807 .data = (void *)MTK_DP_INTF }, 808 { .compatible = "mediatek,mt8192-dpi", 809 .data = (void *)MTK_DPI }, 810 { .compatible = "mediatek,mt8195-dp-intf", 811 .data = (void *)MTK_DP_INTF }, 812 { .compatible = "mediatek,mt8195-dpi", 813 .data = (void *)MTK_DPI }, 814 { .compatible = "mediatek,mt2701-dsi", 815 .data = (void *)MTK_DSI }, 816 { .compatible = "mediatek,mt8173-dsi", 817 .data = (void *)MTK_DSI }, 818 { .compatible = "mediatek,mt8183-dsi", 819 .data = (void *)MTK_DSI }, 820 { .compatible = "mediatek,mt8186-dsi", 821 .data = (void *)MTK_DSI }, 822 { .compatible = "mediatek,mt8188-dsi", 823 .data = (void *)MTK_DSI }, 824 { } 825 }; 826 827 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype) 828 { 829 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 830 831 if (!of_id) 832 return -EINVAL; 833 834 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data); 835 836 return 0; 837 } 838 839 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, 840 int output_port, enum mtk_crtc_path crtc_path, 841 struct device_node **next, unsigned int *cid) 842 { 843 struct device_node *ep_dev_node, *ep_out; 844 enum mtk_ddp_comp_type comp_type; 845 int ret; 846 847 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path); 848 if (!ep_out) 849 return -ENOENT; 850 851 ep_dev_node = of_graph_get_remote_port_parent(ep_out); 852 of_node_put(ep_out); 853 if (!ep_dev_node) 854 return -EINVAL; 855 856 /* 857 * Pass the next node pointer regardless of failures in the later code 858 * so that if this function is called in a loop it will walk through all 859 * of the subsequent endpoints anyway. 860 */ 861 *next = ep_dev_node; 862 863 if (!of_device_is_available(ep_dev_node)) 864 return -ENODEV; 865 866 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); 867 if (ret) { 868 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { 869 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR; 870 return 0; 871 } 872 return ret; 873 } 874 875 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type); 876 if (ret < 0) 877 return ret; 878 879 /* All ok! Pass the Component ID to the caller. */ 880 *cid = (unsigned int)ret; 881 882 return 0; 883 } 884 885 /** 886 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path 887 * @dev: The mediatek-drm device 888 * @cpath: CRTC Path relative to a VDO or MMSYS 889 * @out_path: Pointer to an array that will contain the new pipeline 890 * @out_path_len: Number of entries in the pipeline array 891 * 892 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending 893 * on the board-specific desired display configuration; this function walks 894 * through all of the output endpoints starting from a VDO or MMSYS hardware 895 * instance and builds the right pipeline as specified in device trees. 896 * 897 * Return: 898 * * %0 - Display HW Pipeline successfully built and validated 899 * * %-ENOENT - Display pipeline was not specified in device tree 900 * * %-EINVAL - Display pipeline built but validation failed 901 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller 902 */ 903 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath, 904 const unsigned int **out_path, 905 unsigned int *out_path_len) 906 { 907 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node; 908 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 }; 909 unsigned int *final_ddp_path; 910 unsigned short int idx = 0; 911 bool ovl_adaptor_comp_added = false; 912 int ret; 913 914 /* Get the first entry for the temp_path array */ 915 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); 916 if (ret) { 917 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 918 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); 919 ovl_adaptor_comp_added = true; 920 } else { 921 if (next) 922 dev_err(dev, "Invalid component %pOF\n", next); 923 else 924 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath); 925 926 return ret; 927 } 928 } 929 idx++; 930 931 /* 932 * Walk through port outputs until we reach the last valid mediatek-drm component. 933 * To be valid, this must end with an "invalid" component that is a display node. 934 */ 935 do { 936 prev = next; 937 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]); 938 of_node_put(prev); 939 if (ret) { 940 of_node_put(next); 941 break; 942 } 943 944 /* 945 * If this is an OVL adaptor exclusive component and one of those 946 * was already added, don't add another instance of the generic 947 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether 948 * to probe that component master driver of which only one instance 949 * is needed and possible. 950 */ 951 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 952 if (!ovl_adaptor_comp_added) 953 ovl_adaptor_comp_added = true; 954 else 955 idx--; 956 } 957 } while (++idx < DDP_COMPONENT_DRM_ID_MAX); 958 959 /* 960 * The device component might not be enabled: in that case, don't 961 * check the last entry and just report that the device is missing. 962 */ 963 if (ret == -ENODEV) 964 return ret; 965 966 /* If the last entry is not a final display output, the configuration is wrong */ 967 switch (temp_path[idx - 1]) { 968 case DDP_COMPONENT_DP_INTF0: 969 case DDP_COMPONENT_DP_INTF1: 970 case DDP_COMPONENT_DPI0: 971 case DDP_COMPONENT_DPI1: 972 case DDP_COMPONENT_DSI0: 973 case DDP_COMPONENT_DSI1: 974 case DDP_COMPONENT_DSI2: 975 case DDP_COMPONENT_DSI3: 976 break; 977 default: 978 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n", 979 temp_path[idx - 1], ret); 980 return -EINVAL; 981 } 982 983 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL); 984 if (!final_ddp_path) 985 return -ENOMEM; 986 987 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx); 988 989 /* Pipeline built! */ 990 *out_path = final_ddp_path; 991 *out_path_len = idx; 992 993 return 0; 994 } 995 996 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node, 997 struct mtk_mmsys_driver_data *data) 998 { 999 struct device_node *ep_node; 1000 struct of_endpoint of_ep; 1001 bool output_present[MAX_CRTC] = { false }; 1002 int ret; 1003 1004 for_each_endpoint_of_node(node, ep_node) { 1005 ret = of_graph_parse_endpoint(ep_node, &of_ep); 1006 if (ret) { 1007 dev_err_probe(dev, ret, "Cannot parse endpoint\n"); 1008 break; 1009 } 1010 1011 if (of_ep.id >= MAX_CRTC) { 1012 ret = dev_err_probe(dev, -EINVAL, 1013 "Invalid endpoint%u number\n", of_ep.port); 1014 break; 1015 } 1016 1017 output_present[of_ep.id] = true; 1018 } 1019 1020 if (ret) { 1021 of_node_put(ep_node); 1022 return ret; 1023 } 1024 1025 if (output_present[CRTC_MAIN]) { 1026 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN, 1027 &data->main_path, &data->main_len); 1028 if (ret && ret != -ENODEV) 1029 return ret; 1030 } 1031 1032 if (output_present[CRTC_EXT]) { 1033 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT, 1034 &data->ext_path, &data->ext_len); 1035 if (ret && ret != -ENODEV) 1036 return ret; 1037 } 1038 1039 if (output_present[CRTC_THIRD]) { 1040 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD, 1041 &data->third_path, &data->third_len); 1042 if (ret && ret != -ENODEV) 1043 return ret; 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int mtk_drm_probe(struct platform_device *pdev) 1050 { 1051 struct device *dev = &pdev->dev; 1052 struct device_node *phandle = dev->parent->of_node; 1053 const struct of_device_id *of_id; 1054 struct mtk_drm_private *private; 1055 struct mtk_mmsys_driver_data *mtk_drm_data; 1056 struct device_node *node; 1057 struct component_match *match = NULL; 1058 struct platform_device *ovl_adaptor; 1059 int ret; 1060 int i; 1061 1062 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 1063 if (!private) 1064 return -ENOMEM; 1065 1066 private->mmsys_dev = dev->parent; 1067 if (!private->mmsys_dev) { 1068 dev_err(dev, "Failed to get MMSYS device\n"); 1069 return -ENODEV; 1070 } 1071 1072 of_id = of_match_node(mtk_drm_of_ids, phandle); 1073 if (!of_id) 1074 return -ENODEV; 1075 1076 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data; 1077 if (!mtk_drm_data) 1078 return -EINVAL; 1079 1080 /* Try to build the display pipeline from devicetree graphs */ 1081 if (of_graph_is_present(phandle)) { 1082 dev_dbg(dev, "Building display pipeline for MMSYS %u\n", 1083 mtk_drm_data->mmsys_id); 1084 private->data = devm_kmemdup(dev, mtk_drm_data, 1085 sizeof(*mtk_drm_data), GFP_KERNEL); 1086 if (!private->data) 1087 return -ENOMEM; 1088 1089 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data); 1090 if (ret) 1091 return ret; 1092 } else { 1093 /* No devicetree graphs support: go with hardcoded paths if present */ 1094 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id); 1095 private->data = mtk_drm_data; 1096 } 1097 1098 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 1099 sizeof(*private->all_drm_private), 1100 GFP_KERNEL); 1101 if (!private->all_drm_private) 1102 return -ENOMEM; 1103 1104 /* Bringup ovl_adaptor */ 1105 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 1106 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 1107 PLATFORM_DEVID_AUTO, 1108 (void *)private->mmsys_dev, 1109 sizeof(*private->mmsys_dev)); 1110 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 1111 mtk_ddp_comp_init(dev, NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 1112 DDP_COMPONENT_DRM_OVL_ADAPTOR); 1113 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 1114 } 1115 1116 /* Iterate over sibling DISP function blocks */ 1117 for_each_child_of_node(phandle->parent, node) { 1118 enum mtk_ddp_comp_type comp_type; 1119 int comp_id; 1120 1121 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type); 1122 if (ret) 1123 continue; 1124 1125 if (!of_device_is_available(node)) { 1126 dev_dbg(dev, "Skipping disabled component %pOF\n", 1127 node); 1128 continue; 1129 } 1130 1131 if (comp_type == MTK_DISP_MUTEX) { 1132 int id; 1133 1134 id = of_alias_get_id(node, "mutex"); 1135 if (id < 0 || id == private->data->mmsys_id) { 1136 private->mutex_node = of_node_get(node); 1137 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 1138 } 1139 continue; 1140 } 1141 1142 comp_id = mtk_ddp_comp_get_id(node, comp_type); 1143 if (comp_id < 0) { 1144 dev_warn(dev, "Skipping unknown component %pOF\n", 1145 node); 1146 continue; 1147 } 1148 1149 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 1150 continue; 1151 1152 private->comp_node[comp_id] = of_node_get(node); 1153 1154 /* 1155 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 1156 * blocks have separate component platform drivers and initialize their own 1157 * DDP component structure. The others are initialized here. 1158 */ 1159 if (comp_type == MTK_DISP_AAL || 1160 comp_type == MTK_DISP_CCORR || 1161 comp_type == MTK_DISP_COLOR || 1162 comp_type == MTK_DISP_GAMMA || 1163 comp_type == MTK_DISP_MERGE || 1164 comp_type == MTK_DISP_OVL || 1165 comp_type == MTK_DISP_OVL_2L || 1166 comp_type == MTK_DISP_OVL_ADAPTOR || 1167 comp_type == MTK_DISP_RDMA || 1168 comp_type == MTK_DP_INTF || 1169 comp_type == MTK_DPI || 1170 comp_type == MTK_DSI) { 1171 dev_info(dev, "Adding component match for %pOF\n", 1172 node); 1173 drm_of_component_match_add(dev, &match, component_compare_of, 1174 node); 1175 } 1176 1177 ret = mtk_ddp_comp_init(dev, node, &private->ddp_comp[comp_id], comp_id); 1178 if (ret) { 1179 of_node_put(node); 1180 goto err_node; 1181 } 1182 } 1183 1184 if (!private->mutex_node) { 1185 dev_err(dev, "Failed to find disp-mutex node\n"); 1186 ret = -ENODEV; 1187 goto err_node; 1188 } 1189 1190 pm_runtime_enable(dev); 1191 1192 platform_set_drvdata(pdev, private); 1193 1194 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 1195 if (ret) 1196 goto err_pm; 1197 1198 return 0; 1199 1200 err_pm: 1201 pm_runtime_disable(dev); 1202 err_node: 1203 of_node_put(private->mutex_node); 1204 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1205 of_node_put(private->comp_node[i]); 1206 return ret; 1207 } 1208 1209 static void mtk_drm_remove(struct platform_device *pdev) 1210 { 1211 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1212 int i; 1213 1214 component_master_del(&pdev->dev, &mtk_drm_ops); 1215 pm_runtime_disable(&pdev->dev); 1216 of_node_put(private->mutex_node); 1217 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1218 of_node_put(private->comp_node[i]); 1219 } 1220 1221 static void mtk_drm_shutdown(struct platform_device *pdev) 1222 { 1223 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1224 1225 drm_atomic_helper_shutdown(private->drm); 1226 } 1227 1228 static int mtk_drm_sys_prepare(struct device *dev) 1229 { 1230 struct mtk_drm_private *private = dev_get_drvdata(dev); 1231 struct drm_device *drm = private->drm; 1232 1233 if (private->drm_master) 1234 return drm_mode_config_helper_suspend(drm); 1235 else 1236 return 0; 1237 } 1238 1239 static void mtk_drm_sys_complete(struct device *dev) 1240 { 1241 struct mtk_drm_private *private = dev_get_drvdata(dev); 1242 struct drm_device *drm = private->drm; 1243 int ret = 0; 1244 1245 if (private->drm_master) 1246 ret = drm_mode_config_helper_resume(drm); 1247 if (ret) 1248 dev_err(dev, "Failed to resume\n"); 1249 } 1250 1251 static const struct dev_pm_ops mtk_drm_pm_ops = { 1252 .prepare = mtk_drm_sys_prepare, 1253 .complete = mtk_drm_sys_complete, 1254 }; 1255 1256 static struct platform_driver mtk_drm_platform_driver = { 1257 .probe = mtk_drm_probe, 1258 .remove = mtk_drm_remove, 1259 .shutdown = mtk_drm_shutdown, 1260 .driver = { 1261 .name = "mediatek-drm", 1262 .pm = &mtk_drm_pm_ops, 1263 }, 1264 }; 1265 1266 static struct platform_driver * const mtk_drm_drivers[] = { 1267 &mtk_disp_aal_driver, 1268 &mtk_disp_ccorr_driver, 1269 &mtk_disp_color_driver, 1270 &mtk_disp_gamma_driver, 1271 &mtk_disp_merge_driver, 1272 &mtk_disp_ovl_adaptor_driver, 1273 &mtk_disp_ovl_driver, 1274 &mtk_disp_rdma_driver, 1275 &mtk_dpi_driver, 1276 &mtk_drm_platform_driver, 1277 &mtk_dsi_driver, 1278 &mtk_ethdr_driver, 1279 &mtk_mdp_rdma_driver, 1280 &mtk_padding_driver, 1281 }; 1282 1283 static int __init mtk_drm_init(void) 1284 { 1285 return platform_register_drivers(mtk_drm_drivers, 1286 ARRAY_SIZE(mtk_drm_drivers)); 1287 } 1288 1289 static void __exit mtk_drm_exit(void) 1290 { 1291 platform_unregister_drivers(mtk_drm_drivers, 1292 ARRAY_SIZE(mtk_drm_drivers)); 1293 } 1294 1295 module_init(mtk_drm_init); 1296 module_exit(mtk_drm_exit); 1297 1298 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1299 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1300 MODULE_LICENSE("GPL v2"); 1301