1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/clients/drm_client_setup.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_crtc.h" 29 #include "mtk_ddp_comp.h" 30 #include "mtk_disp_drv.h" 31 #include "mtk_drm_drv.h" 32 #include "mtk_gem.h" 33 34 #define DRIVER_NAME "mediatek" 35 #define DRIVER_DESC "Mediatek SoC DRM" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_mode_fb_cmd2 *cmd) 47 { 48 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 49 50 if (info->num_planes != 1) 51 return ERR_PTR(-EINVAL); 52 53 return drm_gem_fb_create(dev, file, cmd); 54 } 55 56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 57 .fb_create = mtk_drm_mode_fb_create, 58 .atomic_check = drm_atomic_helper_check, 59 .atomic_commit = drm_atomic_helper_commit, 60 }; 61 62 static const unsigned int mt2701_mtk_ddp_main[] = { 63 DDP_COMPONENT_OVL0, 64 DDP_COMPONENT_RDMA0, 65 DDP_COMPONENT_COLOR0, 66 DDP_COMPONENT_BLS, 67 DDP_COMPONENT_DSI0, 68 }; 69 70 static const unsigned int mt2701_mtk_ddp_ext[] = { 71 DDP_COMPONENT_RDMA1, 72 DDP_COMPONENT_DPI0, 73 }; 74 75 static const unsigned int mt7623_mtk_ddp_main[] = { 76 DDP_COMPONENT_OVL0, 77 DDP_COMPONENT_RDMA0, 78 DDP_COMPONENT_COLOR0, 79 DDP_COMPONENT_BLS, 80 DDP_COMPONENT_DPI0, 81 }; 82 83 static const unsigned int mt7623_mtk_ddp_ext[] = { 84 DDP_COMPONENT_RDMA1, 85 DDP_COMPONENT_DSI0, 86 }; 87 88 static const unsigned int mt2712_mtk_ddp_main[] = { 89 DDP_COMPONENT_OVL0, 90 DDP_COMPONENT_COLOR0, 91 DDP_COMPONENT_AAL0, 92 DDP_COMPONENT_OD0, 93 DDP_COMPONENT_RDMA0, 94 DDP_COMPONENT_DPI0, 95 DDP_COMPONENT_PWM0, 96 }; 97 98 static const unsigned int mt2712_mtk_ddp_ext[] = { 99 DDP_COMPONENT_OVL1, 100 DDP_COMPONENT_COLOR1, 101 DDP_COMPONENT_AAL1, 102 DDP_COMPONENT_OD1, 103 DDP_COMPONENT_RDMA1, 104 DDP_COMPONENT_DPI1, 105 DDP_COMPONENT_PWM1, 106 }; 107 108 static const unsigned int mt2712_mtk_ddp_third[] = { 109 DDP_COMPONENT_RDMA2, 110 DDP_COMPONENT_DSI3, 111 DDP_COMPONENT_PWM2, 112 }; 113 114 static unsigned int mt8167_mtk_ddp_main[] = { 115 DDP_COMPONENT_OVL0, 116 DDP_COMPONENT_COLOR0, 117 DDP_COMPONENT_CCORR, 118 DDP_COMPONENT_AAL0, 119 DDP_COMPONENT_GAMMA, 120 DDP_COMPONENT_DITHER0, 121 DDP_COMPONENT_RDMA0, 122 DDP_COMPONENT_DSI0, 123 }; 124 125 static const unsigned int mt8173_mtk_ddp_main[] = { 126 DDP_COMPONENT_OVL0, 127 DDP_COMPONENT_COLOR0, 128 DDP_COMPONENT_AAL0, 129 DDP_COMPONENT_OD0, 130 DDP_COMPONENT_RDMA0, 131 DDP_COMPONENT_UFOE, 132 DDP_COMPONENT_DSI0, 133 DDP_COMPONENT_PWM0, 134 }; 135 136 static const unsigned int mt8173_mtk_ddp_ext[] = { 137 DDP_COMPONENT_OVL1, 138 DDP_COMPONENT_COLOR1, 139 DDP_COMPONENT_GAMMA, 140 DDP_COMPONENT_RDMA1, 141 DDP_COMPONENT_DPI0, 142 }; 143 144 static const unsigned int mt8183_mtk_ddp_main[] = { 145 DDP_COMPONENT_OVL0, 146 DDP_COMPONENT_OVL_2L0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_COLOR0, 149 DDP_COMPONENT_CCORR, 150 DDP_COMPONENT_AAL0, 151 DDP_COMPONENT_GAMMA, 152 DDP_COMPONENT_DITHER0, 153 DDP_COMPONENT_DSI0, 154 }; 155 156 static const unsigned int mt8183_mtk_ddp_ext[] = { 157 DDP_COMPONENT_OVL_2L1, 158 DDP_COMPONENT_RDMA1, 159 DDP_COMPONENT_DPI0, 160 }; 161 162 static const unsigned int mt8186_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER0, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const unsigned int mt8186_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L0, 176 DDP_COMPONENT_RDMA1, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const unsigned int mt8188_mtk_ddp_main[] = { 181 DDP_COMPONENT_OVL0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_COLOR0, 184 DDP_COMPONENT_CCORR, 185 DDP_COMPONENT_AAL0, 186 DDP_COMPONENT_GAMMA, 187 DDP_COMPONENT_POSTMASK0, 188 DDP_COMPONENT_DITHER0, 189 }; 190 191 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 192 {0, DDP_COMPONENT_DP_INTF0}, 193 {0, DDP_COMPONENT_DSI0}, 194 }; 195 196 static const unsigned int mt8192_mtk_ddp_main[] = { 197 DDP_COMPONENT_OVL0, 198 DDP_COMPONENT_OVL_2L0, 199 DDP_COMPONENT_RDMA0, 200 DDP_COMPONENT_COLOR0, 201 DDP_COMPONENT_CCORR, 202 DDP_COMPONENT_AAL0, 203 DDP_COMPONENT_GAMMA, 204 DDP_COMPONENT_POSTMASK0, 205 DDP_COMPONENT_DITHER0, 206 DDP_COMPONENT_DSI0, 207 }; 208 209 static const unsigned int mt8192_mtk_ddp_ext[] = { 210 DDP_COMPONENT_OVL_2L2, 211 DDP_COMPONENT_RDMA4, 212 DDP_COMPONENT_DPI0, 213 }; 214 215 static const unsigned int mt8195_mtk_ddp_main[] = { 216 DDP_COMPONENT_OVL0, 217 DDP_COMPONENT_RDMA0, 218 DDP_COMPONENT_COLOR0, 219 DDP_COMPONENT_CCORR, 220 DDP_COMPONENT_AAL0, 221 DDP_COMPONENT_GAMMA, 222 DDP_COMPONENT_DITHER0, 223 DDP_COMPONENT_DSC0, 224 DDP_COMPONENT_MERGE0, 225 DDP_COMPONENT_DP_INTF0, 226 }; 227 228 static const unsigned int mt8195_mtk_ddp_ext[] = { 229 DDP_COMPONENT_DRM_OVL_ADAPTOR, 230 DDP_COMPONENT_MERGE5, 231 DDP_COMPONENT_DP_INTF1, 232 }; 233 234 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 235 .main_path = mt2701_mtk_ddp_main, 236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 237 .ext_path = mt2701_mtk_ddp_ext, 238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 239 .shadow_register = true, 240 .mmsys_dev_num = 1, 241 }; 242 243 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 244 .main_path = mt7623_mtk_ddp_main, 245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 246 .ext_path = mt7623_mtk_ddp_ext, 247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 248 .shadow_register = true, 249 .mmsys_dev_num = 1, 250 }; 251 252 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 253 .main_path = mt2712_mtk_ddp_main, 254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 255 .ext_path = mt2712_mtk_ddp_ext, 256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 257 .third_path = mt2712_mtk_ddp_third, 258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 259 .mmsys_dev_num = 1, 260 }; 261 262 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 263 .main_path = mt8167_mtk_ddp_main, 264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 265 .mmsys_dev_num = 1, 266 }; 267 268 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 269 .main_path = mt8173_mtk_ddp_main, 270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 271 .ext_path = mt8173_mtk_ddp_ext, 272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 273 .mmsys_dev_num = 1, 274 }; 275 276 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 277 .main_path = mt8183_mtk_ddp_main, 278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 279 .ext_path = mt8183_mtk_ddp_ext, 280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 281 .mmsys_dev_num = 1, 282 }; 283 284 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 285 .main_path = mt8186_mtk_ddp_main, 286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 287 .ext_path = mt8186_mtk_ddp_ext, 288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 289 .mmsys_dev_num = 1, 290 }; 291 292 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 293 .main_path = mt8188_mtk_ddp_main, 294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 295 .conn_routes = mt8188_mtk_ddp_main_routes, 296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 297 .mmsys_dev_num = 2, 298 .max_width = 8191, 299 .min_width = 1, 300 .min_height = 1, 301 }; 302 303 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 304 .main_path = mt8192_mtk_ddp_main, 305 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 306 .ext_path = mt8192_mtk_ddp_ext, 307 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 308 .mmsys_dev_num = 1, 309 }; 310 311 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 312 .main_path = mt8195_mtk_ddp_main, 313 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 314 .mmsys_dev_num = 2, 315 .max_width = 8191, 316 .min_width = 1, 317 .min_height = 1, 318 }; 319 320 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 321 .ext_path = mt8195_mtk_ddp_ext, 322 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 323 .mmsys_id = 1, 324 .mmsys_dev_num = 2, 325 .max_width = 8191, 326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 327 .min_height = 1, 328 }; 329 330 static const struct of_device_id mtk_drm_of_ids[] = { 331 { .compatible = "mediatek,mt2701-mmsys", 332 .data = &mt2701_mmsys_driver_data}, 333 { .compatible = "mediatek,mt7623-mmsys", 334 .data = &mt7623_mmsys_driver_data}, 335 { .compatible = "mediatek,mt2712-mmsys", 336 .data = &mt2712_mmsys_driver_data}, 337 { .compatible = "mediatek,mt8167-mmsys", 338 .data = &mt8167_mmsys_driver_data}, 339 { .compatible = "mediatek,mt8173-mmsys", 340 .data = &mt8173_mmsys_driver_data}, 341 { .compatible = "mediatek,mt8183-mmsys", 342 .data = &mt8183_mmsys_driver_data}, 343 { .compatible = "mediatek,mt8186-mmsys", 344 .data = &mt8186_mmsys_driver_data}, 345 { .compatible = "mediatek,mt8188-vdosys0", 346 .data = &mt8188_vdosys0_driver_data}, 347 { .compatible = "mediatek,mt8188-vdosys1", 348 .data = &mt8195_vdosys1_driver_data}, 349 { .compatible = "mediatek,mt8192-mmsys", 350 .data = &mt8192_mmsys_driver_data}, 351 { .compatible = "mediatek,mt8195-mmsys", 352 .data = &mt8195_vdosys0_driver_data}, 353 { .compatible = "mediatek,mt8195-vdosys0", 354 .data = &mt8195_vdosys0_driver_data}, 355 { .compatible = "mediatek,mt8195-vdosys1", 356 .data = &mt8195_vdosys1_driver_data}, 357 { } 358 }; 359 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 360 361 static int mtk_drm_match(struct device *dev, void *data) 362 { 363 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 364 return true; 365 return false; 366 } 367 368 static bool mtk_drm_get_all_drm_priv(struct device *dev) 369 { 370 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 371 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 372 struct mtk_drm_private *temp_drm_priv; 373 struct device_node *phandle = dev->parent->of_node; 374 const struct of_device_id *of_id; 375 struct device *drm_dev; 376 unsigned int cnt = 0; 377 int i, j; 378 379 for_each_child_of_node_scoped(phandle->parent, node) { 380 struct platform_device *pdev; 381 382 of_id = of_match_node(mtk_drm_of_ids, node); 383 if (!of_id) 384 continue; 385 386 pdev = of_find_device_by_node(node); 387 if (!pdev) 388 continue; 389 390 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 391 if (!drm_dev) 392 continue; 393 394 temp_drm_priv = dev_get_drvdata(drm_dev); 395 if (!temp_drm_priv) 396 continue; 397 398 if (temp_drm_priv->data->main_len) 399 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 400 else if (temp_drm_priv->data->ext_len) 401 all_drm_priv[CRTC_EXT] = temp_drm_priv; 402 else if (temp_drm_priv->data->third_len) 403 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 404 405 if (temp_drm_priv->mtk_drm_bound) 406 cnt++; 407 408 if (cnt == MAX_CRTC) 409 break; 410 } 411 412 if (drm_priv->data->mmsys_dev_num == cnt) { 413 for (i = 0; i < cnt; i++) 414 for (j = 0; j < cnt; j++) 415 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 416 417 return true; 418 } 419 420 return false; 421 } 422 423 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 424 { 425 const struct mtk_mmsys_driver_data *drv_data = private->data; 426 int i; 427 428 if (drv_data->main_path) 429 for (i = 0; i < drv_data->main_len; i++) 430 if (drv_data->main_path[i] == comp_id) 431 return true; 432 433 if (drv_data->ext_path) 434 for (i = 0; i < drv_data->ext_len; i++) 435 if (drv_data->ext_path[i] == comp_id) 436 return true; 437 438 if (drv_data->third_path) 439 for (i = 0; i < drv_data->third_len; i++) 440 if (drv_data->third_path[i] == comp_id) 441 return true; 442 443 if (drv_data->num_conn_routes) 444 for (i = 0; i < drv_data->num_conn_routes; i++) 445 if (drv_data->conn_routes[i].route_ddp == comp_id) 446 return true; 447 448 return false; 449 } 450 451 static int mtk_drm_kms_init(struct drm_device *drm) 452 { 453 struct mtk_drm_private *private = drm->dev_private; 454 struct mtk_drm_private *priv_n; 455 struct device *dma_dev = NULL; 456 struct drm_crtc *crtc; 457 int ret, i, j; 458 459 if (drm_firmware_drivers_only()) 460 return -ENODEV; 461 462 ret = drmm_mode_config_init(drm); 463 if (ret) 464 goto put_mutex_dev; 465 466 drm->mode_config.min_width = 64; 467 drm->mode_config.min_height = 64; 468 469 /* 470 * set max width and height as default value(4096x4096). 471 * this value would be used to check framebuffer size limitation 472 * at drm_mode_addfb(). 473 */ 474 drm->mode_config.max_width = 4096; 475 drm->mode_config.max_height = 4096; 476 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 477 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 478 479 for (i = 0; i < private->data->mmsys_dev_num; i++) { 480 drm->dev_private = private->all_drm_private[i]; 481 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 482 if (ret) 483 goto put_mutex_dev; 484 } 485 486 /* 487 * Ensure internal panels are at the top of the connector list before 488 * crtc creation. 489 */ 490 drm_helper_move_panel_connectors_to_head(drm); 491 492 /* 493 * 1. We currently support two fixed data streams, each optional, 494 * and each statically assigned to a crtc: 495 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 496 * 2. For multi mmsys architecture, crtc path data are located in 497 * different drm private data structures. Loop through crtc index to 498 * create crtc from the main path and then ext_path and finally the 499 * third path. 500 */ 501 for (i = 0; i < MAX_CRTC; i++) { 502 for (j = 0; j < private->data->mmsys_dev_num; j++) { 503 priv_n = private->all_drm_private[j]; 504 505 if (priv_n->data->max_width) 506 drm->mode_config.max_width = priv_n->data->max_width; 507 508 if (priv_n->data->min_width) 509 drm->mode_config.min_width = priv_n->data->min_width; 510 511 if (priv_n->data->min_height) 512 drm->mode_config.min_height = priv_n->data->min_height; 513 514 if (i == CRTC_MAIN && priv_n->data->main_len) { 515 ret = mtk_crtc_create(drm, priv_n->data->main_path, 516 priv_n->data->main_len, j, 517 priv_n->data->conn_routes, 518 priv_n->data->num_conn_routes); 519 if (ret) 520 goto err_component_unbind; 521 522 continue; 523 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 524 ret = mtk_crtc_create(drm, priv_n->data->ext_path, 525 priv_n->data->ext_len, j, NULL, 0); 526 if (ret) 527 goto err_component_unbind; 528 529 continue; 530 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 531 ret = mtk_crtc_create(drm, priv_n->data->third_path, 532 priv_n->data->third_len, j, NULL, 0); 533 if (ret) 534 goto err_component_unbind; 535 536 continue; 537 } 538 } 539 } 540 541 /* IGT will check if the cursor size is configured */ 542 drm->mode_config.cursor_width = 512; 543 drm->mode_config.cursor_height = 512; 544 545 /* Use OVL device for all DMA memory allocations */ 546 crtc = drm_crtc_from_index(drm, 0); 547 if (crtc) 548 dma_dev = mtk_crtc_dma_dev_get(crtc); 549 if (!dma_dev) { 550 ret = -ENODEV; 551 dev_err(drm->dev, "Need at least one OVL device\n"); 552 goto err_component_unbind; 553 } 554 555 for (i = 0; i < private->data->mmsys_dev_num; i++) 556 private->all_drm_private[i]->dma_dev = dma_dev; 557 558 /* 559 * Configure the DMA segment size to make sure we get contiguous IOVA 560 * when importing PRIME buffers. 561 */ 562 dma_set_max_seg_size(dma_dev, UINT_MAX); 563 564 ret = drm_vblank_init(drm, MAX_CRTC); 565 if (ret < 0) 566 goto err_component_unbind; 567 568 drm_kms_helper_poll_init(drm); 569 drm_mode_config_reset(drm); 570 571 return 0; 572 573 err_component_unbind: 574 for (i = 0; i < private->data->mmsys_dev_num; i++) 575 component_unbind_all(private->all_drm_private[i]->dev, drm); 576 put_mutex_dev: 577 for (i = 0; i < private->data->mmsys_dev_num; i++) 578 put_device(private->all_drm_private[i]->mutex_dev); 579 580 return ret; 581 } 582 583 static void mtk_drm_kms_deinit(struct drm_device *drm) 584 { 585 drm_kms_helper_poll_fini(drm); 586 drm_atomic_helper_shutdown(drm); 587 588 component_unbind_all(drm->dev, drm); 589 } 590 591 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 592 593 /* 594 * We need to override this because the device used to import the memory is 595 * not dev->dev, as drm_gem_prime_import() expects. 596 */ 597 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev, 598 struct dma_buf *dma_buf) 599 { 600 struct mtk_drm_private *private = dev->dev_private; 601 602 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 603 } 604 605 static const struct drm_driver mtk_drm_driver = { 606 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 607 608 .dumb_create = mtk_gem_dumb_create, 609 DRM_FBDEV_DMA_DRIVER_OPS, 610 611 .gem_prime_import = mtk_gem_prime_import, 612 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 613 .fops = &mtk_drm_fops, 614 615 .name = DRIVER_NAME, 616 .desc = DRIVER_DESC, 617 .major = DRIVER_MAJOR, 618 .minor = DRIVER_MINOR, 619 }; 620 621 static int compare_dev(struct device *dev, void *data) 622 { 623 return dev == (struct device *)data; 624 } 625 626 static int mtk_drm_bind(struct device *dev) 627 { 628 struct mtk_drm_private *private = dev_get_drvdata(dev); 629 struct platform_device *pdev; 630 struct drm_device *drm; 631 int ret, i; 632 633 pdev = of_find_device_by_node(private->mutex_node); 634 if (!pdev) { 635 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 636 private->mutex_node); 637 of_node_put(private->mutex_node); 638 return -EPROBE_DEFER; 639 } 640 641 private->mutex_dev = &pdev->dev; 642 private->mtk_drm_bound = true; 643 private->dev = dev; 644 645 if (!mtk_drm_get_all_drm_priv(dev)) 646 return 0; 647 648 drm = drm_dev_alloc(&mtk_drm_driver, dev); 649 if (IS_ERR(drm)) 650 return PTR_ERR(drm); 651 652 private->drm_master = true; 653 drm->dev_private = private; 654 for (i = 0; i < private->data->mmsys_dev_num; i++) 655 private->all_drm_private[i]->drm = drm; 656 657 ret = mtk_drm_kms_init(drm); 658 if (ret < 0) 659 goto err_free; 660 661 ret = drm_dev_register(drm, 0); 662 if (ret < 0) 663 goto err_deinit; 664 665 drm_client_setup(drm, NULL); 666 667 return 0; 668 669 err_deinit: 670 mtk_drm_kms_deinit(drm); 671 err_free: 672 private->drm = NULL; 673 drm_dev_put(drm); 674 return ret; 675 } 676 677 static void mtk_drm_unbind(struct device *dev) 678 { 679 struct mtk_drm_private *private = dev_get_drvdata(dev); 680 681 /* for multi mmsys dev, unregister drm dev in mmsys master */ 682 if (private->drm_master) { 683 drm_dev_unregister(private->drm); 684 mtk_drm_kms_deinit(private->drm); 685 drm_dev_put(private->drm); 686 } 687 private->mtk_drm_bound = false; 688 private->drm_master = false; 689 private->drm = NULL; 690 } 691 692 static const struct component_master_ops mtk_drm_ops = { 693 .bind = mtk_drm_bind, 694 .unbind = mtk_drm_unbind, 695 }; 696 697 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 698 { .compatible = "mediatek,mt8167-disp-aal", 699 .data = (void *)MTK_DISP_AAL}, 700 { .compatible = "mediatek,mt8173-disp-aal", 701 .data = (void *)MTK_DISP_AAL}, 702 { .compatible = "mediatek,mt8183-disp-aal", 703 .data = (void *)MTK_DISP_AAL}, 704 { .compatible = "mediatek,mt8192-disp-aal", 705 .data = (void *)MTK_DISP_AAL}, 706 { .compatible = "mediatek,mt8167-disp-ccorr", 707 .data = (void *)MTK_DISP_CCORR }, 708 { .compatible = "mediatek,mt8183-disp-ccorr", 709 .data = (void *)MTK_DISP_CCORR }, 710 { .compatible = "mediatek,mt8192-disp-ccorr", 711 .data = (void *)MTK_DISP_CCORR }, 712 { .compatible = "mediatek,mt2701-disp-color", 713 .data = (void *)MTK_DISP_COLOR }, 714 { .compatible = "mediatek,mt8167-disp-color", 715 .data = (void *)MTK_DISP_COLOR }, 716 { .compatible = "mediatek,mt8173-disp-color", 717 .data = (void *)MTK_DISP_COLOR }, 718 { .compatible = "mediatek,mt8167-disp-dither", 719 .data = (void *)MTK_DISP_DITHER }, 720 { .compatible = "mediatek,mt8183-disp-dither", 721 .data = (void *)MTK_DISP_DITHER }, 722 { .compatible = "mediatek,mt8195-disp-dsc", 723 .data = (void *)MTK_DISP_DSC }, 724 { .compatible = "mediatek,mt8167-disp-gamma", 725 .data = (void *)MTK_DISP_GAMMA, }, 726 { .compatible = "mediatek,mt8173-disp-gamma", 727 .data = (void *)MTK_DISP_GAMMA, }, 728 { .compatible = "mediatek,mt8183-disp-gamma", 729 .data = (void *)MTK_DISP_GAMMA, }, 730 { .compatible = "mediatek,mt8195-disp-gamma", 731 .data = (void *)MTK_DISP_GAMMA, }, 732 { .compatible = "mediatek,mt8195-disp-merge", 733 .data = (void *)MTK_DISP_MERGE }, 734 { .compatible = "mediatek,mt2701-disp-mutex", 735 .data = (void *)MTK_DISP_MUTEX }, 736 { .compatible = "mediatek,mt2712-disp-mutex", 737 .data = (void *)MTK_DISP_MUTEX }, 738 { .compatible = "mediatek,mt8167-disp-mutex", 739 .data = (void *)MTK_DISP_MUTEX }, 740 { .compatible = "mediatek,mt8173-disp-mutex", 741 .data = (void *)MTK_DISP_MUTEX }, 742 { .compatible = "mediatek,mt8183-disp-mutex", 743 .data = (void *)MTK_DISP_MUTEX }, 744 { .compatible = "mediatek,mt8186-disp-mutex", 745 .data = (void *)MTK_DISP_MUTEX }, 746 { .compatible = "mediatek,mt8188-disp-mutex", 747 .data = (void *)MTK_DISP_MUTEX }, 748 { .compatible = "mediatek,mt8192-disp-mutex", 749 .data = (void *)MTK_DISP_MUTEX }, 750 { .compatible = "mediatek,mt8195-disp-mutex", 751 .data = (void *)MTK_DISP_MUTEX }, 752 { .compatible = "mediatek,mt8173-disp-od", 753 .data = (void *)MTK_DISP_OD }, 754 { .compatible = "mediatek,mt2701-disp-ovl", 755 .data = (void *)MTK_DISP_OVL }, 756 { .compatible = "mediatek,mt8167-disp-ovl", 757 .data = (void *)MTK_DISP_OVL }, 758 { .compatible = "mediatek,mt8173-disp-ovl", 759 .data = (void *)MTK_DISP_OVL }, 760 { .compatible = "mediatek,mt8183-disp-ovl", 761 .data = (void *)MTK_DISP_OVL }, 762 { .compatible = "mediatek,mt8192-disp-ovl", 763 .data = (void *)MTK_DISP_OVL }, 764 { .compatible = "mediatek,mt8195-disp-ovl", 765 .data = (void *)MTK_DISP_OVL }, 766 { .compatible = "mediatek,mt8183-disp-ovl-2l", 767 .data = (void *)MTK_DISP_OVL_2L }, 768 { .compatible = "mediatek,mt8192-disp-ovl-2l", 769 .data = (void *)MTK_DISP_OVL_2L }, 770 { .compatible = "mediatek,mt8192-disp-postmask", 771 .data = (void *)MTK_DISP_POSTMASK }, 772 { .compatible = "mediatek,mt2701-disp-pwm", 773 .data = (void *)MTK_DISP_BLS }, 774 { .compatible = "mediatek,mt8167-disp-pwm", 775 .data = (void *)MTK_DISP_PWM }, 776 { .compatible = "mediatek,mt8173-disp-pwm", 777 .data = (void *)MTK_DISP_PWM }, 778 { .compatible = "mediatek,mt2701-disp-rdma", 779 .data = (void *)MTK_DISP_RDMA }, 780 { .compatible = "mediatek,mt8167-disp-rdma", 781 .data = (void *)MTK_DISP_RDMA }, 782 { .compatible = "mediatek,mt8173-disp-rdma", 783 .data = (void *)MTK_DISP_RDMA }, 784 { .compatible = "mediatek,mt8183-disp-rdma", 785 .data = (void *)MTK_DISP_RDMA }, 786 { .compatible = "mediatek,mt8195-disp-rdma", 787 .data = (void *)MTK_DISP_RDMA }, 788 { .compatible = "mediatek,mt8173-disp-ufoe", 789 .data = (void *)MTK_DISP_UFOE }, 790 { .compatible = "mediatek,mt8173-disp-wdma", 791 .data = (void *)MTK_DISP_WDMA }, 792 { .compatible = "mediatek,mt2701-dpi", 793 .data = (void *)MTK_DPI }, 794 { .compatible = "mediatek,mt8167-dsi", 795 .data = (void *)MTK_DSI }, 796 { .compatible = "mediatek,mt8173-dpi", 797 .data = (void *)MTK_DPI }, 798 { .compatible = "mediatek,mt8183-dpi", 799 .data = (void *)MTK_DPI }, 800 { .compatible = "mediatek,mt8186-dpi", 801 .data = (void *)MTK_DPI }, 802 { .compatible = "mediatek,mt8188-dp-intf", 803 .data = (void *)MTK_DP_INTF }, 804 { .compatible = "mediatek,mt8192-dpi", 805 .data = (void *)MTK_DPI }, 806 { .compatible = "mediatek,mt8195-dp-intf", 807 .data = (void *)MTK_DP_INTF }, 808 { .compatible = "mediatek,mt2701-dsi", 809 .data = (void *)MTK_DSI }, 810 { .compatible = "mediatek,mt8173-dsi", 811 .data = (void *)MTK_DSI }, 812 { .compatible = "mediatek,mt8183-dsi", 813 .data = (void *)MTK_DSI }, 814 { .compatible = "mediatek,mt8186-dsi", 815 .data = (void *)MTK_DSI }, 816 { .compatible = "mediatek,mt8188-dsi", 817 .data = (void *)MTK_DSI }, 818 { } 819 }; 820 821 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype) 822 { 823 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 824 825 if (!of_id) 826 return -EINVAL; 827 828 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data); 829 830 return 0; 831 } 832 833 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, 834 int output_port, enum mtk_crtc_path crtc_path, 835 struct device_node **next, unsigned int *cid) 836 { 837 struct device_node *ep_dev_node, *ep_out; 838 enum mtk_ddp_comp_type comp_type; 839 int ret; 840 841 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path); 842 if (!ep_out) 843 return -ENOENT; 844 845 ep_dev_node = of_graph_get_remote_port_parent(ep_out); 846 of_node_put(ep_out); 847 if (!ep_dev_node) 848 return -EINVAL; 849 850 /* 851 * Pass the next node pointer regardless of failures in the later code 852 * so that if this function is called in a loop it will walk through all 853 * of the subsequent endpoints anyway. 854 */ 855 *next = ep_dev_node; 856 857 if (!of_device_is_available(ep_dev_node)) 858 return -ENODEV; 859 860 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); 861 if (ret) { 862 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { 863 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR; 864 return 0; 865 } 866 return ret; 867 } 868 869 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type); 870 if (ret < 0) 871 return ret; 872 873 /* All ok! Pass the Component ID to the caller. */ 874 *cid = (unsigned int)ret; 875 876 return 0; 877 } 878 879 /** 880 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path 881 * @dev: The mediatek-drm device 882 * @cpath: CRTC Path relative to a VDO or MMSYS 883 * @out_path: Pointer to an array that will contain the new pipeline 884 * @out_path_len: Number of entries in the pipeline array 885 * 886 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending 887 * on the board-specific desired display configuration; this function walks 888 * through all of the output endpoints starting from a VDO or MMSYS hardware 889 * instance and builds the right pipeline as specified in device trees. 890 * 891 * Return: 892 * * %0 - Display HW Pipeline successfully built and validated 893 * * %-ENOENT - Display pipeline was not specified in device tree 894 * * %-EINVAL - Display pipeline built but validation failed 895 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller 896 */ 897 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath, 898 const unsigned int **out_path, 899 unsigned int *out_path_len) 900 { 901 struct device_node *next, *prev, *vdo = dev->parent->of_node; 902 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 }; 903 unsigned int *final_ddp_path; 904 unsigned short int idx = 0; 905 bool ovl_adaptor_comp_added = false; 906 int ret; 907 908 /* Get the first entry for the temp_path array */ 909 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); 910 if (ret) { 911 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 912 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); 913 ovl_adaptor_comp_added = true; 914 } else { 915 if (next) 916 dev_err(dev, "Invalid component %pOF\n", next); 917 else 918 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath); 919 920 return ret; 921 } 922 } 923 idx++; 924 925 /* 926 * Walk through port outputs until we reach the last valid mediatek-drm component. 927 * To be valid, this must end with an "invalid" component that is a display node. 928 */ 929 do { 930 prev = next; 931 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]); 932 of_node_put(prev); 933 if (ret) { 934 of_node_put(next); 935 break; 936 } 937 938 /* 939 * If this is an OVL adaptor exclusive component and one of those 940 * was already added, don't add another instance of the generic 941 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether 942 * to probe that component master driver of which only one instance 943 * is needed and possible. 944 */ 945 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 946 if (!ovl_adaptor_comp_added) 947 ovl_adaptor_comp_added = true; 948 else 949 idx--; 950 } 951 } while (++idx < DDP_COMPONENT_DRM_ID_MAX); 952 953 /* 954 * The device component might not be enabled: in that case, don't 955 * check the last entry and just report that the device is missing. 956 */ 957 if (ret == -ENODEV) 958 return ret; 959 960 /* If the last entry is not a final display output, the configuration is wrong */ 961 switch (temp_path[idx - 1]) { 962 case DDP_COMPONENT_DP_INTF0: 963 case DDP_COMPONENT_DP_INTF1: 964 case DDP_COMPONENT_DPI0: 965 case DDP_COMPONENT_DPI1: 966 case DDP_COMPONENT_DSI0: 967 case DDP_COMPONENT_DSI1: 968 case DDP_COMPONENT_DSI2: 969 case DDP_COMPONENT_DSI3: 970 break; 971 default: 972 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n", 973 temp_path[idx - 1], ret); 974 return -EINVAL; 975 } 976 977 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL); 978 if (!final_ddp_path) 979 return -ENOMEM; 980 981 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx); 982 983 /* Pipeline built! */ 984 *out_path = final_ddp_path; 985 *out_path_len = idx; 986 987 return 0; 988 } 989 990 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node, 991 struct mtk_mmsys_driver_data *data) 992 { 993 struct device_node *ep_node; 994 struct of_endpoint of_ep; 995 bool output_present[MAX_CRTC] = { false }; 996 int ret; 997 998 for_each_endpoint_of_node(node, ep_node) { 999 ret = of_graph_parse_endpoint(ep_node, &of_ep); 1000 if (ret) { 1001 dev_err_probe(dev, ret, "Cannot parse endpoint\n"); 1002 break; 1003 } 1004 1005 if (of_ep.id >= MAX_CRTC) { 1006 ret = dev_err_probe(dev, -EINVAL, 1007 "Invalid endpoint%u number\n", of_ep.port); 1008 break; 1009 } 1010 1011 output_present[of_ep.id] = true; 1012 } 1013 1014 if (ret) { 1015 of_node_put(ep_node); 1016 return ret; 1017 } 1018 1019 if (output_present[CRTC_MAIN]) { 1020 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN, 1021 &data->main_path, &data->main_len); 1022 if (ret && ret != -ENODEV) 1023 return ret; 1024 } 1025 1026 if (output_present[CRTC_EXT]) { 1027 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT, 1028 &data->ext_path, &data->ext_len); 1029 if (ret && ret != -ENODEV) 1030 return ret; 1031 } 1032 1033 if (output_present[CRTC_THIRD]) { 1034 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD, 1035 &data->third_path, &data->third_len); 1036 if (ret && ret != -ENODEV) 1037 return ret; 1038 } 1039 1040 return 0; 1041 } 1042 1043 static int mtk_drm_probe(struct platform_device *pdev) 1044 { 1045 struct device *dev = &pdev->dev; 1046 struct device_node *phandle = dev->parent->of_node; 1047 const struct of_device_id *of_id; 1048 struct mtk_drm_private *private; 1049 struct mtk_mmsys_driver_data *mtk_drm_data; 1050 struct device_node *node; 1051 struct component_match *match = NULL; 1052 struct platform_device *ovl_adaptor; 1053 int ret; 1054 int i; 1055 1056 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 1057 if (!private) 1058 return -ENOMEM; 1059 1060 private->mmsys_dev = dev->parent; 1061 if (!private->mmsys_dev) { 1062 dev_err(dev, "Failed to get MMSYS device\n"); 1063 return -ENODEV; 1064 } 1065 1066 of_id = of_match_node(mtk_drm_of_ids, phandle); 1067 if (!of_id) 1068 return -ENODEV; 1069 1070 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data; 1071 if (!mtk_drm_data) 1072 return -EINVAL; 1073 1074 /* Try to build the display pipeline from devicetree graphs */ 1075 if (of_graph_is_present(phandle)) { 1076 dev_dbg(dev, "Building display pipeline for MMSYS %u\n", 1077 mtk_drm_data->mmsys_id); 1078 private->data = devm_kmemdup(dev, mtk_drm_data, 1079 sizeof(*mtk_drm_data), GFP_KERNEL); 1080 if (!private->data) 1081 return -ENOMEM; 1082 1083 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data); 1084 if (ret) 1085 return ret; 1086 } else { 1087 /* No devicetree graphs support: go with hardcoded paths if present */ 1088 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id); 1089 private->data = mtk_drm_data; 1090 }; 1091 1092 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 1093 sizeof(*private->all_drm_private), 1094 GFP_KERNEL); 1095 if (!private->all_drm_private) 1096 return -ENOMEM; 1097 1098 /* Bringup ovl_adaptor */ 1099 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 1100 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 1101 PLATFORM_DEVID_AUTO, 1102 (void *)private->mmsys_dev, 1103 sizeof(*private->mmsys_dev)); 1104 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 1105 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 1106 DDP_COMPONENT_DRM_OVL_ADAPTOR); 1107 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 1108 } 1109 1110 /* Iterate over sibling DISP function blocks */ 1111 for_each_child_of_node(phandle->parent, node) { 1112 enum mtk_ddp_comp_type comp_type; 1113 int comp_id; 1114 1115 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type); 1116 if (ret) 1117 continue; 1118 1119 if (!of_device_is_available(node)) { 1120 dev_dbg(dev, "Skipping disabled component %pOF\n", 1121 node); 1122 continue; 1123 } 1124 1125 if (comp_type == MTK_DISP_MUTEX) { 1126 int id; 1127 1128 id = of_alias_get_id(node, "mutex"); 1129 if (id < 0 || id == private->data->mmsys_id) { 1130 private->mutex_node = of_node_get(node); 1131 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 1132 } 1133 continue; 1134 } 1135 1136 comp_id = mtk_ddp_comp_get_id(node, comp_type); 1137 if (comp_id < 0) { 1138 dev_warn(dev, "Skipping unknown component %pOF\n", 1139 node); 1140 continue; 1141 } 1142 1143 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 1144 continue; 1145 1146 private->comp_node[comp_id] = of_node_get(node); 1147 1148 /* 1149 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 1150 * blocks have separate component platform drivers and initialize their own 1151 * DDP component structure. The others are initialized here. 1152 */ 1153 if (comp_type == MTK_DISP_AAL || 1154 comp_type == MTK_DISP_CCORR || 1155 comp_type == MTK_DISP_COLOR || 1156 comp_type == MTK_DISP_GAMMA || 1157 comp_type == MTK_DISP_MERGE || 1158 comp_type == MTK_DISP_OVL || 1159 comp_type == MTK_DISP_OVL_2L || 1160 comp_type == MTK_DISP_OVL_ADAPTOR || 1161 comp_type == MTK_DISP_RDMA || 1162 comp_type == MTK_DP_INTF || 1163 comp_type == MTK_DPI || 1164 comp_type == MTK_DSI) { 1165 dev_info(dev, "Adding component match for %pOF\n", 1166 node); 1167 drm_of_component_match_add(dev, &match, component_compare_of, 1168 node); 1169 } 1170 1171 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 1172 if (ret) { 1173 of_node_put(node); 1174 goto err_node; 1175 } 1176 } 1177 1178 if (!private->mutex_node) { 1179 dev_err(dev, "Failed to find disp-mutex node\n"); 1180 ret = -ENODEV; 1181 goto err_node; 1182 } 1183 1184 pm_runtime_enable(dev); 1185 1186 platform_set_drvdata(pdev, private); 1187 1188 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 1189 if (ret) 1190 goto err_pm; 1191 1192 return 0; 1193 1194 err_pm: 1195 pm_runtime_disable(dev); 1196 err_node: 1197 of_node_put(private->mutex_node); 1198 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1199 of_node_put(private->comp_node[i]); 1200 return ret; 1201 } 1202 1203 static void mtk_drm_remove(struct platform_device *pdev) 1204 { 1205 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1206 int i; 1207 1208 component_master_del(&pdev->dev, &mtk_drm_ops); 1209 pm_runtime_disable(&pdev->dev); 1210 of_node_put(private->mutex_node); 1211 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1212 of_node_put(private->comp_node[i]); 1213 } 1214 1215 static void mtk_drm_shutdown(struct platform_device *pdev) 1216 { 1217 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1218 1219 drm_atomic_helper_shutdown(private->drm); 1220 } 1221 1222 static int mtk_drm_sys_prepare(struct device *dev) 1223 { 1224 struct mtk_drm_private *private = dev_get_drvdata(dev); 1225 struct drm_device *drm = private->drm; 1226 1227 if (private->drm_master) 1228 return drm_mode_config_helper_suspend(drm); 1229 else 1230 return 0; 1231 } 1232 1233 static void mtk_drm_sys_complete(struct device *dev) 1234 { 1235 struct mtk_drm_private *private = dev_get_drvdata(dev); 1236 struct drm_device *drm = private->drm; 1237 int ret = 0; 1238 1239 if (private->drm_master) 1240 ret = drm_mode_config_helper_resume(drm); 1241 if (ret) 1242 dev_err(dev, "Failed to resume\n"); 1243 } 1244 1245 static const struct dev_pm_ops mtk_drm_pm_ops = { 1246 .prepare = mtk_drm_sys_prepare, 1247 .complete = mtk_drm_sys_complete, 1248 }; 1249 1250 static struct platform_driver mtk_drm_platform_driver = { 1251 .probe = mtk_drm_probe, 1252 .remove = mtk_drm_remove, 1253 .shutdown = mtk_drm_shutdown, 1254 .driver = { 1255 .name = "mediatek-drm", 1256 .pm = &mtk_drm_pm_ops, 1257 }, 1258 }; 1259 1260 static struct platform_driver * const mtk_drm_drivers[] = { 1261 &mtk_disp_aal_driver, 1262 &mtk_disp_ccorr_driver, 1263 &mtk_disp_color_driver, 1264 &mtk_disp_gamma_driver, 1265 &mtk_disp_merge_driver, 1266 &mtk_disp_ovl_adaptor_driver, 1267 &mtk_disp_ovl_driver, 1268 &mtk_disp_rdma_driver, 1269 &mtk_dpi_driver, 1270 &mtk_drm_platform_driver, 1271 &mtk_dsi_driver, 1272 &mtk_ethdr_driver, 1273 &mtk_mdp_rdma_driver, 1274 &mtk_padding_driver, 1275 }; 1276 1277 static int __init mtk_drm_init(void) 1278 { 1279 return platform_register_drivers(mtk_drm_drivers, 1280 ARRAY_SIZE(mtk_drm_drivers)); 1281 } 1282 1283 static void __exit mtk_drm_exit(void) 1284 { 1285 platform_unregister_drivers(mtk_drm_drivers, 1286 ARRAY_SIZE(mtk_drm_drivers)); 1287 } 1288 1289 module_init(mtk_drm_init); 1290 module_exit(mtk_drm_exit); 1291 1292 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1293 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1294 MODULE_LICENSE("GPL v2"); 1295