1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_client_setup.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_crtc.h" 29 #include "mtk_ddp_comp.h" 30 #include "mtk_disp_drv.h" 31 #include "mtk_drm_drv.h" 32 #include "mtk_gem.h" 33 34 #define DRIVER_NAME "mediatek" 35 #define DRIVER_DESC "Mediatek SoC DRM" 36 #define DRIVER_DATE "20150513" 37 #define DRIVER_MAJOR 1 38 #define DRIVER_MINOR 0 39 40 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 41 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 42 }; 43 44 static struct drm_framebuffer * 45 mtk_drm_mode_fb_create(struct drm_device *dev, 46 struct drm_file *file, 47 const struct drm_mode_fb_cmd2 *cmd) 48 { 49 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 50 51 if (info->num_planes != 1) 52 return ERR_PTR(-EINVAL); 53 54 return drm_gem_fb_create(dev, file, cmd); 55 } 56 57 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 58 .fb_create = mtk_drm_mode_fb_create, 59 .atomic_check = drm_atomic_helper_check, 60 .atomic_commit = drm_atomic_helper_commit, 61 }; 62 63 static const unsigned int mt2701_mtk_ddp_main[] = { 64 DDP_COMPONENT_OVL0, 65 DDP_COMPONENT_RDMA0, 66 DDP_COMPONENT_COLOR0, 67 DDP_COMPONENT_BLS, 68 DDP_COMPONENT_DSI0, 69 }; 70 71 static const unsigned int mt2701_mtk_ddp_ext[] = { 72 DDP_COMPONENT_RDMA1, 73 DDP_COMPONENT_DPI0, 74 }; 75 76 static const unsigned int mt7623_mtk_ddp_main[] = { 77 DDP_COMPONENT_OVL0, 78 DDP_COMPONENT_RDMA0, 79 DDP_COMPONENT_COLOR0, 80 DDP_COMPONENT_BLS, 81 DDP_COMPONENT_DPI0, 82 }; 83 84 static const unsigned int mt7623_mtk_ddp_ext[] = { 85 DDP_COMPONENT_RDMA1, 86 DDP_COMPONENT_DSI0, 87 }; 88 89 static const unsigned int mt2712_mtk_ddp_main[] = { 90 DDP_COMPONENT_OVL0, 91 DDP_COMPONENT_COLOR0, 92 DDP_COMPONENT_AAL0, 93 DDP_COMPONENT_OD0, 94 DDP_COMPONENT_RDMA0, 95 DDP_COMPONENT_DPI0, 96 DDP_COMPONENT_PWM0, 97 }; 98 99 static const unsigned int mt2712_mtk_ddp_ext[] = { 100 DDP_COMPONENT_OVL1, 101 DDP_COMPONENT_COLOR1, 102 DDP_COMPONENT_AAL1, 103 DDP_COMPONENT_OD1, 104 DDP_COMPONENT_RDMA1, 105 DDP_COMPONENT_DPI1, 106 DDP_COMPONENT_PWM1, 107 }; 108 109 static const unsigned int mt2712_mtk_ddp_third[] = { 110 DDP_COMPONENT_RDMA2, 111 DDP_COMPONENT_DSI3, 112 DDP_COMPONENT_PWM2, 113 }; 114 115 static unsigned int mt8167_mtk_ddp_main[] = { 116 DDP_COMPONENT_OVL0, 117 DDP_COMPONENT_COLOR0, 118 DDP_COMPONENT_CCORR, 119 DDP_COMPONENT_AAL0, 120 DDP_COMPONENT_GAMMA, 121 DDP_COMPONENT_DITHER0, 122 DDP_COMPONENT_RDMA0, 123 DDP_COMPONENT_DSI0, 124 }; 125 126 static const unsigned int mt8173_mtk_ddp_main[] = { 127 DDP_COMPONENT_OVL0, 128 DDP_COMPONENT_COLOR0, 129 DDP_COMPONENT_AAL0, 130 DDP_COMPONENT_OD0, 131 DDP_COMPONENT_RDMA0, 132 DDP_COMPONENT_UFOE, 133 DDP_COMPONENT_DSI0, 134 DDP_COMPONENT_PWM0, 135 }; 136 137 static const unsigned int mt8173_mtk_ddp_ext[] = { 138 DDP_COMPONENT_OVL1, 139 DDP_COMPONENT_COLOR1, 140 DDP_COMPONENT_GAMMA, 141 DDP_COMPONENT_RDMA1, 142 DDP_COMPONENT_DPI0, 143 }; 144 145 static const unsigned int mt8183_mtk_ddp_main[] = { 146 DDP_COMPONENT_OVL0, 147 DDP_COMPONENT_OVL_2L0, 148 DDP_COMPONENT_RDMA0, 149 DDP_COMPONENT_COLOR0, 150 DDP_COMPONENT_CCORR, 151 DDP_COMPONENT_AAL0, 152 DDP_COMPONENT_GAMMA, 153 DDP_COMPONENT_DITHER0, 154 DDP_COMPONENT_DSI0, 155 }; 156 157 static const unsigned int mt8183_mtk_ddp_ext[] = { 158 DDP_COMPONENT_OVL_2L1, 159 DDP_COMPONENT_RDMA1, 160 DDP_COMPONENT_DPI0, 161 }; 162 163 static const unsigned int mt8186_mtk_ddp_main[] = { 164 DDP_COMPONENT_OVL0, 165 DDP_COMPONENT_RDMA0, 166 DDP_COMPONENT_COLOR0, 167 DDP_COMPONENT_CCORR, 168 DDP_COMPONENT_AAL0, 169 DDP_COMPONENT_GAMMA, 170 DDP_COMPONENT_POSTMASK0, 171 DDP_COMPONENT_DITHER0, 172 DDP_COMPONENT_DSI0, 173 }; 174 175 static const unsigned int mt8186_mtk_ddp_ext[] = { 176 DDP_COMPONENT_OVL_2L0, 177 DDP_COMPONENT_RDMA1, 178 DDP_COMPONENT_DPI0, 179 }; 180 181 static const unsigned int mt8188_mtk_ddp_main[] = { 182 DDP_COMPONENT_OVL0, 183 DDP_COMPONENT_RDMA0, 184 DDP_COMPONENT_COLOR0, 185 DDP_COMPONENT_CCORR, 186 DDP_COMPONENT_AAL0, 187 DDP_COMPONENT_GAMMA, 188 DDP_COMPONENT_POSTMASK0, 189 DDP_COMPONENT_DITHER0, 190 }; 191 192 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 193 {0, DDP_COMPONENT_DP_INTF0}, 194 {0, DDP_COMPONENT_DSI0}, 195 }; 196 197 static const unsigned int mt8192_mtk_ddp_main[] = { 198 DDP_COMPONENT_OVL0, 199 DDP_COMPONENT_OVL_2L0, 200 DDP_COMPONENT_RDMA0, 201 DDP_COMPONENT_COLOR0, 202 DDP_COMPONENT_CCORR, 203 DDP_COMPONENT_AAL0, 204 DDP_COMPONENT_GAMMA, 205 DDP_COMPONENT_POSTMASK0, 206 DDP_COMPONENT_DITHER0, 207 DDP_COMPONENT_DSI0, 208 }; 209 210 static const unsigned int mt8192_mtk_ddp_ext[] = { 211 DDP_COMPONENT_OVL_2L2, 212 DDP_COMPONENT_RDMA4, 213 DDP_COMPONENT_DPI0, 214 }; 215 216 static const unsigned int mt8195_mtk_ddp_main[] = { 217 DDP_COMPONENT_OVL0, 218 DDP_COMPONENT_RDMA0, 219 DDP_COMPONENT_COLOR0, 220 DDP_COMPONENT_CCORR, 221 DDP_COMPONENT_AAL0, 222 DDP_COMPONENT_GAMMA, 223 DDP_COMPONENT_DITHER0, 224 DDP_COMPONENT_DSC0, 225 DDP_COMPONENT_MERGE0, 226 DDP_COMPONENT_DP_INTF0, 227 }; 228 229 static const unsigned int mt8195_mtk_ddp_ext[] = { 230 DDP_COMPONENT_DRM_OVL_ADAPTOR, 231 DDP_COMPONENT_MERGE5, 232 DDP_COMPONENT_DP_INTF1, 233 }; 234 235 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 236 .main_path = mt2701_mtk_ddp_main, 237 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 238 .ext_path = mt2701_mtk_ddp_ext, 239 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 240 .shadow_register = true, 241 .mmsys_dev_num = 1, 242 }; 243 244 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 245 .main_path = mt7623_mtk_ddp_main, 246 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 247 .ext_path = mt7623_mtk_ddp_ext, 248 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 249 .shadow_register = true, 250 .mmsys_dev_num = 1, 251 }; 252 253 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 254 .main_path = mt2712_mtk_ddp_main, 255 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 256 .ext_path = mt2712_mtk_ddp_ext, 257 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 258 .third_path = mt2712_mtk_ddp_third, 259 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 260 .mmsys_dev_num = 1, 261 }; 262 263 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 264 .main_path = mt8167_mtk_ddp_main, 265 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 266 .mmsys_dev_num = 1, 267 }; 268 269 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 270 .main_path = mt8173_mtk_ddp_main, 271 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 272 .ext_path = mt8173_mtk_ddp_ext, 273 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 274 .mmsys_dev_num = 1, 275 }; 276 277 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 278 .main_path = mt8183_mtk_ddp_main, 279 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 280 .ext_path = mt8183_mtk_ddp_ext, 281 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 282 .mmsys_dev_num = 1, 283 }; 284 285 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 286 .main_path = mt8186_mtk_ddp_main, 287 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 288 .ext_path = mt8186_mtk_ddp_ext, 289 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 290 .mmsys_dev_num = 1, 291 }; 292 293 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 294 .main_path = mt8188_mtk_ddp_main, 295 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 296 .conn_routes = mt8188_mtk_ddp_main_routes, 297 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 298 .mmsys_dev_num = 2, 299 .max_width = 8191, 300 .min_width = 1, 301 .min_height = 1, 302 }; 303 304 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 305 .main_path = mt8192_mtk_ddp_main, 306 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 307 .ext_path = mt8192_mtk_ddp_ext, 308 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 309 .mmsys_dev_num = 1, 310 }; 311 312 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 313 .main_path = mt8195_mtk_ddp_main, 314 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 315 .mmsys_dev_num = 2, 316 .max_width = 8191, 317 .min_width = 1, 318 .min_height = 1, 319 }; 320 321 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 322 .ext_path = mt8195_mtk_ddp_ext, 323 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 324 .mmsys_id = 1, 325 .mmsys_dev_num = 2, 326 .max_width = 8191, 327 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 328 .min_height = 1, 329 }; 330 331 static const struct of_device_id mtk_drm_of_ids[] = { 332 { .compatible = "mediatek,mt2701-mmsys", 333 .data = &mt2701_mmsys_driver_data}, 334 { .compatible = "mediatek,mt7623-mmsys", 335 .data = &mt7623_mmsys_driver_data}, 336 { .compatible = "mediatek,mt2712-mmsys", 337 .data = &mt2712_mmsys_driver_data}, 338 { .compatible = "mediatek,mt8167-mmsys", 339 .data = &mt8167_mmsys_driver_data}, 340 { .compatible = "mediatek,mt8173-mmsys", 341 .data = &mt8173_mmsys_driver_data}, 342 { .compatible = "mediatek,mt8183-mmsys", 343 .data = &mt8183_mmsys_driver_data}, 344 { .compatible = "mediatek,mt8186-mmsys", 345 .data = &mt8186_mmsys_driver_data}, 346 { .compatible = "mediatek,mt8188-vdosys0", 347 .data = &mt8188_vdosys0_driver_data}, 348 { .compatible = "mediatek,mt8188-vdosys1", 349 .data = &mt8195_vdosys1_driver_data}, 350 { .compatible = "mediatek,mt8192-mmsys", 351 .data = &mt8192_mmsys_driver_data}, 352 { .compatible = "mediatek,mt8195-mmsys", 353 .data = &mt8195_vdosys0_driver_data}, 354 { .compatible = "mediatek,mt8195-vdosys0", 355 .data = &mt8195_vdosys0_driver_data}, 356 { .compatible = "mediatek,mt8195-vdosys1", 357 .data = &mt8195_vdosys1_driver_data}, 358 { } 359 }; 360 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 361 362 static int mtk_drm_match(struct device *dev, void *data) 363 { 364 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 365 return true; 366 return false; 367 } 368 369 static bool mtk_drm_get_all_drm_priv(struct device *dev) 370 { 371 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 372 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 373 struct mtk_drm_private *temp_drm_priv; 374 struct device_node *phandle = dev->parent->of_node; 375 const struct of_device_id *of_id; 376 struct device *drm_dev; 377 unsigned int cnt = 0; 378 int i, j; 379 380 for_each_child_of_node_scoped(phandle->parent, node) { 381 struct platform_device *pdev; 382 383 of_id = of_match_node(mtk_drm_of_ids, node); 384 if (!of_id) 385 continue; 386 387 pdev = of_find_device_by_node(node); 388 if (!pdev) 389 continue; 390 391 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 392 if (!drm_dev) 393 continue; 394 395 temp_drm_priv = dev_get_drvdata(drm_dev); 396 if (!temp_drm_priv) 397 continue; 398 399 if (temp_drm_priv->data->main_len) 400 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 401 else if (temp_drm_priv->data->ext_len) 402 all_drm_priv[CRTC_EXT] = temp_drm_priv; 403 else if (temp_drm_priv->data->third_len) 404 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 405 406 if (temp_drm_priv->mtk_drm_bound) 407 cnt++; 408 409 if (cnt == MAX_CRTC) 410 break; 411 } 412 413 if (drm_priv->data->mmsys_dev_num == cnt) { 414 for (i = 0; i < cnt; i++) 415 for (j = 0; j < cnt; j++) 416 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 417 418 return true; 419 } 420 421 return false; 422 } 423 424 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 425 { 426 const struct mtk_mmsys_driver_data *drv_data = private->data; 427 int i; 428 429 if (drv_data->main_path) 430 for (i = 0; i < drv_data->main_len; i++) 431 if (drv_data->main_path[i] == comp_id) 432 return true; 433 434 if (drv_data->ext_path) 435 for (i = 0; i < drv_data->ext_len; i++) 436 if (drv_data->ext_path[i] == comp_id) 437 return true; 438 439 if (drv_data->third_path) 440 for (i = 0; i < drv_data->third_len; i++) 441 if (drv_data->third_path[i] == comp_id) 442 return true; 443 444 if (drv_data->num_conn_routes) 445 for (i = 0; i < drv_data->num_conn_routes; i++) 446 if (drv_data->conn_routes[i].route_ddp == comp_id) 447 return true; 448 449 return false; 450 } 451 452 static int mtk_drm_kms_init(struct drm_device *drm) 453 { 454 struct mtk_drm_private *private = drm->dev_private; 455 struct mtk_drm_private *priv_n; 456 struct device *dma_dev = NULL; 457 struct drm_crtc *crtc; 458 int ret, i, j; 459 460 if (drm_firmware_drivers_only()) 461 return -ENODEV; 462 463 ret = drmm_mode_config_init(drm); 464 if (ret) 465 goto put_mutex_dev; 466 467 drm->mode_config.min_width = 64; 468 drm->mode_config.min_height = 64; 469 470 /* 471 * set max width and height as default value(4096x4096). 472 * this value would be used to check framebuffer size limitation 473 * at drm_mode_addfb(). 474 */ 475 drm->mode_config.max_width = 4096; 476 drm->mode_config.max_height = 4096; 477 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 478 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 479 480 for (i = 0; i < private->data->mmsys_dev_num; i++) { 481 drm->dev_private = private->all_drm_private[i]; 482 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 483 if (ret) 484 goto put_mutex_dev; 485 } 486 487 /* 488 * Ensure internal panels are at the top of the connector list before 489 * crtc creation. 490 */ 491 drm_helper_move_panel_connectors_to_head(drm); 492 493 /* 494 * 1. We currently support two fixed data streams, each optional, 495 * and each statically assigned to a crtc: 496 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 497 * 2. For multi mmsys architecture, crtc path data are located in 498 * different drm private data structures. Loop through crtc index to 499 * create crtc from the main path and then ext_path and finally the 500 * third path. 501 */ 502 for (i = 0; i < MAX_CRTC; i++) { 503 for (j = 0; j < private->data->mmsys_dev_num; j++) { 504 priv_n = private->all_drm_private[j]; 505 506 if (priv_n->data->max_width) 507 drm->mode_config.max_width = priv_n->data->max_width; 508 509 if (priv_n->data->min_width) 510 drm->mode_config.min_width = priv_n->data->min_width; 511 512 if (priv_n->data->min_height) 513 drm->mode_config.min_height = priv_n->data->min_height; 514 515 if (i == CRTC_MAIN && priv_n->data->main_len) { 516 ret = mtk_crtc_create(drm, priv_n->data->main_path, 517 priv_n->data->main_len, j, 518 priv_n->data->conn_routes, 519 priv_n->data->num_conn_routes); 520 if (ret) 521 goto err_component_unbind; 522 523 continue; 524 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 525 ret = mtk_crtc_create(drm, priv_n->data->ext_path, 526 priv_n->data->ext_len, j, NULL, 0); 527 if (ret) 528 goto err_component_unbind; 529 530 continue; 531 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 532 ret = mtk_crtc_create(drm, priv_n->data->third_path, 533 priv_n->data->third_len, j, NULL, 0); 534 if (ret) 535 goto err_component_unbind; 536 537 continue; 538 } 539 } 540 } 541 542 /* IGT will check if the cursor size is configured */ 543 drm->mode_config.cursor_width = 512; 544 drm->mode_config.cursor_height = 512; 545 546 /* Use OVL device for all DMA memory allocations */ 547 crtc = drm_crtc_from_index(drm, 0); 548 if (crtc) 549 dma_dev = mtk_crtc_dma_dev_get(crtc); 550 if (!dma_dev) { 551 ret = -ENODEV; 552 dev_err(drm->dev, "Need at least one OVL device\n"); 553 goto err_component_unbind; 554 } 555 556 for (i = 0; i < private->data->mmsys_dev_num; i++) 557 private->all_drm_private[i]->dma_dev = dma_dev; 558 559 /* 560 * Configure the DMA segment size to make sure we get contiguous IOVA 561 * when importing PRIME buffers. 562 */ 563 dma_set_max_seg_size(dma_dev, UINT_MAX); 564 565 ret = drm_vblank_init(drm, MAX_CRTC); 566 if (ret < 0) 567 goto err_component_unbind; 568 569 drm_kms_helper_poll_init(drm); 570 drm_mode_config_reset(drm); 571 572 return 0; 573 574 err_component_unbind: 575 for (i = 0; i < private->data->mmsys_dev_num; i++) 576 component_unbind_all(private->all_drm_private[i]->dev, drm); 577 put_mutex_dev: 578 for (i = 0; i < private->data->mmsys_dev_num; i++) 579 put_device(private->all_drm_private[i]->mutex_dev); 580 581 return ret; 582 } 583 584 static void mtk_drm_kms_deinit(struct drm_device *drm) 585 { 586 drm_kms_helper_poll_fini(drm); 587 drm_atomic_helper_shutdown(drm); 588 589 component_unbind_all(drm->dev, drm); 590 } 591 592 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 593 594 /* 595 * We need to override this because the device used to import the memory is 596 * not dev->dev, as drm_gem_prime_import() expects. 597 */ 598 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev, 599 struct dma_buf *dma_buf) 600 { 601 struct mtk_drm_private *private = dev->dev_private; 602 603 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 604 } 605 606 static const struct drm_driver mtk_drm_driver = { 607 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 608 609 .dumb_create = mtk_gem_dumb_create, 610 DRM_FBDEV_DMA_DRIVER_OPS, 611 612 .gem_prime_import = mtk_gem_prime_import, 613 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 614 .fops = &mtk_drm_fops, 615 616 .name = DRIVER_NAME, 617 .desc = DRIVER_DESC, 618 .date = DRIVER_DATE, 619 .major = DRIVER_MAJOR, 620 .minor = DRIVER_MINOR, 621 }; 622 623 static int compare_dev(struct device *dev, void *data) 624 { 625 return dev == (struct device *)data; 626 } 627 628 static int mtk_drm_bind(struct device *dev) 629 { 630 struct mtk_drm_private *private = dev_get_drvdata(dev); 631 struct platform_device *pdev; 632 struct drm_device *drm; 633 int ret, i; 634 635 pdev = of_find_device_by_node(private->mutex_node); 636 if (!pdev) { 637 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 638 private->mutex_node); 639 of_node_put(private->mutex_node); 640 return -EPROBE_DEFER; 641 } 642 643 private->mutex_dev = &pdev->dev; 644 private->mtk_drm_bound = true; 645 private->dev = dev; 646 647 if (!mtk_drm_get_all_drm_priv(dev)) 648 return 0; 649 650 drm = drm_dev_alloc(&mtk_drm_driver, dev); 651 if (IS_ERR(drm)) 652 return PTR_ERR(drm); 653 654 private->drm_master = true; 655 drm->dev_private = private; 656 for (i = 0; i < private->data->mmsys_dev_num; i++) 657 private->all_drm_private[i]->drm = drm; 658 659 ret = mtk_drm_kms_init(drm); 660 if (ret < 0) 661 goto err_free; 662 663 ret = drm_dev_register(drm, 0); 664 if (ret < 0) 665 goto err_deinit; 666 667 drm_client_setup(drm, NULL); 668 669 return 0; 670 671 err_deinit: 672 mtk_drm_kms_deinit(drm); 673 err_free: 674 private->drm = NULL; 675 drm_dev_put(drm); 676 return ret; 677 } 678 679 static void mtk_drm_unbind(struct device *dev) 680 { 681 struct mtk_drm_private *private = dev_get_drvdata(dev); 682 683 /* for multi mmsys dev, unregister drm dev in mmsys master */ 684 if (private->drm_master) { 685 drm_dev_unregister(private->drm); 686 mtk_drm_kms_deinit(private->drm); 687 drm_dev_put(private->drm); 688 } 689 private->mtk_drm_bound = false; 690 private->drm_master = false; 691 private->drm = NULL; 692 } 693 694 static const struct component_master_ops mtk_drm_ops = { 695 .bind = mtk_drm_bind, 696 .unbind = mtk_drm_unbind, 697 }; 698 699 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 700 { .compatible = "mediatek,mt8167-disp-aal", 701 .data = (void *)MTK_DISP_AAL}, 702 { .compatible = "mediatek,mt8173-disp-aal", 703 .data = (void *)MTK_DISP_AAL}, 704 { .compatible = "mediatek,mt8183-disp-aal", 705 .data = (void *)MTK_DISP_AAL}, 706 { .compatible = "mediatek,mt8192-disp-aal", 707 .data = (void *)MTK_DISP_AAL}, 708 { .compatible = "mediatek,mt8167-disp-ccorr", 709 .data = (void *)MTK_DISP_CCORR }, 710 { .compatible = "mediatek,mt8183-disp-ccorr", 711 .data = (void *)MTK_DISP_CCORR }, 712 { .compatible = "mediatek,mt8192-disp-ccorr", 713 .data = (void *)MTK_DISP_CCORR }, 714 { .compatible = "mediatek,mt2701-disp-color", 715 .data = (void *)MTK_DISP_COLOR }, 716 { .compatible = "mediatek,mt8167-disp-color", 717 .data = (void *)MTK_DISP_COLOR }, 718 { .compatible = "mediatek,mt8173-disp-color", 719 .data = (void *)MTK_DISP_COLOR }, 720 { .compatible = "mediatek,mt8167-disp-dither", 721 .data = (void *)MTK_DISP_DITHER }, 722 { .compatible = "mediatek,mt8183-disp-dither", 723 .data = (void *)MTK_DISP_DITHER }, 724 { .compatible = "mediatek,mt8195-disp-dsc", 725 .data = (void *)MTK_DISP_DSC }, 726 { .compatible = "mediatek,mt8167-disp-gamma", 727 .data = (void *)MTK_DISP_GAMMA, }, 728 { .compatible = "mediatek,mt8173-disp-gamma", 729 .data = (void *)MTK_DISP_GAMMA, }, 730 { .compatible = "mediatek,mt8183-disp-gamma", 731 .data = (void *)MTK_DISP_GAMMA, }, 732 { .compatible = "mediatek,mt8195-disp-gamma", 733 .data = (void *)MTK_DISP_GAMMA, }, 734 { .compatible = "mediatek,mt8195-disp-merge", 735 .data = (void *)MTK_DISP_MERGE }, 736 { .compatible = "mediatek,mt2701-disp-mutex", 737 .data = (void *)MTK_DISP_MUTEX }, 738 { .compatible = "mediatek,mt2712-disp-mutex", 739 .data = (void *)MTK_DISP_MUTEX }, 740 { .compatible = "mediatek,mt8167-disp-mutex", 741 .data = (void *)MTK_DISP_MUTEX }, 742 { .compatible = "mediatek,mt8173-disp-mutex", 743 .data = (void *)MTK_DISP_MUTEX }, 744 { .compatible = "mediatek,mt8183-disp-mutex", 745 .data = (void *)MTK_DISP_MUTEX }, 746 { .compatible = "mediatek,mt8186-disp-mutex", 747 .data = (void *)MTK_DISP_MUTEX }, 748 { .compatible = "mediatek,mt8188-disp-mutex", 749 .data = (void *)MTK_DISP_MUTEX }, 750 { .compatible = "mediatek,mt8192-disp-mutex", 751 .data = (void *)MTK_DISP_MUTEX }, 752 { .compatible = "mediatek,mt8195-disp-mutex", 753 .data = (void *)MTK_DISP_MUTEX }, 754 { .compatible = "mediatek,mt8173-disp-od", 755 .data = (void *)MTK_DISP_OD }, 756 { .compatible = "mediatek,mt2701-disp-ovl", 757 .data = (void *)MTK_DISP_OVL }, 758 { .compatible = "mediatek,mt8167-disp-ovl", 759 .data = (void *)MTK_DISP_OVL }, 760 { .compatible = "mediatek,mt8173-disp-ovl", 761 .data = (void *)MTK_DISP_OVL }, 762 { .compatible = "mediatek,mt8183-disp-ovl", 763 .data = (void *)MTK_DISP_OVL }, 764 { .compatible = "mediatek,mt8192-disp-ovl", 765 .data = (void *)MTK_DISP_OVL }, 766 { .compatible = "mediatek,mt8195-disp-ovl", 767 .data = (void *)MTK_DISP_OVL }, 768 { .compatible = "mediatek,mt8183-disp-ovl-2l", 769 .data = (void *)MTK_DISP_OVL_2L }, 770 { .compatible = "mediatek,mt8192-disp-ovl-2l", 771 .data = (void *)MTK_DISP_OVL_2L }, 772 { .compatible = "mediatek,mt8192-disp-postmask", 773 .data = (void *)MTK_DISP_POSTMASK }, 774 { .compatible = "mediatek,mt2701-disp-pwm", 775 .data = (void *)MTK_DISP_BLS }, 776 { .compatible = "mediatek,mt8167-disp-pwm", 777 .data = (void *)MTK_DISP_PWM }, 778 { .compatible = "mediatek,mt8173-disp-pwm", 779 .data = (void *)MTK_DISP_PWM }, 780 { .compatible = "mediatek,mt2701-disp-rdma", 781 .data = (void *)MTK_DISP_RDMA }, 782 { .compatible = "mediatek,mt8167-disp-rdma", 783 .data = (void *)MTK_DISP_RDMA }, 784 { .compatible = "mediatek,mt8173-disp-rdma", 785 .data = (void *)MTK_DISP_RDMA }, 786 { .compatible = "mediatek,mt8183-disp-rdma", 787 .data = (void *)MTK_DISP_RDMA }, 788 { .compatible = "mediatek,mt8195-disp-rdma", 789 .data = (void *)MTK_DISP_RDMA }, 790 { .compatible = "mediatek,mt8173-disp-ufoe", 791 .data = (void *)MTK_DISP_UFOE }, 792 { .compatible = "mediatek,mt8173-disp-wdma", 793 .data = (void *)MTK_DISP_WDMA }, 794 { .compatible = "mediatek,mt2701-dpi", 795 .data = (void *)MTK_DPI }, 796 { .compatible = "mediatek,mt8167-dsi", 797 .data = (void *)MTK_DSI }, 798 { .compatible = "mediatek,mt8173-dpi", 799 .data = (void *)MTK_DPI }, 800 { .compatible = "mediatek,mt8183-dpi", 801 .data = (void *)MTK_DPI }, 802 { .compatible = "mediatek,mt8186-dpi", 803 .data = (void *)MTK_DPI }, 804 { .compatible = "mediatek,mt8188-dp-intf", 805 .data = (void *)MTK_DP_INTF }, 806 { .compatible = "mediatek,mt8192-dpi", 807 .data = (void *)MTK_DPI }, 808 { .compatible = "mediatek,mt8195-dp-intf", 809 .data = (void *)MTK_DP_INTF }, 810 { .compatible = "mediatek,mt2701-dsi", 811 .data = (void *)MTK_DSI }, 812 { .compatible = "mediatek,mt8173-dsi", 813 .data = (void *)MTK_DSI }, 814 { .compatible = "mediatek,mt8183-dsi", 815 .data = (void *)MTK_DSI }, 816 { .compatible = "mediatek,mt8186-dsi", 817 .data = (void *)MTK_DSI }, 818 { .compatible = "mediatek,mt8188-dsi", 819 .data = (void *)MTK_DSI }, 820 { } 821 }; 822 823 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype) 824 { 825 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 826 827 if (!of_id) 828 return -EINVAL; 829 830 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data); 831 832 return 0; 833 } 834 835 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, 836 int output_port, enum mtk_crtc_path crtc_path, 837 struct device_node **next, unsigned int *cid) 838 { 839 struct device_node *ep_dev_node, *ep_out; 840 enum mtk_ddp_comp_type comp_type; 841 int ret; 842 843 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path); 844 if (!ep_out) 845 return -ENOENT; 846 847 ep_dev_node = of_graph_get_remote_port_parent(ep_out); 848 of_node_put(ep_out); 849 if (!ep_dev_node) 850 return -EINVAL; 851 852 /* 853 * Pass the next node pointer regardless of failures in the later code 854 * so that if this function is called in a loop it will walk through all 855 * of the subsequent endpoints anyway. 856 */ 857 *next = ep_dev_node; 858 859 if (!of_device_is_available(ep_dev_node)) 860 return -ENODEV; 861 862 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); 863 if (ret) { 864 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { 865 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR; 866 return 0; 867 } 868 return ret; 869 } 870 871 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type); 872 if (ret < 0) 873 return ret; 874 875 /* All ok! Pass the Component ID to the caller. */ 876 *cid = (unsigned int)ret; 877 878 return 0; 879 } 880 881 /** 882 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path 883 * @dev: The mediatek-drm device 884 * @cpath: CRTC Path relative to a VDO or MMSYS 885 * @out_path: Pointer to an array that will contain the new pipeline 886 * @out_path_len: Number of entries in the pipeline array 887 * 888 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending 889 * on the board-specific desired display configuration; this function walks 890 * through all of the output endpoints starting from a VDO or MMSYS hardware 891 * instance and builds the right pipeline as specified in device trees. 892 * 893 * Return: 894 * * %0 - Display HW Pipeline successfully built and validated 895 * * %-ENOENT - Display pipeline was not specified in device tree 896 * * %-EINVAL - Display pipeline built but validation failed 897 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller 898 */ 899 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath, 900 const unsigned int **out_path, 901 unsigned int *out_path_len) 902 { 903 struct device_node *next, *prev, *vdo = dev->parent->of_node; 904 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 }; 905 unsigned int *final_ddp_path; 906 unsigned short int idx = 0; 907 bool ovl_adaptor_comp_added = false; 908 int ret; 909 910 /* Get the first entry for the temp_path array */ 911 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); 912 if (ret) { 913 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 914 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); 915 ovl_adaptor_comp_added = true; 916 } else { 917 if (next) 918 dev_err(dev, "Invalid component %pOF\n", next); 919 else 920 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath); 921 922 return ret; 923 } 924 } 925 idx++; 926 927 /* 928 * Walk through port outputs until we reach the last valid mediatek-drm component. 929 * To be valid, this must end with an "invalid" component that is a display node. 930 */ 931 do { 932 prev = next; 933 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]); 934 of_node_put(prev); 935 if (ret) { 936 of_node_put(next); 937 break; 938 } 939 940 /* 941 * If this is an OVL adaptor exclusive component and one of those 942 * was already added, don't add another instance of the generic 943 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether 944 * to probe that component master driver of which only one instance 945 * is needed and possible. 946 */ 947 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 948 if (!ovl_adaptor_comp_added) 949 ovl_adaptor_comp_added = true; 950 else 951 idx--; 952 } 953 } while (++idx < DDP_COMPONENT_DRM_ID_MAX); 954 955 /* 956 * The device component might not be enabled: in that case, don't 957 * check the last entry and just report that the device is missing. 958 */ 959 if (ret == -ENODEV) 960 return ret; 961 962 /* If the last entry is not a final display output, the configuration is wrong */ 963 switch (temp_path[idx - 1]) { 964 case DDP_COMPONENT_DP_INTF0: 965 case DDP_COMPONENT_DP_INTF1: 966 case DDP_COMPONENT_DPI0: 967 case DDP_COMPONENT_DPI1: 968 case DDP_COMPONENT_DSI0: 969 case DDP_COMPONENT_DSI1: 970 case DDP_COMPONENT_DSI2: 971 case DDP_COMPONENT_DSI3: 972 break; 973 default: 974 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n", 975 temp_path[idx - 1], ret); 976 return -EINVAL; 977 } 978 979 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL); 980 if (!final_ddp_path) 981 return -ENOMEM; 982 983 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx); 984 985 /* Pipeline built! */ 986 *out_path = final_ddp_path; 987 *out_path_len = idx; 988 989 return 0; 990 } 991 992 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node, 993 struct mtk_mmsys_driver_data *data) 994 { 995 struct device_node *ep_node; 996 struct of_endpoint of_ep; 997 bool output_present[MAX_CRTC] = { false }; 998 int ret; 999 1000 for_each_endpoint_of_node(node, ep_node) { 1001 ret = of_graph_parse_endpoint(ep_node, &of_ep); 1002 if (ret) { 1003 dev_err_probe(dev, ret, "Cannot parse endpoint\n"); 1004 break; 1005 } 1006 1007 if (of_ep.id >= MAX_CRTC) { 1008 ret = dev_err_probe(dev, -EINVAL, 1009 "Invalid endpoint%u number\n", of_ep.port); 1010 break; 1011 } 1012 1013 output_present[of_ep.id] = true; 1014 } 1015 1016 if (ret) { 1017 of_node_put(ep_node); 1018 return ret; 1019 } 1020 1021 if (output_present[CRTC_MAIN]) { 1022 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN, 1023 &data->main_path, &data->main_len); 1024 if (ret && ret != -ENODEV) 1025 return ret; 1026 } 1027 1028 if (output_present[CRTC_EXT]) { 1029 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT, 1030 &data->ext_path, &data->ext_len); 1031 if (ret && ret != -ENODEV) 1032 return ret; 1033 } 1034 1035 if (output_present[CRTC_THIRD]) { 1036 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD, 1037 &data->third_path, &data->third_len); 1038 if (ret && ret != -ENODEV) 1039 return ret; 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int mtk_drm_probe(struct platform_device *pdev) 1046 { 1047 struct device *dev = &pdev->dev; 1048 struct device_node *phandle = dev->parent->of_node; 1049 const struct of_device_id *of_id; 1050 struct mtk_drm_private *private; 1051 struct mtk_mmsys_driver_data *mtk_drm_data; 1052 struct device_node *node; 1053 struct component_match *match = NULL; 1054 struct platform_device *ovl_adaptor; 1055 int ret; 1056 int i; 1057 1058 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 1059 if (!private) 1060 return -ENOMEM; 1061 1062 private->mmsys_dev = dev->parent; 1063 if (!private->mmsys_dev) { 1064 dev_err(dev, "Failed to get MMSYS device\n"); 1065 return -ENODEV; 1066 } 1067 1068 of_id = of_match_node(mtk_drm_of_ids, phandle); 1069 if (!of_id) 1070 return -ENODEV; 1071 1072 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data; 1073 if (!mtk_drm_data) 1074 return -EINVAL; 1075 1076 /* Try to build the display pipeline from devicetree graphs */ 1077 if (of_graph_is_present(phandle)) { 1078 dev_dbg(dev, "Building display pipeline for MMSYS %u\n", 1079 mtk_drm_data->mmsys_id); 1080 private->data = devm_kmemdup(dev, mtk_drm_data, 1081 sizeof(*mtk_drm_data), GFP_KERNEL); 1082 if (!private->data) 1083 return -ENOMEM; 1084 1085 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data); 1086 if (ret) 1087 return ret; 1088 } else { 1089 /* No devicetree graphs support: go with hardcoded paths if present */ 1090 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id); 1091 private->data = mtk_drm_data; 1092 }; 1093 1094 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 1095 sizeof(*private->all_drm_private), 1096 GFP_KERNEL); 1097 if (!private->all_drm_private) 1098 return -ENOMEM; 1099 1100 /* Bringup ovl_adaptor */ 1101 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 1102 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 1103 PLATFORM_DEVID_AUTO, 1104 (void *)private->mmsys_dev, 1105 sizeof(*private->mmsys_dev)); 1106 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 1107 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 1108 DDP_COMPONENT_DRM_OVL_ADAPTOR); 1109 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 1110 } 1111 1112 /* Iterate over sibling DISP function blocks */ 1113 for_each_child_of_node(phandle->parent, node) { 1114 enum mtk_ddp_comp_type comp_type; 1115 int comp_id; 1116 1117 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type); 1118 if (ret) 1119 continue; 1120 1121 if (!of_device_is_available(node)) { 1122 dev_dbg(dev, "Skipping disabled component %pOF\n", 1123 node); 1124 continue; 1125 } 1126 1127 if (comp_type == MTK_DISP_MUTEX) { 1128 int id; 1129 1130 id = of_alias_get_id(node, "mutex"); 1131 if (id < 0 || id == private->data->mmsys_id) { 1132 private->mutex_node = of_node_get(node); 1133 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 1134 } 1135 continue; 1136 } 1137 1138 comp_id = mtk_ddp_comp_get_id(node, comp_type); 1139 if (comp_id < 0) { 1140 dev_warn(dev, "Skipping unknown component %pOF\n", 1141 node); 1142 continue; 1143 } 1144 1145 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 1146 continue; 1147 1148 private->comp_node[comp_id] = of_node_get(node); 1149 1150 /* 1151 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 1152 * blocks have separate component platform drivers and initialize their own 1153 * DDP component structure. The others are initialized here. 1154 */ 1155 if (comp_type == MTK_DISP_AAL || 1156 comp_type == MTK_DISP_CCORR || 1157 comp_type == MTK_DISP_COLOR || 1158 comp_type == MTK_DISP_GAMMA || 1159 comp_type == MTK_DISP_MERGE || 1160 comp_type == MTK_DISP_OVL || 1161 comp_type == MTK_DISP_OVL_2L || 1162 comp_type == MTK_DISP_OVL_ADAPTOR || 1163 comp_type == MTK_DISP_RDMA || 1164 comp_type == MTK_DP_INTF || 1165 comp_type == MTK_DPI || 1166 comp_type == MTK_DSI) { 1167 dev_info(dev, "Adding component match for %pOF\n", 1168 node); 1169 drm_of_component_match_add(dev, &match, component_compare_of, 1170 node); 1171 } 1172 1173 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 1174 if (ret) { 1175 of_node_put(node); 1176 goto err_node; 1177 } 1178 } 1179 1180 if (!private->mutex_node) { 1181 dev_err(dev, "Failed to find disp-mutex node\n"); 1182 ret = -ENODEV; 1183 goto err_node; 1184 } 1185 1186 pm_runtime_enable(dev); 1187 1188 platform_set_drvdata(pdev, private); 1189 1190 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 1191 if (ret) 1192 goto err_pm; 1193 1194 return 0; 1195 1196 err_pm: 1197 pm_runtime_disable(dev); 1198 err_node: 1199 of_node_put(private->mutex_node); 1200 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1201 of_node_put(private->comp_node[i]); 1202 return ret; 1203 } 1204 1205 static void mtk_drm_remove(struct platform_device *pdev) 1206 { 1207 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1208 int i; 1209 1210 component_master_del(&pdev->dev, &mtk_drm_ops); 1211 pm_runtime_disable(&pdev->dev); 1212 of_node_put(private->mutex_node); 1213 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1214 of_node_put(private->comp_node[i]); 1215 } 1216 1217 static void mtk_drm_shutdown(struct platform_device *pdev) 1218 { 1219 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1220 1221 drm_atomic_helper_shutdown(private->drm); 1222 } 1223 1224 static int mtk_drm_sys_prepare(struct device *dev) 1225 { 1226 struct mtk_drm_private *private = dev_get_drvdata(dev); 1227 struct drm_device *drm = private->drm; 1228 1229 if (private->drm_master) 1230 return drm_mode_config_helper_suspend(drm); 1231 else 1232 return 0; 1233 } 1234 1235 static void mtk_drm_sys_complete(struct device *dev) 1236 { 1237 struct mtk_drm_private *private = dev_get_drvdata(dev); 1238 struct drm_device *drm = private->drm; 1239 int ret = 0; 1240 1241 if (private->drm_master) 1242 ret = drm_mode_config_helper_resume(drm); 1243 if (ret) 1244 dev_err(dev, "Failed to resume\n"); 1245 } 1246 1247 static const struct dev_pm_ops mtk_drm_pm_ops = { 1248 .prepare = mtk_drm_sys_prepare, 1249 .complete = mtk_drm_sys_complete, 1250 }; 1251 1252 static struct platform_driver mtk_drm_platform_driver = { 1253 .probe = mtk_drm_probe, 1254 .remove_new = mtk_drm_remove, 1255 .shutdown = mtk_drm_shutdown, 1256 .driver = { 1257 .name = "mediatek-drm", 1258 .pm = &mtk_drm_pm_ops, 1259 }, 1260 }; 1261 1262 static struct platform_driver * const mtk_drm_drivers[] = { 1263 &mtk_disp_aal_driver, 1264 &mtk_disp_ccorr_driver, 1265 &mtk_disp_color_driver, 1266 &mtk_disp_gamma_driver, 1267 &mtk_disp_merge_driver, 1268 &mtk_disp_ovl_adaptor_driver, 1269 &mtk_disp_ovl_driver, 1270 &mtk_disp_rdma_driver, 1271 &mtk_dpi_driver, 1272 &mtk_drm_platform_driver, 1273 &mtk_dsi_driver, 1274 &mtk_ethdr_driver, 1275 &mtk_mdp_rdma_driver, 1276 &mtk_padding_driver, 1277 }; 1278 1279 static int __init mtk_drm_init(void) 1280 { 1281 return platform_register_drivers(mtk_drm_drivers, 1282 ARRAY_SIZE(mtk_drm_drivers)); 1283 } 1284 1285 static void __exit mtk_drm_exit(void) 1286 { 1287 platform_unregister_drivers(mtk_drm_drivers, 1288 ARRAY_SIZE(mtk_drm_drivers)); 1289 } 1290 1291 module_init(mtk_drm_init); 1292 module_exit(mtk_drm_exit); 1293 1294 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1295 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1296 MODULE_LICENSE("GPL v2"); 1297