1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fbdev_generic.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_ioctl.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "mtk_drm_crtc.h" 28 #include "mtk_drm_ddp_comp.h" 29 #include "mtk_drm_drv.h" 30 #include "mtk_drm_gem.h" 31 32 #define DRIVER_NAME "mediatek" 33 #define DRIVER_DESC "Mediatek SoC DRM" 34 #define DRIVER_DATE "20150513" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 39 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 40 }; 41 42 static struct drm_framebuffer * 43 mtk_drm_mode_fb_create(struct drm_device *dev, 44 struct drm_file *file, 45 const struct drm_mode_fb_cmd2 *cmd) 46 { 47 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 48 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const unsigned int mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const unsigned int mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const unsigned int mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const unsigned int mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const unsigned int mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const unsigned int mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const unsigned int mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static unsigned int mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER0, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const unsigned int mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const unsigned int mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const unsigned int mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER0, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const unsigned int mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const unsigned int mt8186_mtk_ddp_main[] = { 162 DDP_COMPONENT_OVL0, 163 DDP_COMPONENT_RDMA0, 164 DDP_COMPONENT_COLOR0, 165 DDP_COMPONENT_CCORR, 166 DDP_COMPONENT_AAL0, 167 DDP_COMPONENT_GAMMA, 168 DDP_COMPONENT_POSTMASK0, 169 DDP_COMPONENT_DITHER0, 170 DDP_COMPONENT_DSI0, 171 }; 172 173 static const unsigned int mt8186_mtk_ddp_ext[] = { 174 DDP_COMPONENT_OVL_2L0, 175 DDP_COMPONENT_RDMA1, 176 DDP_COMPONENT_DPI0, 177 }; 178 179 static const unsigned int mt8188_mtk_ddp_main[] = { 180 DDP_COMPONENT_OVL0, 181 DDP_COMPONENT_RDMA0, 182 DDP_COMPONENT_COLOR0, 183 DDP_COMPONENT_CCORR, 184 DDP_COMPONENT_AAL0, 185 DDP_COMPONENT_GAMMA, 186 DDP_COMPONENT_POSTMASK0, 187 DDP_COMPONENT_DITHER0, 188 }; 189 190 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 191 {0, DDP_COMPONENT_DP_INTF0}, 192 {0, DDP_COMPONENT_DSI0}, 193 }; 194 195 static const unsigned int mt8192_mtk_ddp_main[] = { 196 DDP_COMPONENT_OVL0, 197 DDP_COMPONENT_OVL_2L0, 198 DDP_COMPONENT_RDMA0, 199 DDP_COMPONENT_COLOR0, 200 DDP_COMPONENT_CCORR, 201 DDP_COMPONENT_AAL0, 202 DDP_COMPONENT_GAMMA, 203 DDP_COMPONENT_POSTMASK0, 204 DDP_COMPONENT_DITHER0, 205 DDP_COMPONENT_DSI0, 206 }; 207 208 static const unsigned int mt8192_mtk_ddp_ext[] = { 209 DDP_COMPONENT_OVL_2L2, 210 DDP_COMPONENT_RDMA4, 211 DDP_COMPONENT_DPI0, 212 }; 213 214 static const unsigned int mt8195_mtk_ddp_main[] = { 215 DDP_COMPONENT_OVL0, 216 DDP_COMPONENT_RDMA0, 217 DDP_COMPONENT_COLOR0, 218 DDP_COMPONENT_CCORR, 219 DDP_COMPONENT_AAL0, 220 DDP_COMPONENT_GAMMA, 221 DDP_COMPONENT_DITHER0, 222 DDP_COMPONENT_DSC0, 223 DDP_COMPONENT_MERGE0, 224 DDP_COMPONENT_DP_INTF0, 225 }; 226 227 static const unsigned int mt8195_mtk_ddp_ext[] = { 228 DDP_COMPONENT_DRM_OVL_ADAPTOR, 229 DDP_COMPONENT_MERGE5, 230 DDP_COMPONENT_DP_INTF1, 231 }; 232 233 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 234 .main_path = mt2701_mtk_ddp_main, 235 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 236 .ext_path = mt2701_mtk_ddp_ext, 237 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 238 .shadow_register = true, 239 .mmsys_dev_num = 1, 240 }; 241 242 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 243 .main_path = mt7623_mtk_ddp_main, 244 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 245 .ext_path = mt7623_mtk_ddp_ext, 246 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 247 .shadow_register = true, 248 .mmsys_dev_num = 1, 249 }; 250 251 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 252 .main_path = mt2712_mtk_ddp_main, 253 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 254 .ext_path = mt2712_mtk_ddp_ext, 255 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 256 .third_path = mt2712_mtk_ddp_third, 257 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 258 .mmsys_dev_num = 1, 259 }; 260 261 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 262 .main_path = mt8167_mtk_ddp_main, 263 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 264 .mmsys_dev_num = 1, 265 }; 266 267 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 268 .main_path = mt8173_mtk_ddp_main, 269 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 270 .ext_path = mt8173_mtk_ddp_ext, 271 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 272 .mmsys_dev_num = 1, 273 }; 274 275 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 276 .main_path = mt8183_mtk_ddp_main, 277 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 278 .ext_path = mt8183_mtk_ddp_ext, 279 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 280 .mmsys_dev_num = 1, 281 }; 282 283 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 284 .main_path = mt8186_mtk_ddp_main, 285 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 286 .ext_path = mt8186_mtk_ddp_ext, 287 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 288 .mmsys_dev_num = 1, 289 }; 290 291 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 292 .main_path = mt8188_mtk_ddp_main, 293 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 294 .conn_routes = mt8188_mtk_ddp_main_routes, 295 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 296 .mmsys_dev_num = 1, 297 }; 298 299 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 300 .main_path = mt8192_mtk_ddp_main, 301 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 302 .ext_path = mt8192_mtk_ddp_ext, 303 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 304 .mmsys_dev_num = 1, 305 }; 306 307 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 308 .main_path = mt8195_mtk_ddp_main, 309 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 310 .mmsys_dev_num = 2, 311 }; 312 313 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 314 .ext_path = mt8195_mtk_ddp_ext, 315 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 316 .mmsys_id = 1, 317 .mmsys_dev_num = 2, 318 }; 319 320 static const struct of_device_id mtk_drm_of_ids[] = { 321 { .compatible = "mediatek,mt2701-mmsys", 322 .data = &mt2701_mmsys_driver_data}, 323 { .compatible = "mediatek,mt7623-mmsys", 324 .data = &mt7623_mmsys_driver_data}, 325 { .compatible = "mediatek,mt2712-mmsys", 326 .data = &mt2712_mmsys_driver_data}, 327 { .compatible = "mediatek,mt8167-mmsys", 328 .data = &mt8167_mmsys_driver_data}, 329 { .compatible = "mediatek,mt8173-mmsys", 330 .data = &mt8173_mmsys_driver_data}, 331 { .compatible = "mediatek,mt8183-mmsys", 332 .data = &mt8183_mmsys_driver_data}, 333 { .compatible = "mediatek,mt8186-mmsys", 334 .data = &mt8186_mmsys_driver_data}, 335 { .compatible = "mediatek,mt8188-vdosys0", 336 .data = &mt8188_vdosys0_driver_data}, 337 { .compatible = "mediatek,mt8192-mmsys", 338 .data = &mt8192_mmsys_driver_data}, 339 { .compatible = "mediatek,mt8195-mmsys", 340 .data = &mt8195_vdosys0_driver_data}, 341 { .compatible = "mediatek,mt8195-vdosys0", 342 .data = &mt8195_vdosys0_driver_data}, 343 { .compatible = "mediatek,mt8195-vdosys1", 344 .data = &mt8195_vdosys1_driver_data}, 345 { } 346 }; 347 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 348 349 static int mtk_drm_match(struct device *dev, void *data) 350 { 351 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 352 return true; 353 return false; 354 } 355 356 static bool mtk_drm_get_all_drm_priv(struct device *dev) 357 { 358 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 359 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 360 struct mtk_drm_private *temp_drm_priv; 361 struct device_node *phandle = dev->parent->of_node; 362 const struct of_device_id *of_id; 363 struct device_node *node; 364 struct device *drm_dev; 365 unsigned int cnt = 0; 366 int i, j; 367 368 for_each_child_of_node(phandle->parent, node) { 369 struct platform_device *pdev; 370 371 of_id = of_match_node(mtk_drm_of_ids, node); 372 if (!of_id) 373 continue; 374 375 pdev = of_find_device_by_node(node); 376 if (!pdev) 377 continue; 378 379 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 380 if (!drm_dev) 381 continue; 382 383 temp_drm_priv = dev_get_drvdata(drm_dev); 384 if (!temp_drm_priv) 385 continue; 386 387 if (temp_drm_priv->data->main_len) 388 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 389 else if (temp_drm_priv->data->ext_len) 390 all_drm_priv[CRTC_EXT] = temp_drm_priv; 391 else if (temp_drm_priv->data->third_len) 392 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 393 394 if (temp_drm_priv->mtk_drm_bound) 395 cnt++; 396 397 if (cnt == MAX_CRTC) 398 break; 399 } 400 401 if (drm_priv->data->mmsys_dev_num == cnt) { 402 for (i = 0; i < cnt; i++) 403 for (j = 0; j < cnt; j++) 404 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 405 406 return true; 407 } 408 409 return false; 410 } 411 412 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 413 { 414 const struct mtk_mmsys_driver_data *drv_data = private->data; 415 int i; 416 417 if (drv_data->main_path) 418 for (i = 0; i < drv_data->main_len; i++) 419 if (drv_data->main_path[i] == comp_id) 420 return true; 421 422 if (drv_data->ext_path) 423 for (i = 0; i < drv_data->ext_len; i++) 424 if (drv_data->ext_path[i] == comp_id) 425 return true; 426 427 if (drv_data->third_path) 428 for (i = 0; i < drv_data->third_len; i++) 429 if (drv_data->third_path[i] == comp_id) 430 return true; 431 432 if (drv_data->num_conn_routes) 433 for (i = 0; i < drv_data->num_conn_routes; i++) 434 if (drv_data->conn_routes[i].route_ddp == comp_id) 435 return true; 436 437 return false; 438 } 439 440 static int mtk_drm_kms_init(struct drm_device *drm) 441 { 442 struct mtk_drm_private *private = drm->dev_private; 443 struct mtk_drm_private *priv_n; 444 struct device *dma_dev = NULL; 445 int ret, i, j; 446 447 if (drm_firmware_drivers_only()) 448 return -ENODEV; 449 450 ret = drmm_mode_config_init(drm); 451 if (ret) 452 goto put_mutex_dev; 453 454 drm->mode_config.min_width = 64; 455 drm->mode_config.min_height = 64; 456 457 /* 458 * set max width and height as default value(4096x4096). 459 * this value would be used to check framebuffer size limitation 460 * at drm_mode_addfb(). 461 */ 462 drm->mode_config.max_width = 4096; 463 drm->mode_config.max_height = 4096; 464 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 465 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 466 467 for (i = 0; i < private->data->mmsys_dev_num; i++) { 468 drm->dev_private = private->all_drm_private[i]; 469 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 470 if (ret) 471 goto put_mutex_dev; 472 } 473 474 /* 475 * Ensure internal panels are at the top of the connector list before 476 * crtc creation. 477 */ 478 drm_helper_move_panel_connectors_to_head(drm); 479 480 /* 481 * 1. We currently support two fixed data streams, each optional, 482 * and each statically assigned to a crtc: 483 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 484 * 2. For multi mmsys architecture, crtc path data are located in 485 * different drm private data structures. Loop through crtc index to 486 * create crtc from the main path and then ext_path and finally the 487 * third path. 488 */ 489 for (i = 0; i < MAX_CRTC; i++) { 490 for (j = 0; j < private->data->mmsys_dev_num; j++) { 491 priv_n = private->all_drm_private[j]; 492 493 if (i == CRTC_MAIN && priv_n->data->main_len) { 494 ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, 495 priv_n->data->main_len, j, 496 priv_n->data->conn_routes, 497 priv_n->data->num_conn_routes); 498 if (ret) 499 goto err_component_unbind; 500 501 continue; 502 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 503 ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path, 504 priv_n->data->ext_len, j, NULL, 0); 505 if (ret) 506 goto err_component_unbind; 507 508 continue; 509 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 510 ret = mtk_drm_crtc_create(drm, priv_n->data->third_path, 511 priv_n->data->third_len, j, NULL, 0); 512 if (ret) 513 goto err_component_unbind; 514 515 continue; 516 } 517 } 518 } 519 520 /* Use OVL device for all DMA memory allocations */ 521 dma_dev = mtk_drm_crtc_dma_dev_get(drm_crtc_from_index(drm, 0)); 522 if (!dma_dev) { 523 ret = -ENODEV; 524 dev_err(drm->dev, "Need at least one OVL device\n"); 525 goto err_component_unbind; 526 } 527 528 for (i = 0; i < private->data->mmsys_dev_num; i++) 529 private->all_drm_private[i]->dma_dev = dma_dev; 530 531 /* 532 * Configure the DMA segment size to make sure we get contiguous IOVA 533 * when importing PRIME buffers. 534 */ 535 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 536 if (ret) { 537 dev_err(dma_dev, "Failed to set DMA segment size\n"); 538 goto err_component_unbind; 539 } 540 541 ret = drm_vblank_init(drm, MAX_CRTC); 542 if (ret < 0) 543 goto err_component_unbind; 544 545 drm_kms_helper_poll_init(drm); 546 drm_mode_config_reset(drm); 547 548 return 0; 549 550 err_component_unbind: 551 for (i = 0; i < private->data->mmsys_dev_num; i++) 552 component_unbind_all(private->all_drm_private[i]->dev, drm); 553 put_mutex_dev: 554 for (i = 0; i < private->data->mmsys_dev_num; i++) 555 put_device(private->all_drm_private[i]->mutex_dev); 556 557 return ret; 558 } 559 560 static void mtk_drm_kms_deinit(struct drm_device *drm) 561 { 562 drm_kms_helper_poll_fini(drm); 563 drm_atomic_helper_shutdown(drm); 564 565 component_unbind_all(drm->dev, drm); 566 } 567 568 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 569 570 /* 571 * We need to override this because the device used to import the memory is 572 * not dev->dev, as drm_gem_prime_import() expects. 573 */ 574 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 575 struct dma_buf *dma_buf) 576 { 577 struct mtk_drm_private *private = dev->dev_private; 578 579 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 580 } 581 582 static const struct drm_driver mtk_drm_driver = { 583 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 584 585 .dumb_create = mtk_drm_gem_dumb_create, 586 587 .gem_prime_import = mtk_drm_gem_prime_import, 588 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 589 .fops = &mtk_drm_fops, 590 591 .name = DRIVER_NAME, 592 .desc = DRIVER_DESC, 593 .date = DRIVER_DATE, 594 .major = DRIVER_MAJOR, 595 .minor = DRIVER_MINOR, 596 }; 597 598 static int compare_dev(struct device *dev, void *data) 599 { 600 return dev == (struct device *)data; 601 } 602 603 static int mtk_drm_bind(struct device *dev) 604 { 605 struct mtk_drm_private *private = dev_get_drvdata(dev); 606 struct platform_device *pdev; 607 struct drm_device *drm; 608 int ret, i; 609 610 pdev = of_find_device_by_node(private->mutex_node); 611 if (!pdev) { 612 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 613 private->mutex_node); 614 of_node_put(private->mutex_node); 615 return -EPROBE_DEFER; 616 } 617 618 private->mutex_dev = &pdev->dev; 619 private->mtk_drm_bound = true; 620 private->dev = dev; 621 622 if (!mtk_drm_get_all_drm_priv(dev)) 623 return 0; 624 625 drm = drm_dev_alloc(&mtk_drm_driver, dev); 626 if (IS_ERR(drm)) 627 return PTR_ERR(drm); 628 629 private->drm_master = true; 630 drm->dev_private = private; 631 for (i = 0; i < private->data->mmsys_dev_num; i++) 632 private->all_drm_private[i]->drm = drm; 633 634 ret = mtk_drm_kms_init(drm); 635 if (ret < 0) 636 goto err_free; 637 638 ret = drm_dev_register(drm, 0); 639 if (ret < 0) 640 goto err_deinit; 641 642 drm_fbdev_generic_setup(drm, 32); 643 644 return 0; 645 646 err_deinit: 647 mtk_drm_kms_deinit(drm); 648 err_free: 649 private->drm = NULL; 650 drm_dev_put(drm); 651 return ret; 652 } 653 654 static void mtk_drm_unbind(struct device *dev) 655 { 656 struct mtk_drm_private *private = dev_get_drvdata(dev); 657 658 /* for multi mmsys dev, unregister drm dev in mmsys master */ 659 if (private->drm_master) { 660 drm_dev_unregister(private->drm); 661 mtk_drm_kms_deinit(private->drm); 662 drm_dev_put(private->drm); 663 } 664 private->mtk_drm_bound = false; 665 private->drm_master = false; 666 private->drm = NULL; 667 } 668 669 static const struct component_master_ops mtk_drm_ops = { 670 .bind = mtk_drm_bind, 671 .unbind = mtk_drm_unbind, 672 }; 673 674 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 675 { .compatible = "mediatek,mt8167-disp-aal", 676 .data = (void *)MTK_DISP_AAL}, 677 { .compatible = "mediatek,mt8173-disp-aal", 678 .data = (void *)MTK_DISP_AAL}, 679 { .compatible = "mediatek,mt8183-disp-aal", 680 .data = (void *)MTK_DISP_AAL}, 681 { .compatible = "mediatek,mt8192-disp-aal", 682 .data = (void *)MTK_DISP_AAL}, 683 { .compatible = "mediatek,mt8167-disp-ccorr", 684 .data = (void *)MTK_DISP_CCORR }, 685 { .compatible = "mediatek,mt8183-disp-ccorr", 686 .data = (void *)MTK_DISP_CCORR }, 687 { .compatible = "mediatek,mt8192-disp-ccorr", 688 .data = (void *)MTK_DISP_CCORR }, 689 { .compatible = "mediatek,mt2701-disp-color", 690 .data = (void *)MTK_DISP_COLOR }, 691 { .compatible = "mediatek,mt8167-disp-color", 692 .data = (void *)MTK_DISP_COLOR }, 693 { .compatible = "mediatek,mt8173-disp-color", 694 .data = (void *)MTK_DISP_COLOR }, 695 { .compatible = "mediatek,mt8167-disp-dither", 696 .data = (void *)MTK_DISP_DITHER }, 697 { .compatible = "mediatek,mt8183-disp-dither", 698 .data = (void *)MTK_DISP_DITHER }, 699 { .compatible = "mediatek,mt8195-disp-dsc", 700 .data = (void *)MTK_DISP_DSC }, 701 { .compatible = "mediatek,mt8167-disp-gamma", 702 .data = (void *)MTK_DISP_GAMMA, }, 703 { .compatible = "mediatek,mt8173-disp-gamma", 704 .data = (void *)MTK_DISP_GAMMA, }, 705 { .compatible = "mediatek,mt8183-disp-gamma", 706 .data = (void *)MTK_DISP_GAMMA, }, 707 { .compatible = "mediatek,mt8195-disp-merge", 708 .data = (void *)MTK_DISP_MERGE }, 709 { .compatible = "mediatek,mt2701-disp-mutex", 710 .data = (void *)MTK_DISP_MUTEX }, 711 { .compatible = "mediatek,mt2712-disp-mutex", 712 .data = (void *)MTK_DISP_MUTEX }, 713 { .compatible = "mediatek,mt8167-disp-mutex", 714 .data = (void *)MTK_DISP_MUTEX }, 715 { .compatible = "mediatek,mt8173-disp-mutex", 716 .data = (void *)MTK_DISP_MUTEX }, 717 { .compatible = "mediatek,mt8183-disp-mutex", 718 .data = (void *)MTK_DISP_MUTEX }, 719 { .compatible = "mediatek,mt8186-disp-mutex", 720 .data = (void *)MTK_DISP_MUTEX }, 721 { .compatible = "mediatek,mt8188-disp-mutex", 722 .data = (void *)MTK_DISP_MUTEX }, 723 { .compatible = "mediatek,mt8192-disp-mutex", 724 .data = (void *)MTK_DISP_MUTEX }, 725 { .compatible = "mediatek,mt8195-disp-mutex", 726 .data = (void *)MTK_DISP_MUTEX }, 727 { .compatible = "mediatek,mt8173-disp-od", 728 .data = (void *)MTK_DISP_OD }, 729 { .compatible = "mediatek,mt2701-disp-ovl", 730 .data = (void *)MTK_DISP_OVL }, 731 { .compatible = "mediatek,mt8167-disp-ovl", 732 .data = (void *)MTK_DISP_OVL }, 733 { .compatible = "mediatek,mt8173-disp-ovl", 734 .data = (void *)MTK_DISP_OVL }, 735 { .compatible = "mediatek,mt8183-disp-ovl", 736 .data = (void *)MTK_DISP_OVL }, 737 { .compatible = "mediatek,mt8192-disp-ovl", 738 .data = (void *)MTK_DISP_OVL }, 739 { .compatible = "mediatek,mt8183-disp-ovl-2l", 740 .data = (void *)MTK_DISP_OVL_2L }, 741 { .compatible = "mediatek,mt8192-disp-ovl-2l", 742 .data = (void *)MTK_DISP_OVL_2L }, 743 { .compatible = "mediatek,mt8192-disp-postmask", 744 .data = (void *)MTK_DISP_POSTMASK }, 745 { .compatible = "mediatek,mt2701-disp-pwm", 746 .data = (void *)MTK_DISP_BLS }, 747 { .compatible = "mediatek,mt8167-disp-pwm", 748 .data = (void *)MTK_DISP_PWM }, 749 { .compatible = "mediatek,mt8173-disp-pwm", 750 .data = (void *)MTK_DISP_PWM }, 751 { .compatible = "mediatek,mt2701-disp-rdma", 752 .data = (void *)MTK_DISP_RDMA }, 753 { .compatible = "mediatek,mt8167-disp-rdma", 754 .data = (void *)MTK_DISP_RDMA }, 755 { .compatible = "mediatek,mt8173-disp-rdma", 756 .data = (void *)MTK_DISP_RDMA }, 757 { .compatible = "mediatek,mt8183-disp-rdma", 758 .data = (void *)MTK_DISP_RDMA }, 759 { .compatible = "mediatek,mt8195-disp-rdma", 760 .data = (void *)MTK_DISP_RDMA }, 761 { .compatible = "mediatek,mt8173-disp-ufoe", 762 .data = (void *)MTK_DISP_UFOE }, 763 { .compatible = "mediatek,mt8173-disp-wdma", 764 .data = (void *)MTK_DISP_WDMA }, 765 { .compatible = "mediatek,mt2701-dpi", 766 .data = (void *)MTK_DPI }, 767 { .compatible = "mediatek,mt8167-dsi", 768 .data = (void *)MTK_DSI }, 769 { .compatible = "mediatek,mt8173-dpi", 770 .data = (void *)MTK_DPI }, 771 { .compatible = "mediatek,mt8183-dpi", 772 .data = (void *)MTK_DPI }, 773 { .compatible = "mediatek,mt8186-dpi", 774 .data = (void *)MTK_DPI }, 775 { .compatible = "mediatek,mt8188-dp-intf", 776 .data = (void *)MTK_DP_INTF }, 777 { .compatible = "mediatek,mt8192-dpi", 778 .data = (void *)MTK_DPI }, 779 { .compatible = "mediatek,mt8195-dp-intf", 780 .data = (void *)MTK_DP_INTF }, 781 { .compatible = "mediatek,mt2701-dsi", 782 .data = (void *)MTK_DSI }, 783 { .compatible = "mediatek,mt8173-dsi", 784 .data = (void *)MTK_DSI }, 785 { .compatible = "mediatek,mt8183-dsi", 786 .data = (void *)MTK_DSI }, 787 { .compatible = "mediatek,mt8186-dsi", 788 .data = (void *)MTK_DSI }, 789 { .compatible = "mediatek,mt8188-dsi", 790 .data = (void *)MTK_DSI }, 791 { } 792 }; 793 794 static int mtk_drm_probe(struct platform_device *pdev) 795 { 796 struct device *dev = &pdev->dev; 797 struct device_node *phandle = dev->parent->of_node; 798 const struct of_device_id *of_id; 799 struct mtk_drm_private *private; 800 struct device_node *node; 801 struct component_match *match = NULL; 802 struct platform_device *ovl_adaptor; 803 int ret; 804 int i; 805 806 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 807 if (!private) 808 return -ENOMEM; 809 810 private->mmsys_dev = dev->parent; 811 if (!private->mmsys_dev) { 812 dev_err(dev, "Failed to get MMSYS device\n"); 813 return -ENODEV; 814 } 815 816 of_id = of_match_node(mtk_drm_of_ids, phandle); 817 if (!of_id) 818 return -ENODEV; 819 820 private->data = of_id->data; 821 822 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 823 sizeof(*private->all_drm_private), 824 GFP_KERNEL); 825 if (!private->all_drm_private) 826 return -ENOMEM; 827 828 /* Bringup ovl_adaptor */ 829 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 830 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 831 PLATFORM_DEVID_AUTO, 832 (void *)private->mmsys_dev, 833 sizeof(*private->mmsys_dev)); 834 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 835 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 836 DDP_COMPONENT_DRM_OVL_ADAPTOR); 837 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 838 } 839 840 /* Iterate over sibling DISP function blocks */ 841 for_each_child_of_node(phandle->parent, node) { 842 const struct of_device_id *of_id; 843 enum mtk_ddp_comp_type comp_type; 844 int comp_id; 845 846 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 847 if (!of_id) 848 continue; 849 850 if (!of_device_is_available(node)) { 851 dev_dbg(dev, "Skipping disabled component %pOF\n", 852 node); 853 continue; 854 } 855 856 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data; 857 858 if (comp_type == MTK_DISP_MUTEX) { 859 int id; 860 861 id = of_alias_get_id(node, "mutex"); 862 if (id < 0 || id == private->data->mmsys_id) { 863 private->mutex_node = of_node_get(node); 864 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 865 } 866 continue; 867 } 868 869 comp_id = mtk_ddp_comp_get_id(node, comp_type); 870 if (comp_id < 0) { 871 dev_warn(dev, "Skipping unknown component %pOF\n", 872 node); 873 continue; 874 } 875 876 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 877 continue; 878 879 private->comp_node[comp_id] = of_node_get(node); 880 881 /* 882 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 883 * blocks have separate component platform drivers and initialize their own 884 * DDP component structure. The others are initialized here. 885 */ 886 if (comp_type == MTK_DISP_AAL || 887 comp_type == MTK_DISP_CCORR || 888 comp_type == MTK_DISP_COLOR || 889 comp_type == MTK_DISP_GAMMA || 890 comp_type == MTK_DISP_MERGE || 891 comp_type == MTK_DISP_OVL || 892 comp_type == MTK_DISP_OVL_2L || 893 comp_type == MTK_DISP_OVL_ADAPTOR || 894 comp_type == MTK_DISP_RDMA || 895 comp_type == MTK_DP_INTF || 896 comp_type == MTK_DPI || 897 comp_type == MTK_DSI) { 898 dev_info(dev, "Adding component match for %pOF\n", 899 node); 900 drm_of_component_match_add(dev, &match, component_compare_of, 901 node); 902 } 903 904 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 905 if (ret) { 906 of_node_put(node); 907 goto err_node; 908 } 909 } 910 911 if (!private->mutex_node) { 912 dev_err(dev, "Failed to find disp-mutex node\n"); 913 ret = -ENODEV; 914 goto err_node; 915 } 916 917 pm_runtime_enable(dev); 918 919 platform_set_drvdata(pdev, private); 920 921 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 922 if (ret) 923 goto err_pm; 924 925 return 0; 926 927 err_pm: 928 pm_runtime_disable(dev); 929 err_node: 930 of_node_put(private->mutex_node); 931 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 932 of_node_put(private->comp_node[i]); 933 return ret; 934 } 935 936 static void mtk_drm_remove(struct platform_device *pdev) 937 { 938 struct mtk_drm_private *private = platform_get_drvdata(pdev); 939 int i; 940 941 component_master_del(&pdev->dev, &mtk_drm_ops); 942 pm_runtime_disable(&pdev->dev); 943 of_node_put(private->mutex_node); 944 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 945 of_node_put(private->comp_node[i]); 946 } 947 948 static int mtk_drm_sys_prepare(struct device *dev) 949 { 950 struct mtk_drm_private *private = dev_get_drvdata(dev); 951 struct drm_device *drm = private->drm; 952 953 if (private->drm_master) 954 return drm_mode_config_helper_suspend(drm); 955 else 956 return 0; 957 } 958 959 static void mtk_drm_sys_complete(struct device *dev) 960 { 961 struct mtk_drm_private *private = dev_get_drvdata(dev); 962 struct drm_device *drm = private->drm; 963 int ret = 0; 964 965 if (private->drm_master) 966 ret = drm_mode_config_helper_resume(drm); 967 if (ret) 968 dev_err(dev, "Failed to resume\n"); 969 } 970 971 static const struct dev_pm_ops mtk_drm_pm_ops = { 972 .prepare = mtk_drm_sys_prepare, 973 .complete = mtk_drm_sys_complete, 974 }; 975 976 static struct platform_driver mtk_drm_platform_driver = { 977 .probe = mtk_drm_probe, 978 .remove_new = mtk_drm_remove, 979 .driver = { 980 .name = "mediatek-drm", 981 .pm = &mtk_drm_pm_ops, 982 }, 983 }; 984 985 static struct platform_driver * const mtk_drm_drivers[] = { 986 &mtk_disp_aal_driver, 987 &mtk_disp_ccorr_driver, 988 &mtk_disp_color_driver, 989 &mtk_disp_gamma_driver, 990 &mtk_disp_merge_driver, 991 &mtk_disp_ovl_adaptor_driver, 992 &mtk_disp_ovl_driver, 993 &mtk_disp_rdma_driver, 994 &mtk_dpi_driver, 995 &mtk_drm_platform_driver, 996 &mtk_dsi_driver, 997 &mtk_ethdr_driver, 998 &mtk_mdp_rdma_driver, 999 &mtk_padding_driver, 1000 }; 1001 1002 static int __init mtk_drm_init(void) 1003 { 1004 return platform_register_drivers(mtk_drm_drivers, 1005 ARRAY_SIZE(mtk_drm_drivers)); 1006 } 1007 1008 static void __exit mtk_drm_exit(void) 1009 { 1010 platform_unregister_drivers(mtk_drm_drivers, 1011 ARRAY_SIZE(mtk_drm_drivers)); 1012 } 1013 1014 module_init(mtk_drm_init); 1015 module_exit(mtk_drm_exit); 1016 1017 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1018 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1019 MODULE_LICENSE("GPL v2"); 1020