1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_client_setup.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_crtc.h" 29 #include "mtk_ddp_comp.h" 30 #include "mtk_drm_drv.h" 31 #include "mtk_gem.h" 32 33 #define DRIVER_NAME "mediatek" 34 #define DRIVER_DESC "Mediatek SoC DRM" 35 #define DRIVER_DATE "20150513" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_mode_fb_cmd2 *cmd) 47 { 48 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 49 50 if (info->num_planes != 1) 51 return ERR_PTR(-EINVAL); 52 53 return drm_gem_fb_create(dev, file, cmd); 54 } 55 56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 57 .fb_create = mtk_drm_mode_fb_create, 58 .atomic_check = drm_atomic_helper_check, 59 .atomic_commit = drm_atomic_helper_commit, 60 }; 61 62 static const unsigned int mt2701_mtk_ddp_main[] = { 63 DDP_COMPONENT_OVL0, 64 DDP_COMPONENT_RDMA0, 65 DDP_COMPONENT_COLOR0, 66 DDP_COMPONENT_BLS, 67 DDP_COMPONENT_DSI0, 68 }; 69 70 static const unsigned int mt2701_mtk_ddp_ext[] = { 71 DDP_COMPONENT_RDMA1, 72 DDP_COMPONENT_DPI0, 73 }; 74 75 static const unsigned int mt7623_mtk_ddp_main[] = { 76 DDP_COMPONENT_OVL0, 77 DDP_COMPONENT_RDMA0, 78 DDP_COMPONENT_COLOR0, 79 DDP_COMPONENT_BLS, 80 DDP_COMPONENT_DPI0, 81 }; 82 83 static const unsigned int mt7623_mtk_ddp_ext[] = { 84 DDP_COMPONENT_RDMA1, 85 DDP_COMPONENT_DSI0, 86 }; 87 88 static const unsigned int mt2712_mtk_ddp_main[] = { 89 DDP_COMPONENT_OVL0, 90 DDP_COMPONENT_COLOR0, 91 DDP_COMPONENT_AAL0, 92 DDP_COMPONENT_OD0, 93 DDP_COMPONENT_RDMA0, 94 DDP_COMPONENT_DPI0, 95 DDP_COMPONENT_PWM0, 96 }; 97 98 static const unsigned int mt2712_mtk_ddp_ext[] = { 99 DDP_COMPONENT_OVL1, 100 DDP_COMPONENT_COLOR1, 101 DDP_COMPONENT_AAL1, 102 DDP_COMPONENT_OD1, 103 DDP_COMPONENT_RDMA1, 104 DDP_COMPONENT_DPI1, 105 DDP_COMPONENT_PWM1, 106 }; 107 108 static const unsigned int mt2712_mtk_ddp_third[] = { 109 DDP_COMPONENT_RDMA2, 110 DDP_COMPONENT_DSI3, 111 DDP_COMPONENT_PWM2, 112 }; 113 114 static unsigned int mt8167_mtk_ddp_main[] = { 115 DDP_COMPONENT_OVL0, 116 DDP_COMPONENT_COLOR0, 117 DDP_COMPONENT_CCORR, 118 DDP_COMPONENT_AAL0, 119 DDP_COMPONENT_GAMMA, 120 DDP_COMPONENT_DITHER0, 121 DDP_COMPONENT_RDMA0, 122 DDP_COMPONENT_DSI0, 123 }; 124 125 static const unsigned int mt8173_mtk_ddp_main[] = { 126 DDP_COMPONENT_OVL0, 127 DDP_COMPONENT_COLOR0, 128 DDP_COMPONENT_AAL0, 129 DDP_COMPONENT_OD0, 130 DDP_COMPONENT_RDMA0, 131 DDP_COMPONENT_UFOE, 132 DDP_COMPONENT_DSI0, 133 DDP_COMPONENT_PWM0, 134 }; 135 136 static const unsigned int mt8173_mtk_ddp_ext[] = { 137 DDP_COMPONENT_OVL1, 138 DDP_COMPONENT_COLOR1, 139 DDP_COMPONENT_GAMMA, 140 DDP_COMPONENT_RDMA1, 141 DDP_COMPONENT_DPI0, 142 }; 143 144 static const unsigned int mt8183_mtk_ddp_main[] = { 145 DDP_COMPONENT_OVL0, 146 DDP_COMPONENT_OVL_2L0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_COLOR0, 149 DDP_COMPONENT_CCORR, 150 DDP_COMPONENT_AAL0, 151 DDP_COMPONENT_GAMMA, 152 DDP_COMPONENT_DITHER0, 153 DDP_COMPONENT_DSI0, 154 }; 155 156 static const unsigned int mt8183_mtk_ddp_ext[] = { 157 DDP_COMPONENT_OVL_2L1, 158 DDP_COMPONENT_RDMA1, 159 DDP_COMPONENT_DPI0, 160 }; 161 162 static const unsigned int mt8186_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER0, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const unsigned int mt8186_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L0, 176 DDP_COMPONENT_RDMA1, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const unsigned int mt8188_mtk_ddp_main[] = { 181 DDP_COMPONENT_OVL0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_COLOR0, 184 DDP_COMPONENT_CCORR, 185 DDP_COMPONENT_AAL0, 186 DDP_COMPONENT_GAMMA, 187 DDP_COMPONENT_POSTMASK0, 188 DDP_COMPONENT_DITHER0, 189 }; 190 191 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 192 {0, DDP_COMPONENT_DP_INTF0}, 193 {0, DDP_COMPONENT_DSI0}, 194 }; 195 196 static const unsigned int mt8192_mtk_ddp_main[] = { 197 DDP_COMPONENT_OVL0, 198 DDP_COMPONENT_OVL_2L0, 199 DDP_COMPONENT_RDMA0, 200 DDP_COMPONENT_COLOR0, 201 DDP_COMPONENT_CCORR, 202 DDP_COMPONENT_AAL0, 203 DDP_COMPONENT_GAMMA, 204 DDP_COMPONENT_POSTMASK0, 205 DDP_COMPONENT_DITHER0, 206 DDP_COMPONENT_DSI0, 207 }; 208 209 static const unsigned int mt8192_mtk_ddp_ext[] = { 210 DDP_COMPONENT_OVL_2L2, 211 DDP_COMPONENT_RDMA4, 212 DDP_COMPONENT_DPI0, 213 }; 214 215 static const unsigned int mt8195_mtk_ddp_main[] = { 216 DDP_COMPONENT_OVL0, 217 DDP_COMPONENT_RDMA0, 218 DDP_COMPONENT_COLOR0, 219 DDP_COMPONENT_CCORR, 220 DDP_COMPONENT_AAL0, 221 DDP_COMPONENT_GAMMA, 222 DDP_COMPONENT_DITHER0, 223 DDP_COMPONENT_DSC0, 224 DDP_COMPONENT_MERGE0, 225 DDP_COMPONENT_DP_INTF0, 226 }; 227 228 static const unsigned int mt8195_mtk_ddp_ext[] = { 229 DDP_COMPONENT_DRM_OVL_ADAPTOR, 230 DDP_COMPONENT_MERGE5, 231 DDP_COMPONENT_DP_INTF1, 232 }; 233 234 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 235 .main_path = mt2701_mtk_ddp_main, 236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 237 .ext_path = mt2701_mtk_ddp_ext, 238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 239 .shadow_register = true, 240 .mmsys_dev_num = 1, 241 }; 242 243 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 244 .main_path = mt7623_mtk_ddp_main, 245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 246 .ext_path = mt7623_mtk_ddp_ext, 247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 248 .shadow_register = true, 249 .mmsys_dev_num = 1, 250 }; 251 252 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 253 .main_path = mt2712_mtk_ddp_main, 254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 255 .ext_path = mt2712_mtk_ddp_ext, 256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 257 .third_path = mt2712_mtk_ddp_third, 258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 259 .mmsys_dev_num = 1, 260 }; 261 262 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 263 .main_path = mt8167_mtk_ddp_main, 264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 265 .mmsys_dev_num = 1, 266 }; 267 268 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 269 .main_path = mt8173_mtk_ddp_main, 270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 271 .ext_path = mt8173_mtk_ddp_ext, 272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 273 .mmsys_dev_num = 1, 274 }; 275 276 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 277 .main_path = mt8183_mtk_ddp_main, 278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 279 .ext_path = mt8183_mtk_ddp_ext, 280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 281 .mmsys_dev_num = 1, 282 }; 283 284 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 285 .main_path = mt8186_mtk_ddp_main, 286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 287 .ext_path = mt8186_mtk_ddp_ext, 288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 289 .mmsys_dev_num = 1, 290 }; 291 292 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 293 .main_path = mt8188_mtk_ddp_main, 294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 295 .conn_routes = mt8188_mtk_ddp_main_routes, 296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 297 .mmsys_dev_num = 2, 298 .max_width = 8191, 299 .min_width = 1, 300 .min_height = 1, 301 }; 302 303 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 304 .main_path = mt8192_mtk_ddp_main, 305 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 306 .ext_path = mt8192_mtk_ddp_ext, 307 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 308 .mmsys_dev_num = 1, 309 }; 310 311 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 312 .main_path = mt8195_mtk_ddp_main, 313 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 314 .mmsys_dev_num = 2, 315 .max_width = 8191, 316 .min_width = 1, 317 .min_height = 1, 318 }; 319 320 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 321 .ext_path = mt8195_mtk_ddp_ext, 322 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 323 .mmsys_id = 1, 324 .mmsys_dev_num = 2, 325 .max_width = 8191, 326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 327 .min_height = 1, 328 }; 329 330 static const struct of_device_id mtk_drm_of_ids[] = { 331 { .compatible = "mediatek,mt2701-mmsys", 332 .data = &mt2701_mmsys_driver_data}, 333 { .compatible = "mediatek,mt7623-mmsys", 334 .data = &mt7623_mmsys_driver_data}, 335 { .compatible = "mediatek,mt2712-mmsys", 336 .data = &mt2712_mmsys_driver_data}, 337 { .compatible = "mediatek,mt8167-mmsys", 338 .data = &mt8167_mmsys_driver_data}, 339 { .compatible = "mediatek,mt8173-mmsys", 340 .data = &mt8173_mmsys_driver_data}, 341 { .compatible = "mediatek,mt8183-mmsys", 342 .data = &mt8183_mmsys_driver_data}, 343 { .compatible = "mediatek,mt8186-mmsys", 344 .data = &mt8186_mmsys_driver_data}, 345 { .compatible = "mediatek,mt8188-vdosys0", 346 .data = &mt8188_vdosys0_driver_data}, 347 { .compatible = "mediatek,mt8188-vdosys1", 348 .data = &mt8195_vdosys1_driver_data}, 349 { .compatible = "mediatek,mt8192-mmsys", 350 .data = &mt8192_mmsys_driver_data}, 351 { .compatible = "mediatek,mt8195-mmsys", 352 .data = &mt8195_vdosys0_driver_data}, 353 { .compatible = "mediatek,mt8195-vdosys0", 354 .data = &mt8195_vdosys0_driver_data}, 355 { .compatible = "mediatek,mt8195-vdosys1", 356 .data = &mt8195_vdosys1_driver_data}, 357 { } 358 }; 359 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 360 361 static int mtk_drm_match(struct device *dev, void *data) 362 { 363 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 364 return true; 365 return false; 366 } 367 368 static bool mtk_drm_get_all_drm_priv(struct device *dev) 369 { 370 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 371 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 372 struct mtk_drm_private *temp_drm_priv; 373 struct device_node *phandle = dev->parent->of_node; 374 const struct of_device_id *of_id; 375 struct device_node *node; 376 struct device *drm_dev; 377 unsigned int cnt = 0; 378 int i, j; 379 380 for_each_child_of_node(phandle->parent, node) { 381 struct platform_device *pdev; 382 383 of_id = of_match_node(mtk_drm_of_ids, node); 384 if (!of_id) 385 continue; 386 387 pdev = of_find_device_by_node(node); 388 if (!pdev) 389 continue; 390 391 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 392 if (!drm_dev) 393 continue; 394 395 temp_drm_priv = dev_get_drvdata(drm_dev); 396 if (!temp_drm_priv) 397 continue; 398 399 if (temp_drm_priv->data->main_len) 400 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 401 else if (temp_drm_priv->data->ext_len) 402 all_drm_priv[CRTC_EXT] = temp_drm_priv; 403 else if (temp_drm_priv->data->third_len) 404 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 405 406 if (temp_drm_priv->mtk_drm_bound) 407 cnt++; 408 409 if (cnt == MAX_CRTC) 410 break; 411 } 412 413 if (drm_priv->data->mmsys_dev_num == cnt) { 414 for (i = 0; i < cnt; i++) 415 for (j = 0; j < cnt; j++) 416 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 417 418 return true; 419 } 420 421 return false; 422 } 423 424 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 425 { 426 const struct mtk_mmsys_driver_data *drv_data = private->data; 427 int i; 428 429 if (drv_data->main_path) 430 for (i = 0; i < drv_data->main_len; i++) 431 if (drv_data->main_path[i] == comp_id) 432 return true; 433 434 if (drv_data->ext_path) 435 for (i = 0; i < drv_data->ext_len; i++) 436 if (drv_data->ext_path[i] == comp_id) 437 return true; 438 439 if (drv_data->third_path) 440 for (i = 0; i < drv_data->third_len; i++) 441 if (drv_data->third_path[i] == comp_id) 442 return true; 443 444 if (drv_data->num_conn_routes) 445 for (i = 0; i < drv_data->num_conn_routes; i++) 446 if (drv_data->conn_routes[i].route_ddp == comp_id) 447 return true; 448 449 return false; 450 } 451 452 static int mtk_drm_kms_init(struct drm_device *drm) 453 { 454 struct mtk_drm_private *private = drm->dev_private; 455 struct mtk_drm_private *priv_n; 456 struct device *dma_dev = NULL; 457 struct drm_crtc *crtc; 458 int ret, i, j; 459 460 if (drm_firmware_drivers_only()) 461 return -ENODEV; 462 463 ret = drmm_mode_config_init(drm); 464 if (ret) 465 goto put_mutex_dev; 466 467 drm->mode_config.min_width = 64; 468 drm->mode_config.min_height = 64; 469 470 /* 471 * set max width and height as default value(4096x4096). 472 * this value would be used to check framebuffer size limitation 473 * at drm_mode_addfb(). 474 */ 475 drm->mode_config.max_width = 4096; 476 drm->mode_config.max_height = 4096; 477 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 478 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 479 480 for (i = 0; i < private->data->mmsys_dev_num; i++) { 481 drm->dev_private = private->all_drm_private[i]; 482 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 483 if (ret) 484 goto put_mutex_dev; 485 } 486 487 /* 488 * Ensure internal panels are at the top of the connector list before 489 * crtc creation. 490 */ 491 drm_helper_move_panel_connectors_to_head(drm); 492 493 /* 494 * 1. We currently support two fixed data streams, each optional, 495 * and each statically assigned to a crtc: 496 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 497 * 2. For multi mmsys architecture, crtc path data are located in 498 * different drm private data structures. Loop through crtc index to 499 * create crtc from the main path and then ext_path and finally the 500 * third path. 501 */ 502 for (i = 0; i < MAX_CRTC; i++) { 503 for (j = 0; j < private->data->mmsys_dev_num; j++) { 504 priv_n = private->all_drm_private[j]; 505 506 if (priv_n->data->max_width) 507 drm->mode_config.max_width = priv_n->data->max_width; 508 509 if (priv_n->data->min_width) 510 drm->mode_config.min_width = priv_n->data->min_width; 511 512 if (priv_n->data->min_height) 513 drm->mode_config.min_height = priv_n->data->min_height; 514 515 if (i == CRTC_MAIN && priv_n->data->main_len) { 516 ret = mtk_crtc_create(drm, priv_n->data->main_path, 517 priv_n->data->main_len, j, 518 priv_n->data->conn_routes, 519 priv_n->data->num_conn_routes); 520 if (ret) 521 goto err_component_unbind; 522 523 continue; 524 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 525 ret = mtk_crtc_create(drm, priv_n->data->ext_path, 526 priv_n->data->ext_len, j, NULL, 0); 527 if (ret) 528 goto err_component_unbind; 529 530 continue; 531 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 532 ret = mtk_crtc_create(drm, priv_n->data->third_path, 533 priv_n->data->third_len, j, NULL, 0); 534 if (ret) 535 goto err_component_unbind; 536 537 continue; 538 } 539 } 540 } 541 542 /* IGT will check if the cursor size is configured */ 543 drm->mode_config.cursor_width = 512; 544 drm->mode_config.cursor_height = 512; 545 546 /* Use OVL device for all DMA memory allocations */ 547 crtc = drm_crtc_from_index(drm, 0); 548 if (crtc) 549 dma_dev = mtk_crtc_dma_dev_get(crtc); 550 if (!dma_dev) { 551 ret = -ENODEV; 552 dev_err(drm->dev, "Need at least one OVL device\n"); 553 goto err_component_unbind; 554 } 555 556 for (i = 0; i < private->data->mmsys_dev_num; i++) 557 private->all_drm_private[i]->dma_dev = dma_dev; 558 559 /* 560 * Configure the DMA segment size to make sure we get contiguous IOVA 561 * when importing PRIME buffers. 562 */ 563 dma_set_max_seg_size(dma_dev, UINT_MAX); 564 565 ret = drm_vblank_init(drm, MAX_CRTC); 566 if (ret < 0) 567 goto err_component_unbind; 568 569 drm_kms_helper_poll_init(drm); 570 drm_mode_config_reset(drm); 571 572 return 0; 573 574 err_component_unbind: 575 for (i = 0; i < private->data->mmsys_dev_num; i++) 576 component_unbind_all(private->all_drm_private[i]->dev, drm); 577 put_mutex_dev: 578 for (i = 0; i < private->data->mmsys_dev_num; i++) 579 put_device(private->all_drm_private[i]->mutex_dev); 580 581 return ret; 582 } 583 584 static void mtk_drm_kms_deinit(struct drm_device *drm) 585 { 586 drm_kms_helper_poll_fini(drm); 587 drm_atomic_helper_shutdown(drm); 588 589 component_unbind_all(drm->dev, drm); 590 } 591 592 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 593 594 /* 595 * We need to override this because the device used to import the memory is 596 * not dev->dev, as drm_gem_prime_import() expects. 597 */ 598 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev, 599 struct dma_buf *dma_buf) 600 { 601 struct mtk_drm_private *private = dev->dev_private; 602 603 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 604 } 605 606 static const struct drm_driver mtk_drm_driver = { 607 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 608 609 .dumb_create = mtk_gem_dumb_create, 610 DRM_FBDEV_DMA_DRIVER_OPS, 611 612 .gem_prime_import = mtk_gem_prime_import, 613 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 614 .fops = &mtk_drm_fops, 615 616 .name = DRIVER_NAME, 617 .desc = DRIVER_DESC, 618 .date = DRIVER_DATE, 619 .major = DRIVER_MAJOR, 620 .minor = DRIVER_MINOR, 621 }; 622 623 static int compare_dev(struct device *dev, void *data) 624 { 625 return dev == (struct device *)data; 626 } 627 628 static int mtk_drm_bind(struct device *dev) 629 { 630 struct mtk_drm_private *private = dev_get_drvdata(dev); 631 struct platform_device *pdev; 632 struct drm_device *drm; 633 int ret, i; 634 635 pdev = of_find_device_by_node(private->mutex_node); 636 if (!pdev) { 637 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 638 private->mutex_node); 639 of_node_put(private->mutex_node); 640 return -EPROBE_DEFER; 641 } 642 643 private->mutex_dev = &pdev->dev; 644 private->mtk_drm_bound = true; 645 private->dev = dev; 646 647 if (!mtk_drm_get_all_drm_priv(dev)) 648 return 0; 649 650 drm = drm_dev_alloc(&mtk_drm_driver, dev); 651 if (IS_ERR(drm)) 652 return PTR_ERR(drm); 653 654 private->drm_master = true; 655 drm->dev_private = private; 656 for (i = 0; i < private->data->mmsys_dev_num; i++) 657 private->all_drm_private[i]->drm = drm; 658 659 ret = mtk_drm_kms_init(drm); 660 if (ret < 0) 661 goto err_free; 662 663 ret = drm_dev_register(drm, 0); 664 if (ret < 0) 665 goto err_deinit; 666 667 drm_client_setup(drm, NULL); 668 669 return 0; 670 671 err_deinit: 672 mtk_drm_kms_deinit(drm); 673 err_free: 674 private->drm = NULL; 675 drm_dev_put(drm); 676 return ret; 677 } 678 679 static void mtk_drm_unbind(struct device *dev) 680 { 681 struct mtk_drm_private *private = dev_get_drvdata(dev); 682 683 /* for multi mmsys dev, unregister drm dev in mmsys master */ 684 if (private->drm_master) { 685 drm_dev_unregister(private->drm); 686 mtk_drm_kms_deinit(private->drm); 687 drm_dev_put(private->drm); 688 } 689 private->mtk_drm_bound = false; 690 private->drm_master = false; 691 private->drm = NULL; 692 } 693 694 static const struct component_master_ops mtk_drm_ops = { 695 .bind = mtk_drm_bind, 696 .unbind = mtk_drm_unbind, 697 }; 698 699 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 700 { .compatible = "mediatek,mt8167-disp-aal", 701 .data = (void *)MTK_DISP_AAL}, 702 { .compatible = "mediatek,mt8173-disp-aal", 703 .data = (void *)MTK_DISP_AAL}, 704 { .compatible = "mediatek,mt8183-disp-aal", 705 .data = (void *)MTK_DISP_AAL}, 706 { .compatible = "mediatek,mt8192-disp-aal", 707 .data = (void *)MTK_DISP_AAL}, 708 { .compatible = "mediatek,mt8167-disp-ccorr", 709 .data = (void *)MTK_DISP_CCORR }, 710 { .compatible = "mediatek,mt8183-disp-ccorr", 711 .data = (void *)MTK_DISP_CCORR }, 712 { .compatible = "mediatek,mt8192-disp-ccorr", 713 .data = (void *)MTK_DISP_CCORR }, 714 { .compatible = "mediatek,mt2701-disp-color", 715 .data = (void *)MTK_DISP_COLOR }, 716 { .compatible = "mediatek,mt8167-disp-color", 717 .data = (void *)MTK_DISP_COLOR }, 718 { .compatible = "mediatek,mt8173-disp-color", 719 .data = (void *)MTK_DISP_COLOR }, 720 { .compatible = "mediatek,mt8167-disp-dither", 721 .data = (void *)MTK_DISP_DITHER }, 722 { .compatible = "mediatek,mt8183-disp-dither", 723 .data = (void *)MTK_DISP_DITHER }, 724 { .compatible = "mediatek,mt8195-disp-dsc", 725 .data = (void *)MTK_DISP_DSC }, 726 { .compatible = "mediatek,mt8167-disp-gamma", 727 .data = (void *)MTK_DISP_GAMMA, }, 728 { .compatible = "mediatek,mt8173-disp-gamma", 729 .data = (void *)MTK_DISP_GAMMA, }, 730 { .compatible = "mediatek,mt8183-disp-gamma", 731 .data = (void *)MTK_DISP_GAMMA, }, 732 { .compatible = "mediatek,mt8195-disp-gamma", 733 .data = (void *)MTK_DISP_GAMMA, }, 734 { .compatible = "mediatek,mt8195-disp-merge", 735 .data = (void *)MTK_DISP_MERGE }, 736 { .compatible = "mediatek,mt2701-disp-mutex", 737 .data = (void *)MTK_DISP_MUTEX }, 738 { .compatible = "mediatek,mt2712-disp-mutex", 739 .data = (void *)MTK_DISP_MUTEX }, 740 { .compatible = "mediatek,mt8167-disp-mutex", 741 .data = (void *)MTK_DISP_MUTEX }, 742 { .compatible = "mediatek,mt8173-disp-mutex", 743 .data = (void *)MTK_DISP_MUTEX }, 744 { .compatible = "mediatek,mt8183-disp-mutex", 745 .data = (void *)MTK_DISP_MUTEX }, 746 { .compatible = "mediatek,mt8186-disp-mutex", 747 .data = (void *)MTK_DISP_MUTEX }, 748 { .compatible = "mediatek,mt8188-disp-mutex", 749 .data = (void *)MTK_DISP_MUTEX }, 750 { .compatible = "mediatek,mt8192-disp-mutex", 751 .data = (void *)MTK_DISP_MUTEX }, 752 { .compatible = "mediatek,mt8195-disp-mutex", 753 .data = (void *)MTK_DISP_MUTEX }, 754 { .compatible = "mediatek,mt8173-disp-od", 755 .data = (void *)MTK_DISP_OD }, 756 { .compatible = "mediatek,mt2701-disp-ovl", 757 .data = (void *)MTK_DISP_OVL }, 758 { .compatible = "mediatek,mt8167-disp-ovl", 759 .data = (void *)MTK_DISP_OVL }, 760 { .compatible = "mediatek,mt8173-disp-ovl", 761 .data = (void *)MTK_DISP_OVL }, 762 { .compatible = "mediatek,mt8183-disp-ovl", 763 .data = (void *)MTK_DISP_OVL }, 764 { .compatible = "mediatek,mt8192-disp-ovl", 765 .data = (void *)MTK_DISP_OVL }, 766 { .compatible = "mediatek,mt8195-disp-ovl", 767 .data = (void *)MTK_DISP_OVL }, 768 { .compatible = "mediatek,mt8183-disp-ovl-2l", 769 .data = (void *)MTK_DISP_OVL_2L }, 770 { .compatible = "mediatek,mt8192-disp-ovl-2l", 771 .data = (void *)MTK_DISP_OVL_2L }, 772 { .compatible = "mediatek,mt8192-disp-postmask", 773 .data = (void *)MTK_DISP_POSTMASK }, 774 { .compatible = "mediatek,mt2701-disp-pwm", 775 .data = (void *)MTK_DISP_BLS }, 776 { .compatible = "mediatek,mt8167-disp-pwm", 777 .data = (void *)MTK_DISP_PWM }, 778 { .compatible = "mediatek,mt8173-disp-pwm", 779 .data = (void *)MTK_DISP_PWM }, 780 { .compatible = "mediatek,mt2701-disp-rdma", 781 .data = (void *)MTK_DISP_RDMA }, 782 { .compatible = "mediatek,mt8167-disp-rdma", 783 .data = (void *)MTK_DISP_RDMA }, 784 { .compatible = "mediatek,mt8173-disp-rdma", 785 .data = (void *)MTK_DISP_RDMA }, 786 { .compatible = "mediatek,mt8183-disp-rdma", 787 .data = (void *)MTK_DISP_RDMA }, 788 { .compatible = "mediatek,mt8195-disp-rdma", 789 .data = (void *)MTK_DISP_RDMA }, 790 { .compatible = "mediatek,mt8173-disp-ufoe", 791 .data = (void *)MTK_DISP_UFOE }, 792 { .compatible = "mediatek,mt8173-disp-wdma", 793 .data = (void *)MTK_DISP_WDMA }, 794 { .compatible = "mediatek,mt2701-dpi", 795 .data = (void *)MTK_DPI }, 796 { .compatible = "mediatek,mt8167-dsi", 797 .data = (void *)MTK_DSI }, 798 { .compatible = "mediatek,mt8173-dpi", 799 .data = (void *)MTK_DPI }, 800 { .compatible = "mediatek,mt8183-dpi", 801 .data = (void *)MTK_DPI }, 802 { .compatible = "mediatek,mt8186-dpi", 803 .data = (void *)MTK_DPI }, 804 { .compatible = "mediatek,mt8188-dp-intf", 805 .data = (void *)MTK_DP_INTF }, 806 { .compatible = "mediatek,mt8192-dpi", 807 .data = (void *)MTK_DPI }, 808 { .compatible = "mediatek,mt8195-dp-intf", 809 .data = (void *)MTK_DP_INTF }, 810 { .compatible = "mediatek,mt2701-dsi", 811 .data = (void *)MTK_DSI }, 812 { .compatible = "mediatek,mt8173-dsi", 813 .data = (void *)MTK_DSI }, 814 { .compatible = "mediatek,mt8183-dsi", 815 .data = (void *)MTK_DSI }, 816 { .compatible = "mediatek,mt8186-dsi", 817 .data = (void *)MTK_DSI }, 818 { .compatible = "mediatek,mt8188-dsi", 819 .data = (void *)MTK_DSI }, 820 { } 821 }; 822 823 static int mtk_drm_probe(struct platform_device *pdev) 824 { 825 struct device *dev = &pdev->dev; 826 struct device_node *phandle = dev->parent->of_node; 827 const struct of_device_id *of_id; 828 struct mtk_drm_private *private; 829 struct device_node *node; 830 struct component_match *match = NULL; 831 struct platform_device *ovl_adaptor; 832 int ret; 833 int i; 834 835 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 836 if (!private) 837 return -ENOMEM; 838 839 private->mmsys_dev = dev->parent; 840 if (!private->mmsys_dev) { 841 dev_err(dev, "Failed to get MMSYS device\n"); 842 return -ENODEV; 843 } 844 845 of_id = of_match_node(mtk_drm_of_ids, phandle); 846 if (!of_id) 847 return -ENODEV; 848 849 private->data = of_id->data; 850 851 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 852 sizeof(*private->all_drm_private), 853 GFP_KERNEL); 854 if (!private->all_drm_private) 855 return -ENOMEM; 856 857 /* Bringup ovl_adaptor */ 858 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 859 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 860 PLATFORM_DEVID_AUTO, 861 (void *)private->mmsys_dev, 862 sizeof(*private->mmsys_dev)); 863 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 864 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 865 DDP_COMPONENT_DRM_OVL_ADAPTOR); 866 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 867 } 868 869 /* Iterate over sibling DISP function blocks */ 870 for_each_child_of_node(phandle->parent, node) { 871 const struct of_device_id *of_id; 872 enum mtk_ddp_comp_type comp_type; 873 int comp_id; 874 875 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 876 if (!of_id) 877 continue; 878 879 if (!of_device_is_available(node)) { 880 dev_dbg(dev, "Skipping disabled component %pOF\n", 881 node); 882 continue; 883 } 884 885 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data; 886 887 if (comp_type == MTK_DISP_MUTEX) { 888 int id; 889 890 id = of_alias_get_id(node, "mutex"); 891 if (id < 0 || id == private->data->mmsys_id) { 892 private->mutex_node = of_node_get(node); 893 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 894 } 895 continue; 896 } 897 898 comp_id = mtk_ddp_comp_get_id(node, comp_type); 899 if (comp_id < 0) { 900 dev_warn(dev, "Skipping unknown component %pOF\n", 901 node); 902 continue; 903 } 904 905 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 906 continue; 907 908 private->comp_node[comp_id] = of_node_get(node); 909 910 /* 911 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 912 * blocks have separate component platform drivers and initialize their own 913 * DDP component structure. The others are initialized here. 914 */ 915 if (comp_type == MTK_DISP_AAL || 916 comp_type == MTK_DISP_CCORR || 917 comp_type == MTK_DISP_COLOR || 918 comp_type == MTK_DISP_GAMMA || 919 comp_type == MTK_DISP_MERGE || 920 comp_type == MTK_DISP_OVL || 921 comp_type == MTK_DISP_OVL_2L || 922 comp_type == MTK_DISP_OVL_ADAPTOR || 923 comp_type == MTK_DISP_RDMA || 924 comp_type == MTK_DP_INTF || 925 comp_type == MTK_DPI || 926 comp_type == MTK_DSI) { 927 dev_info(dev, "Adding component match for %pOF\n", 928 node); 929 drm_of_component_match_add(dev, &match, component_compare_of, 930 node); 931 } 932 933 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 934 if (ret) { 935 of_node_put(node); 936 goto err_node; 937 } 938 } 939 940 if (!private->mutex_node) { 941 dev_err(dev, "Failed to find disp-mutex node\n"); 942 ret = -ENODEV; 943 goto err_node; 944 } 945 946 pm_runtime_enable(dev); 947 948 platform_set_drvdata(pdev, private); 949 950 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 951 if (ret) 952 goto err_pm; 953 954 return 0; 955 956 err_pm: 957 pm_runtime_disable(dev); 958 err_node: 959 of_node_put(private->mutex_node); 960 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 961 of_node_put(private->comp_node[i]); 962 return ret; 963 } 964 965 static void mtk_drm_remove(struct platform_device *pdev) 966 { 967 struct mtk_drm_private *private = platform_get_drvdata(pdev); 968 int i; 969 970 component_master_del(&pdev->dev, &mtk_drm_ops); 971 pm_runtime_disable(&pdev->dev); 972 of_node_put(private->mutex_node); 973 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 974 of_node_put(private->comp_node[i]); 975 } 976 977 static void mtk_drm_shutdown(struct platform_device *pdev) 978 { 979 struct mtk_drm_private *private = platform_get_drvdata(pdev); 980 981 drm_atomic_helper_shutdown(private->drm); 982 } 983 984 static int mtk_drm_sys_prepare(struct device *dev) 985 { 986 struct mtk_drm_private *private = dev_get_drvdata(dev); 987 struct drm_device *drm = private->drm; 988 989 if (private->drm_master) 990 return drm_mode_config_helper_suspend(drm); 991 else 992 return 0; 993 } 994 995 static void mtk_drm_sys_complete(struct device *dev) 996 { 997 struct mtk_drm_private *private = dev_get_drvdata(dev); 998 struct drm_device *drm = private->drm; 999 int ret = 0; 1000 1001 if (private->drm_master) 1002 ret = drm_mode_config_helper_resume(drm); 1003 if (ret) 1004 dev_err(dev, "Failed to resume\n"); 1005 } 1006 1007 static const struct dev_pm_ops mtk_drm_pm_ops = { 1008 .prepare = mtk_drm_sys_prepare, 1009 .complete = mtk_drm_sys_complete, 1010 }; 1011 1012 static struct platform_driver mtk_drm_platform_driver = { 1013 .probe = mtk_drm_probe, 1014 .remove_new = mtk_drm_remove, 1015 .shutdown = mtk_drm_shutdown, 1016 .driver = { 1017 .name = "mediatek-drm", 1018 .pm = &mtk_drm_pm_ops, 1019 }, 1020 }; 1021 1022 static struct platform_driver * const mtk_drm_drivers[] = { 1023 &mtk_disp_aal_driver, 1024 &mtk_disp_ccorr_driver, 1025 &mtk_disp_color_driver, 1026 &mtk_disp_gamma_driver, 1027 &mtk_disp_merge_driver, 1028 &mtk_disp_ovl_adaptor_driver, 1029 &mtk_disp_ovl_driver, 1030 &mtk_disp_rdma_driver, 1031 &mtk_dpi_driver, 1032 &mtk_drm_platform_driver, 1033 &mtk_dsi_driver, 1034 &mtk_ethdr_driver, 1035 &mtk_mdp_rdma_driver, 1036 &mtk_padding_driver, 1037 }; 1038 1039 static int __init mtk_drm_init(void) 1040 { 1041 return platform_register_drivers(mtk_drm_drivers, 1042 ARRAY_SIZE(mtk_drm_drivers)); 1043 } 1044 1045 static void __exit mtk_drm_exit(void) 1046 { 1047 platform_unregister_drivers(mtk_drm_drivers, 1048 ARRAY_SIZE(mtk_drm_drivers)); 1049 } 1050 1051 module_init(mtk_drm_init); 1052 module_exit(mtk_drm_exit); 1053 1054 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1055 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1056 MODULE_LICENSE("GPL v2"); 1057