1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/clients/drm_client_setup.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_crtc.h" 29 #include "mtk_ddp_comp.h" 30 #include "mtk_disp_drv.h" 31 #include "mtk_drm_drv.h" 32 #include "mtk_gem.h" 33 34 #define DRIVER_NAME "mediatek" 35 #define DRIVER_DESC "Mediatek SoC DRM" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_format_info *info, 47 const struct drm_mode_fb_cmd2 *cmd) 48 { 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, info, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const unsigned int mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const unsigned int mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const unsigned int mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const unsigned int mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const unsigned int mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const unsigned int mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const unsigned int mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static unsigned int mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER0, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const unsigned int mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const unsigned int mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const unsigned int mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER0, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const unsigned int mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const unsigned int mt8186_mtk_ddp_main[] = { 162 DDP_COMPONENT_OVL0, 163 DDP_COMPONENT_RDMA0, 164 DDP_COMPONENT_COLOR0, 165 DDP_COMPONENT_CCORR, 166 DDP_COMPONENT_AAL0, 167 DDP_COMPONENT_GAMMA, 168 DDP_COMPONENT_POSTMASK0, 169 DDP_COMPONENT_DITHER0, 170 DDP_COMPONENT_DSI0, 171 }; 172 173 static const unsigned int mt8186_mtk_ddp_ext[] = { 174 DDP_COMPONENT_OVL_2L0, 175 DDP_COMPONENT_RDMA1, 176 DDP_COMPONENT_DPI0, 177 }; 178 179 static const unsigned int mt8188_mtk_ddp_main[] = { 180 DDP_COMPONENT_OVL0, 181 DDP_COMPONENT_RDMA0, 182 DDP_COMPONENT_COLOR0, 183 DDP_COMPONENT_CCORR, 184 DDP_COMPONENT_AAL0, 185 DDP_COMPONENT_GAMMA, 186 DDP_COMPONENT_POSTMASK0, 187 DDP_COMPONENT_DITHER0, 188 }; 189 190 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 191 {0, DDP_COMPONENT_DP_INTF0}, 192 {0, DDP_COMPONENT_DSI0}, 193 }; 194 195 static const unsigned int mt8192_mtk_ddp_main[] = { 196 DDP_COMPONENT_OVL0, 197 DDP_COMPONENT_OVL_2L0, 198 DDP_COMPONENT_RDMA0, 199 DDP_COMPONENT_COLOR0, 200 DDP_COMPONENT_CCORR, 201 DDP_COMPONENT_AAL0, 202 DDP_COMPONENT_GAMMA, 203 DDP_COMPONENT_POSTMASK0, 204 DDP_COMPONENT_DITHER0, 205 DDP_COMPONENT_DSI0, 206 }; 207 208 static const unsigned int mt8192_mtk_ddp_ext[] = { 209 DDP_COMPONENT_OVL_2L2, 210 DDP_COMPONENT_RDMA4, 211 DDP_COMPONENT_DPI0, 212 }; 213 214 static const unsigned int mt8195_mtk_ddp_main[] = { 215 DDP_COMPONENT_OVL0, 216 DDP_COMPONENT_RDMA0, 217 DDP_COMPONENT_COLOR0, 218 DDP_COMPONENT_CCORR, 219 DDP_COMPONENT_AAL0, 220 DDP_COMPONENT_GAMMA, 221 DDP_COMPONENT_DITHER0, 222 DDP_COMPONENT_DSC0, 223 DDP_COMPONENT_MERGE0, 224 DDP_COMPONENT_DP_INTF0, 225 }; 226 227 static const unsigned int mt8195_mtk_ddp_ext[] = { 228 DDP_COMPONENT_DRM_OVL_ADAPTOR, 229 DDP_COMPONENT_MERGE5, 230 DDP_COMPONENT_DP_INTF1, 231 }; 232 233 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 234 .main_path = mt2701_mtk_ddp_main, 235 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 236 .ext_path = mt2701_mtk_ddp_ext, 237 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 238 .shadow_register = true, 239 .mmsys_dev_num = 1, 240 }; 241 242 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 243 .main_path = mt7623_mtk_ddp_main, 244 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 245 .ext_path = mt7623_mtk_ddp_ext, 246 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 247 .shadow_register = true, 248 .mmsys_dev_num = 1, 249 }; 250 251 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 252 .main_path = mt2712_mtk_ddp_main, 253 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 254 .ext_path = mt2712_mtk_ddp_ext, 255 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 256 .third_path = mt2712_mtk_ddp_third, 257 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 258 .mmsys_dev_num = 1, 259 }; 260 261 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 262 .main_path = mt8167_mtk_ddp_main, 263 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 264 .mmsys_dev_num = 1, 265 }; 266 267 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 268 .main_path = mt8173_mtk_ddp_main, 269 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 270 .ext_path = mt8173_mtk_ddp_ext, 271 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 272 .mmsys_dev_num = 1, 273 }; 274 275 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 276 .main_path = mt8183_mtk_ddp_main, 277 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 278 .ext_path = mt8183_mtk_ddp_ext, 279 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 280 .mmsys_dev_num = 1, 281 }; 282 283 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 284 .main_path = mt8186_mtk_ddp_main, 285 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 286 .ext_path = mt8186_mtk_ddp_ext, 287 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 288 .mmsys_dev_num = 1, 289 }; 290 291 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 292 .main_path = mt8188_mtk_ddp_main, 293 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 294 .conn_routes = mt8188_mtk_ddp_main_routes, 295 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 296 .mmsys_dev_num = 2, 297 .max_width = 8191, 298 .min_width = 1, 299 .min_height = 1, 300 }; 301 302 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 303 .main_path = mt8192_mtk_ddp_main, 304 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 305 .ext_path = mt8192_mtk_ddp_ext, 306 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 307 .mmsys_dev_num = 1, 308 }; 309 310 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 311 .main_path = mt8195_mtk_ddp_main, 312 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 313 .mmsys_dev_num = 2, 314 .max_width = 8191, 315 .min_width = 1, 316 .min_height = 1, 317 }; 318 319 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 320 .ext_path = mt8195_mtk_ddp_ext, 321 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 322 .mmsys_id = 1, 323 .mmsys_dev_num = 2, 324 .max_width = 8191, 325 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 326 .min_height = 1, 327 }; 328 329 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 330 .mmsys_dev_num = 1, 331 }; 332 333 static const struct of_device_id mtk_drm_of_ids[] = { 334 { .compatible = "mediatek,mt2701-mmsys", 335 .data = &mt2701_mmsys_driver_data}, 336 { .compatible = "mediatek,mt7623-mmsys", 337 .data = &mt7623_mmsys_driver_data}, 338 { .compatible = "mediatek,mt2712-mmsys", 339 .data = &mt2712_mmsys_driver_data}, 340 { .compatible = "mediatek,mt8167-mmsys", 341 .data = &mt8167_mmsys_driver_data}, 342 { .compatible = "mediatek,mt8173-mmsys", 343 .data = &mt8173_mmsys_driver_data}, 344 { .compatible = "mediatek,mt8183-mmsys", 345 .data = &mt8183_mmsys_driver_data}, 346 { .compatible = "mediatek,mt8186-mmsys", 347 .data = &mt8186_mmsys_driver_data}, 348 { .compatible = "mediatek,mt8188-vdosys0", 349 .data = &mt8188_vdosys0_driver_data}, 350 { .compatible = "mediatek,mt8188-vdosys1", 351 .data = &mt8195_vdosys1_driver_data}, 352 { .compatible = "mediatek,mt8192-mmsys", 353 .data = &mt8192_mmsys_driver_data}, 354 { .compatible = "mediatek,mt8195-mmsys", 355 .data = &mt8195_vdosys0_driver_data}, 356 { .compatible = "mediatek,mt8195-vdosys0", 357 .data = &mt8195_vdosys0_driver_data}, 358 { .compatible = "mediatek,mt8195-vdosys1", 359 .data = &mt8195_vdosys1_driver_data}, 360 { .compatible = "mediatek,mt8365-mmsys", 361 .data = &mt8365_mmsys_driver_data}, 362 { } 363 }; 364 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 365 366 static int mtk_drm_match(struct device *dev, const void *data) 367 { 368 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 369 return true; 370 return false; 371 } 372 373 static bool mtk_drm_get_all_drm_priv(struct device *dev) 374 { 375 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 376 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 377 struct mtk_drm_private *temp_drm_priv; 378 struct device_node *phandle = dev->parent->of_node; 379 const struct of_device_id *of_id; 380 struct device_node *node; 381 struct device *drm_dev; 382 unsigned int cnt = 0; 383 int i, j; 384 385 for_each_child_of_node(phandle->parent, node) { 386 struct platform_device *pdev; 387 388 of_id = of_match_node(mtk_drm_of_ids, node); 389 if (!of_id) 390 goto next_put_node; 391 392 pdev = of_find_device_by_node(node); 393 if (!pdev) 394 goto next_put_node; 395 396 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 397 if (!drm_dev) 398 goto next_put_device_pdev_dev; 399 400 temp_drm_priv = dev_get_drvdata(drm_dev); 401 if (!temp_drm_priv) 402 goto next_put_device_drm_dev; 403 404 if (temp_drm_priv->data->main_len) 405 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 406 else if (temp_drm_priv->data->ext_len) 407 all_drm_priv[CRTC_EXT] = temp_drm_priv; 408 else if (temp_drm_priv->data->third_len) 409 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 410 411 if (temp_drm_priv->mtk_drm_bound) 412 cnt++; 413 414 next_put_device_drm_dev: 415 put_device(drm_dev); 416 417 next_put_device_pdev_dev: 418 put_device(&pdev->dev); 419 420 next_put_node: 421 of_node_put(node); 422 423 if (cnt == MAX_CRTC) 424 break; 425 } 426 427 if (drm_priv->data->mmsys_dev_num == cnt) { 428 for (i = 0; i < cnt; i++) 429 for (j = 0; j < cnt; j++) 430 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 431 432 return true; 433 } 434 435 return false; 436 } 437 438 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 439 { 440 const struct mtk_mmsys_driver_data *drv_data = private->data; 441 int i; 442 443 if (drv_data->main_path) 444 for (i = 0; i < drv_data->main_len; i++) 445 if (drv_data->main_path[i] == comp_id) 446 return true; 447 448 if (drv_data->ext_path) 449 for (i = 0; i < drv_data->ext_len; i++) 450 if (drv_data->ext_path[i] == comp_id) 451 return true; 452 453 if (drv_data->third_path) 454 for (i = 0; i < drv_data->third_len; i++) 455 if (drv_data->third_path[i] == comp_id) 456 return true; 457 458 if (drv_data->num_conn_routes) 459 for (i = 0; i < drv_data->num_conn_routes; i++) 460 if (drv_data->conn_routes[i].route_ddp == comp_id) 461 return true; 462 463 return false; 464 } 465 466 static int mtk_drm_kms_init(struct drm_device *drm) 467 { 468 struct mtk_drm_private *private = drm->dev_private; 469 struct mtk_drm_private *priv_n; 470 struct device *dma_dev = NULL; 471 struct drm_crtc *crtc; 472 int ret, i, j; 473 474 if (drm_firmware_drivers_only()) 475 return -ENODEV; 476 477 ret = drmm_mode_config_init(drm); 478 if (ret) 479 return ret; 480 481 drm->mode_config.min_width = 64; 482 drm->mode_config.min_height = 64; 483 484 /* 485 * set max width and height as default value(4096x4096). 486 * this value would be used to check framebuffer size limitation 487 * at drm_mode_addfb(). 488 */ 489 drm->mode_config.max_width = 4096; 490 drm->mode_config.max_height = 4096; 491 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 492 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 493 494 for (i = 0; i < private->data->mmsys_dev_num; i++) { 495 drm->dev_private = private->all_drm_private[i]; 496 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 497 if (ret) { 498 while (--i >= 0) 499 component_unbind_all(private->all_drm_private[i]->dev, drm); 500 return ret; 501 } 502 } 503 504 /* 505 * Ensure internal panels are at the top of the connector list before 506 * crtc creation. 507 */ 508 drm_helper_move_panel_connectors_to_head(drm); 509 510 /* 511 * 1. We currently support two fixed data streams, each optional, 512 * and each statically assigned to a crtc: 513 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 514 * 2. For multi mmsys architecture, crtc path data are located in 515 * different drm private data structures. Loop through crtc index to 516 * create crtc from the main path and then ext_path and finally the 517 * third path. 518 */ 519 for (i = 0; i < MAX_CRTC; i++) { 520 for (j = 0; j < private->data->mmsys_dev_num; j++) { 521 priv_n = private->all_drm_private[j]; 522 523 if (priv_n->data->max_width) 524 drm->mode_config.max_width = priv_n->data->max_width; 525 526 if (priv_n->data->min_width) 527 drm->mode_config.min_width = priv_n->data->min_width; 528 529 if (priv_n->data->min_height) 530 drm->mode_config.min_height = priv_n->data->min_height; 531 532 if (i == CRTC_MAIN && priv_n->data->main_len) { 533 ret = mtk_crtc_create(drm, priv_n->data->main_path, 534 priv_n->data->main_len, j, 535 priv_n->data->conn_routes, 536 priv_n->data->num_conn_routes); 537 if (ret) 538 goto err_component_unbind; 539 540 continue; 541 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 542 ret = mtk_crtc_create(drm, priv_n->data->ext_path, 543 priv_n->data->ext_len, j, NULL, 0); 544 if (ret) 545 goto err_component_unbind; 546 547 continue; 548 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 549 ret = mtk_crtc_create(drm, priv_n->data->third_path, 550 priv_n->data->third_len, j, NULL, 0); 551 if (ret) 552 goto err_component_unbind; 553 554 continue; 555 } 556 } 557 } 558 559 /* IGT will check if the cursor size is configured */ 560 drm->mode_config.cursor_width = 512; 561 drm->mode_config.cursor_height = 512; 562 563 /* Use OVL device for all DMA memory allocations */ 564 crtc = drm_crtc_from_index(drm, 0); 565 if (crtc) 566 dma_dev = mtk_crtc_dma_dev_get(crtc); 567 if (!dma_dev) { 568 ret = -ENODEV; 569 dev_err(drm->dev, "Need at least one OVL device\n"); 570 goto err_component_unbind; 571 } 572 573 for (i = 0; i < private->data->mmsys_dev_num; i++) 574 private->all_drm_private[i]->dma_dev = dma_dev; 575 576 /* 577 * Configure the DMA segment size to make sure we get contiguous IOVA 578 * when importing PRIME buffers. 579 */ 580 dma_set_max_seg_size(dma_dev, UINT_MAX); 581 582 ret = drm_vblank_init(drm, MAX_CRTC); 583 if (ret < 0) 584 goto err_component_unbind; 585 586 drm_kms_helper_poll_init(drm); 587 drm_mode_config_reset(drm); 588 589 return 0; 590 591 err_component_unbind: 592 for (i = 0; i < private->data->mmsys_dev_num; i++) 593 component_unbind_all(private->all_drm_private[i]->dev, drm); 594 595 return ret; 596 } 597 598 static void mtk_drm_kms_deinit(struct drm_device *drm) 599 { 600 drm_kms_helper_poll_fini(drm); 601 drm_atomic_helper_shutdown(drm); 602 603 component_unbind_all(drm->dev, drm); 604 } 605 606 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 607 608 /* 609 * We need to override this because the device used to import the memory is 610 * not dev->dev, as drm_gem_prime_import() expects. 611 */ 612 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev, 613 struct dma_buf *dma_buf) 614 { 615 struct mtk_drm_private *private = dev->dev_private; 616 617 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 618 } 619 620 static const struct drm_driver mtk_drm_driver = { 621 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 622 623 .dumb_create = mtk_gem_dumb_create, 624 DRM_FBDEV_DMA_DRIVER_OPS, 625 626 .gem_prime_import = mtk_gem_prime_import, 627 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 628 .fops = &mtk_drm_fops, 629 630 .name = DRIVER_NAME, 631 .desc = DRIVER_DESC, 632 .major = DRIVER_MAJOR, 633 .minor = DRIVER_MINOR, 634 }; 635 636 static int compare_dev(struct device *dev, void *data) 637 { 638 return dev == (struct device *)data; 639 } 640 641 static int mtk_drm_bind(struct device *dev) 642 { 643 struct mtk_drm_private *private = dev_get_drvdata(dev); 644 struct platform_device *pdev; 645 struct drm_device *drm; 646 int ret, i; 647 648 pdev = of_find_device_by_node(private->mutex_node); 649 if (!pdev) { 650 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 651 private->mutex_node); 652 of_node_put(private->mutex_node); 653 return -EPROBE_DEFER; 654 } 655 656 private->mutex_dev = &pdev->dev; 657 private->mtk_drm_bound = true; 658 private->dev = dev; 659 660 if (!mtk_drm_get_all_drm_priv(dev)) 661 return 0; 662 663 drm = drm_dev_alloc(&mtk_drm_driver, dev); 664 if (IS_ERR(drm)) { 665 ret = PTR_ERR(drm); 666 goto err_put_dev; 667 } 668 669 private->drm_master = true; 670 drm->dev_private = private; 671 for (i = 0; i < private->data->mmsys_dev_num; i++) 672 private->all_drm_private[i]->drm = drm; 673 674 ret = mtk_drm_kms_init(drm); 675 if (ret < 0) 676 goto err_free; 677 678 ret = drm_dev_register(drm, 0); 679 if (ret < 0) 680 goto err_deinit; 681 682 drm_client_setup(drm, NULL); 683 684 return 0; 685 686 err_deinit: 687 mtk_drm_kms_deinit(drm); 688 err_free: 689 private->drm = NULL; 690 drm_dev_put(drm); 691 for (i = 0; i < private->data->mmsys_dev_num; i++) 692 private->all_drm_private[i]->drm = NULL; 693 err_put_dev: 694 for (i = 0; i < private->data->mmsys_dev_num; i++) { 695 /* For device_find_child in mtk_drm_get_all_priv() */ 696 put_device(private->all_drm_private[i]->dev); 697 } 698 put_device(private->mutex_dev); 699 return ret; 700 } 701 702 static void mtk_drm_unbind(struct device *dev) 703 { 704 struct mtk_drm_private *private = dev_get_drvdata(dev); 705 int i; 706 707 /* for multi mmsys dev, unregister drm dev in mmsys master */ 708 if (private->drm_master) { 709 drm_dev_unregister(private->drm); 710 mtk_drm_kms_deinit(private->drm); 711 drm_dev_put(private->drm); 712 713 for (i = 0; i < private->data->mmsys_dev_num; i++) { 714 /* For device_find_child in mtk_drm_get_all_priv() */ 715 put_device(private->all_drm_private[i]->dev); 716 } 717 put_device(private->mutex_dev); 718 } 719 private->mtk_drm_bound = false; 720 private->drm_master = false; 721 private->drm = NULL; 722 } 723 724 static const struct component_master_ops mtk_drm_ops = { 725 .bind = mtk_drm_bind, 726 .unbind = mtk_drm_unbind, 727 }; 728 729 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 730 { .compatible = "mediatek,mt8167-disp-aal", 731 .data = (void *)MTK_DISP_AAL}, 732 { .compatible = "mediatek,mt8173-disp-aal", 733 .data = (void *)MTK_DISP_AAL}, 734 { .compatible = "mediatek,mt8183-disp-aal", 735 .data = (void *)MTK_DISP_AAL}, 736 { .compatible = "mediatek,mt8192-disp-aal", 737 .data = (void *)MTK_DISP_AAL}, 738 { .compatible = "mediatek,mt8167-disp-ccorr", 739 .data = (void *)MTK_DISP_CCORR }, 740 { .compatible = "mediatek,mt8183-disp-ccorr", 741 .data = (void *)MTK_DISP_CCORR }, 742 { .compatible = "mediatek,mt8192-disp-ccorr", 743 .data = (void *)MTK_DISP_CCORR }, 744 { .compatible = "mediatek,mt2701-disp-color", 745 .data = (void *)MTK_DISP_COLOR }, 746 { .compatible = "mediatek,mt8167-disp-color", 747 .data = (void *)MTK_DISP_COLOR }, 748 { .compatible = "mediatek,mt8173-disp-color", 749 .data = (void *)MTK_DISP_COLOR }, 750 { .compatible = "mediatek,mt8167-disp-dither", 751 .data = (void *)MTK_DISP_DITHER }, 752 { .compatible = "mediatek,mt8183-disp-dither", 753 .data = (void *)MTK_DISP_DITHER }, 754 { .compatible = "mediatek,mt8195-disp-dsc", 755 .data = (void *)MTK_DISP_DSC }, 756 { .compatible = "mediatek,mt8167-disp-gamma", 757 .data = (void *)MTK_DISP_GAMMA, }, 758 { .compatible = "mediatek,mt8173-disp-gamma", 759 .data = (void *)MTK_DISP_GAMMA, }, 760 { .compatible = "mediatek,mt8183-disp-gamma", 761 .data = (void *)MTK_DISP_GAMMA, }, 762 { .compatible = "mediatek,mt8195-disp-gamma", 763 .data = (void *)MTK_DISP_GAMMA, }, 764 { .compatible = "mediatek,mt8195-disp-merge", 765 .data = (void *)MTK_DISP_MERGE }, 766 { .compatible = "mediatek,mt2701-disp-mutex", 767 .data = (void *)MTK_DISP_MUTEX }, 768 { .compatible = "mediatek,mt2712-disp-mutex", 769 .data = (void *)MTK_DISP_MUTEX }, 770 { .compatible = "mediatek,mt8167-disp-mutex", 771 .data = (void *)MTK_DISP_MUTEX }, 772 { .compatible = "mediatek,mt8173-disp-mutex", 773 .data = (void *)MTK_DISP_MUTEX }, 774 { .compatible = "mediatek,mt8183-disp-mutex", 775 .data = (void *)MTK_DISP_MUTEX }, 776 { .compatible = "mediatek,mt8186-disp-mutex", 777 .data = (void *)MTK_DISP_MUTEX }, 778 { .compatible = "mediatek,mt8188-disp-mutex", 779 .data = (void *)MTK_DISP_MUTEX }, 780 { .compatible = "mediatek,mt8192-disp-mutex", 781 .data = (void *)MTK_DISP_MUTEX }, 782 { .compatible = "mediatek,mt8195-disp-mutex", 783 .data = (void *)MTK_DISP_MUTEX }, 784 { .compatible = "mediatek,mt8365-disp-mutex", 785 .data = (void *)MTK_DISP_MUTEX }, 786 { .compatible = "mediatek,mt8173-disp-od", 787 .data = (void *)MTK_DISP_OD }, 788 { .compatible = "mediatek,mt2701-disp-ovl", 789 .data = (void *)MTK_DISP_OVL }, 790 { .compatible = "mediatek,mt8167-disp-ovl", 791 .data = (void *)MTK_DISP_OVL }, 792 { .compatible = "mediatek,mt8173-disp-ovl", 793 .data = (void *)MTK_DISP_OVL }, 794 { .compatible = "mediatek,mt8183-disp-ovl", 795 .data = (void *)MTK_DISP_OVL }, 796 { .compatible = "mediatek,mt8192-disp-ovl", 797 .data = (void *)MTK_DISP_OVL }, 798 { .compatible = "mediatek,mt8195-disp-ovl", 799 .data = (void *)MTK_DISP_OVL }, 800 { .compatible = "mediatek,mt8183-disp-ovl-2l", 801 .data = (void *)MTK_DISP_OVL_2L }, 802 { .compatible = "mediatek,mt8192-disp-ovl-2l", 803 .data = (void *)MTK_DISP_OVL_2L }, 804 { .compatible = "mediatek,mt8192-disp-postmask", 805 .data = (void *)MTK_DISP_POSTMASK }, 806 { .compatible = "mediatek,mt2701-disp-pwm", 807 .data = (void *)MTK_DISP_BLS }, 808 { .compatible = "mediatek,mt8167-disp-pwm", 809 .data = (void *)MTK_DISP_PWM }, 810 { .compatible = "mediatek,mt8173-disp-pwm", 811 .data = (void *)MTK_DISP_PWM }, 812 { .compatible = "mediatek,mt2701-disp-rdma", 813 .data = (void *)MTK_DISP_RDMA }, 814 { .compatible = "mediatek,mt8167-disp-rdma", 815 .data = (void *)MTK_DISP_RDMA }, 816 { .compatible = "mediatek,mt8173-disp-rdma", 817 .data = (void *)MTK_DISP_RDMA }, 818 { .compatible = "mediatek,mt8183-disp-rdma", 819 .data = (void *)MTK_DISP_RDMA }, 820 { .compatible = "mediatek,mt8195-disp-rdma", 821 .data = (void *)MTK_DISP_RDMA }, 822 { .compatible = "mediatek,mt8173-disp-ufoe", 823 .data = (void *)MTK_DISP_UFOE }, 824 { .compatible = "mediatek,mt8173-disp-wdma", 825 .data = (void *)MTK_DISP_WDMA }, 826 { .compatible = "mediatek,mt2701-dpi", 827 .data = (void *)MTK_DPI }, 828 { .compatible = "mediatek,mt8167-dsi", 829 .data = (void *)MTK_DSI }, 830 { .compatible = "mediatek,mt8173-dpi", 831 .data = (void *)MTK_DPI }, 832 { .compatible = "mediatek,mt8183-dpi", 833 .data = (void *)MTK_DPI }, 834 { .compatible = "mediatek,mt8186-dpi", 835 .data = (void *)MTK_DPI }, 836 { .compatible = "mediatek,mt8188-dp-intf", 837 .data = (void *)MTK_DP_INTF }, 838 { .compatible = "mediatek,mt8192-dpi", 839 .data = (void *)MTK_DPI }, 840 { .compatible = "mediatek,mt8195-dp-intf", 841 .data = (void *)MTK_DP_INTF }, 842 { .compatible = "mediatek,mt8195-dpi", 843 .data = (void *)MTK_DPI }, 844 { .compatible = "mediatek,mt2701-dsi", 845 .data = (void *)MTK_DSI }, 846 { .compatible = "mediatek,mt8173-dsi", 847 .data = (void *)MTK_DSI }, 848 { .compatible = "mediatek,mt8183-dsi", 849 .data = (void *)MTK_DSI }, 850 { .compatible = "mediatek,mt8186-dsi", 851 .data = (void *)MTK_DSI }, 852 { .compatible = "mediatek,mt8188-dsi", 853 .data = (void *)MTK_DSI }, 854 { } 855 }; 856 857 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype) 858 { 859 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 860 861 if (!of_id) 862 return -EINVAL; 863 864 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data); 865 866 return 0; 867 } 868 869 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, 870 int output_port, enum mtk_crtc_path crtc_path, 871 struct device_node **next, unsigned int *cid) 872 { 873 struct device_node *ep_dev_node, *ep_out; 874 enum mtk_ddp_comp_type comp_type; 875 int ret; 876 877 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path); 878 if (!ep_out) 879 return -ENOENT; 880 881 ep_dev_node = of_graph_get_remote_port_parent(ep_out); 882 of_node_put(ep_out); 883 if (!ep_dev_node) 884 return -EINVAL; 885 886 /* 887 * Pass the next node pointer regardless of failures in the later code 888 * so that if this function is called in a loop it will walk through all 889 * of the subsequent endpoints anyway. 890 */ 891 *next = ep_dev_node; 892 893 if (!of_device_is_available(ep_dev_node)) 894 return -ENODEV; 895 896 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); 897 if (ret) { 898 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { 899 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR; 900 return 0; 901 } 902 return ret; 903 } 904 905 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type); 906 if (ret < 0) 907 return ret; 908 909 /* All ok! Pass the Component ID to the caller. */ 910 *cid = (unsigned int)ret; 911 912 return 0; 913 } 914 915 /** 916 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path 917 * @dev: The mediatek-drm device 918 * @cpath: CRTC Path relative to a VDO or MMSYS 919 * @out_path: Pointer to an array that will contain the new pipeline 920 * @out_path_len: Number of entries in the pipeline array 921 * 922 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending 923 * on the board-specific desired display configuration; this function walks 924 * through all of the output endpoints starting from a VDO or MMSYS hardware 925 * instance and builds the right pipeline as specified in device trees. 926 * 927 * Return: 928 * * %0 - Display HW Pipeline successfully built and validated 929 * * %-ENOENT - Display pipeline was not specified in device tree 930 * * %-EINVAL - Display pipeline built but validation failed 931 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller 932 */ 933 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath, 934 const unsigned int **out_path, 935 unsigned int *out_path_len) 936 { 937 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node; 938 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 }; 939 unsigned int *final_ddp_path; 940 unsigned short int idx = 0; 941 bool ovl_adaptor_comp_added = false; 942 int ret; 943 944 /* Get the first entry for the temp_path array */ 945 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); 946 if (ret) { 947 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 948 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); 949 ovl_adaptor_comp_added = true; 950 } else { 951 if (next) 952 dev_err(dev, "Invalid component %pOF\n", next); 953 else 954 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath); 955 956 return ret; 957 } 958 } 959 idx++; 960 961 /* 962 * Walk through port outputs until we reach the last valid mediatek-drm component. 963 * To be valid, this must end with an "invalid" component that is a display node. 964 */ 965 do { 966 prev = next; 967 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]); 968 of_node_put(prev); 969 if (ret) { 970 of_node_put(next); 971 break; 972 } 973 974 /* 975 * If this is an OVL adaptor exclusive component and one of those 976 * was already added, don't add another instance of the generic 977 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether 978 * to probe that component master driver of which only one instance 979 * is needed and possible. 980 */ 981 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 982 if (!ovl_adaptor_comp_added) 983 ovl_adaptor_comp_added = true; 984 else 985 idx--; 986 } 987 } while (++idx < DDP_COMPONENT_DRM_ID_MAX); 988 989 /* 990 * The device component might not be enabled: in that case, don't 991 * check the last entry and just report that the device is missing. 992 */ 993 if (ret == -ENODEV) 994 return ret; 995 996 /* If the last entry is not a final display output, the configuration is wrong */ 997 switch (temp_path[idx - 1]) { 998 case DDP_COMPONENT_DP_INTF0: 999 case DDP_COMPONENT_DP_INTF1: 1000 case DDP_COMPONENT_DPI0: 1001 case DDP_COMPONENT_DPI1: 1002 case DDP_COMPONENT_DSI0: 1003 case DDP_COMPONENT_DSI1: 1004 case DDP_COMPONENT_DSI2: 1005 case DDP_COMPONENT_DSI3: 1006 break; 1007 default: 1008 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n", 1009 temp_path[idx - 1], ret); 1010 return -EINVAL; 1011 } 1012 1013 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL); 1014 if (!final_ddp_path) 1015 return -ENOMEM; 1016 1017 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx); 1018 1019 /* Pipeline built! */ 1020 *out_path = final_ddp_path; 1021 *out_path_len = idx; 1022 1023 return 0; 1024 } 1025 1026 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node, 1027 struct mtk_mmsys_driver_data *data) 1028 { 1029 struct device_node *ep_node; 1030 struct of_endpoint of_ep; 1031 bool output_present[MAX_CRTC] = { false }; 1032 int ret; 1033 1034 for_each_endpoint_of_node(node, ep_node) { 1035 ret = of_graph_parse_endpoint(ep_node, &of_ep); 1036 if (ret) { 1037 dev_err_probe(dev, ret, "Cannot parse endpoint\n"); 1038 break; 1039 } 1040 1041 if (of_ep.id >= MAX_CRTC) { 1042 ret = dev_err_probe(dev, -EINVAL, 1043 "Invalid endpoint%u number\n", of_ep.port); 1044 break; 1045 } 1046 1047 output_present[of_ep.id] = true; 1048 } 1049 1050 if (ret) { 1051 of_node_put(ep_node); 1052 return ret; 1053 } 1054 1055 if (output_present[CRTC_MAIN]) { 1056 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN, 1057 &data->main_path, &data->main_len); 1058 if (ret && ret != -ENODEV) 1059 return ret; 1060 } 1061 1062 if (output_present[CRTC_EXT]) { 1063 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT, 1064 &data->ext_path, &data->ext_len); 1065 if (ret && ret != -ENODEV) 1066 return ret; 1067 } 1068 1069 if (output_present[CRTC_THIRD]) { 1070 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD, 1071 &data->third_path, &data->third_len); 1072 if (ret && ret != -ENODEV) 1073 return ret; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static int mtk_drm_probe(struct platform_device *pdev) 1080 { 1081 struct device *dev = &pdev->dev; 1082 struct device_node *phandle = dev->parent->of_node; 1083 const struct of_device_id *of_id; 1084 struct mtk_drm_private *private; 1085 struct mtk_mmsys_driver_data *mtk_drm_data; 1086 struct device_node *node; 1087 struct component_match *match = NULL; 1088 struct platform_device *ovl_adaptor; 1089 int ret; 1090 int i; 1091 1092 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 1093 if (!private) 1094 return -ENOMEM; 1095 1096 private->mmsys_dev = dev->parent; 1097 if (!private->mmsys_dev) { 1098 dev_err(dev, "Failed to get MMSYS device\n"); 1099 return -ENODEV; 1100 } 1101 1102 of_id = of_match_node(mtk_drm_of_ids, phandle); 1103 if (!of_id) 1104 return -ENODEV; 1105 1106 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data; 1107 if (!mtk_drm_data) 1108 return -EINVAL; 1109 1110 /* Try to build the display pipeline from devicetree graphs */ 1111 if (of_graph_is_present(phandle)) { 1112 dev_dbg(dev, "Building display pipeline for MMSYS %u\n", 1113 mtk_drm_data->mmsys_id); 1114 private->data = devm_kmemdup(dev, mtk_drm_data, 1115 sizeof(*mtk_drm_data), GFP_KERNEL); 1116 if (!private->data) 1117 return -ENOMEM; 1118 1119 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data); 1120 if (ret) 1121 return ret; 1122 } else { 1123 /* No devicetree graphs support: go with hardcoded paths if present */ 1124 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id); 1125 private->data = mtk_drm_data; 1126 } 1127 1128 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 1129 sizeof(*private->all_drm_private), 1130 GFP_KERNEL); 1131 if (!private->all_drm_private) 1132 return -ENOMEM; 1133 1134 /* Bringup ovl_adaptor */ 1135 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 1136 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 1137 PLATFORM_DEVID_AUTO, 1138 (void *)private->mmsys_dev, 1139 sizeof(*private->mmsys_dev)); 1140 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 1141 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 1142 DDP_COMPONENT_DRM_OVL_ADAPTOR); 1143 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 1144 } 1145 1146 /* Iterate over sibling DISP function blocks */ 1147 for_each_child_of_node(phandle->parent, node) { 1148 enum mtk_ddp_comp_type comp_type; 1149 int comp_id; 1150 1151 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type); 1152 if (ret) 1153 continue; 1154 1155 if (!of_device_is_available(node)) { 1156 dev_dbg(dev, "Skipping disabled component %pOF\n", 1157 node); 1158 continue; 1159 } 1160 1161 if (comp_type == MTK_DISP_MUTEX) { 1162 int id; 1163 1164 id = of_alias_get_id(node, "mutex"); 1165 if (id < 0 || id == private->data->mmsys_id) { 1166 private->mutex_node = of_node_get(node); 1167 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 1168 } 1169 continue; 1170 } 1171 1172 comp_id = mtk_ddp_comp_get_id(node, comp_type); 1173 if (comp_id < 0) { 1174 dev_warn(dev, "Skipping unknown component %pOF\n", 1175 node); 1176 continue; 1177 } 1178 1179 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 1180 continue; 1181 1182 private->comp_node[comp_id] = of_node_get(node); 1183 1184 /* 1185 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 1186 * blocks have separate component platform drivers and initialize their own 1187 * DDP component structure. The others are initialized here. 1188 */ 1189 if (comp_type == MTK_DISP_AAL || 1190 comp_type == MTK_DISP_CCORR || 1191 comp_type == MTK_DISP_COLOR || 1192 comp_type == MTK_DISP_GAMMA || 1193 comp_type == MTK_DISP_MERGE || 1194 comp_type == MTK_DISP_OVL || 1195 comp_type == MTK_DISP_OVL_2L || 1196 comp_type == MTK_DISP_OVL_ADAPTOR || 1197 comp_type == MTK_DISP_RDMA || 1198 comp_type == MTK_DP_INTF || 1199 comp_type == MTK_DPI || 1200 comp_type == MTK_DSI) { 1201 dev_info(dev, "Adding component match for %pOF\n", 1202 node); 1203 drm_of_component_match_add(dev, &match, component_compare_of, 1204 node); 1205 } 1206 1207 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 1208 if (ret) { 1209 of_node_put(node); 1210 goto err_node; 1211 } 1212 } 1213 1214 if (!private->mutex_node) { 1215 dev_err(dev, "Failed to find disp-mutex node\n"); 1216 ret = -ENODEV; 1217 goto err_node; 1218 } 1219 1220 pm_runtime_enable(dev); 1221 1222 platform_set_drvdata(pdev, private); 1223 1224 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 1225 if (ret) 1226 goto err_pm; 1227 1228 return 0; 1229 1230 err_pm: 1231 pm_runtime_disable(dev); 1232 err_node: 1233 of_node_put(private->mutex_node); 1234 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1235 of_node_put(private->comp_node[i]); 1236 return ret; 1237 } 1238 1239 static void mtk_drm_remove(struct platform_device *pdev) 1240 { 1241 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1242 int i; 1243 1244 component_master_del(&pdev->dev, &mtk_drm_ops); 1245 pm_runtime_disable(&pdev->dev); 1246 of_node_put(private->mutex_node); 1247 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1248 of_node_put(private->comp_node[i]); 1249 } 1250 1251 static void mtk_drm_shutdown(struct platform_device *pdev) 1252 { 1253 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1254 1255 drm_atomic_helper_shutdown(private->drm); 1256 } 1257 1258 static int mtk_drm_sys_prepare(struct device *dev) 1259 { 1260 struct mtk_drm_private *private = dev_get_drvdata(dev); 1261 struct drm_device *drm = private->drm; 1262 1263 if (private->drm_master) 1264 return drm_mode_config_helper_suspend(drm); 1265 else 1266 return 0; 1267 } 1268 1269 static void mtk_drm_sys_complete(struct device *dev) 1270 { 1271 struct mtk_drm_private *private = dev_get_drvdata(dev); 1272 struct drm_device *drm = private->drm; 1273 int ret = 0; 1274 1275 if (private->drm_master) 1276 ret = drm_mode_config_helper_resume(drm); 1277 if (ret) 1278 dev_err(dev, "Failed to resume\n"); 1279 } 1280 1281 static const struct dev_pm_ops mtk_drm_pm_ops = { 1282 .prepare = mtk_drm_sys_prepare, 1283 .complete = mtk_drm_sys_complete, 1284 }; 1285 1286 static struct platform_driver mtk_drm_platform_driver = { 1287 .probe = mtk_drm_probe, 1288 .remove = mtk_drm_remove, 1289 .shutdown = mtk_drm_shutdown, 1290 .driver = { 1291 .name = "mediatek-drm", 1292 .pm = &mtk_drm_pm_ops, 1293 }, 1294 }; 1295 1296 static struct platform_driver * const mtk_drm_drivers[] = { 1297 &mtk_disp_aal_driver, 1298 &mtk_disp_ccorr_driver, 1299 &mtk_disp_color_driver, 1300 &mtk_disp_gamma_driver, 1301 &mtk_disp_merge_driver, 1302 &mtk_disp_ovl_adaptor_driver, 1303 &mtk_disp_ovl_driver, 1304 &mtk_disp_rdma_driver, 1305 &mtk_dpi_driver, 1306 &mtk_drm_platform_driver, 1307 &mtk_dsi_driver, 1308 &mtk_ethdr_driver, 1309 &mtk_mdp_rdma_driver, 1310 &mtk_padding_driver, 1311 }; 1312 1313 static int __init mtk_drm_init(void) 1314 { 1315 return platform_register_drivers(mtk_drm_drivers, 1316 ARRAY_SIZE(mtk_drm_drivers)); 1317 } 1318 1319 static void __exit mtk_drm_exit(void) 1320 { 1321 platform_unregister_drivers(mtk_drm_drivers, 1322 ARRAY_SIZE(mtk_drm_drivers)); 1323 } 1324 1325 module_init(mtk_drm_init); 1326 module_exit(mtk_drm_exit); 1327 1328 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1329 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1330 MODULE_LICENSE("GPL v2"); 1331