1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fb_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "mtk_drm_crtc.h" 28 #include "mtk_drm_ddp_comp.h" 29 #include "mtk_drm_drv.h" 30 #include "mtk_drm_gem.h" 31 32 #define DRIVER_NAME "mediatek" 33 #define DRIVER_DESC "Mediatek SoC DRM" 34 #define DRIVER_DATE "20150513" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 38 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 39 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 40 }; 41 42 static struct drm_framebuffer * 43 mtk_drm_mode_fb_create(struct drm_device *dev, 44 struct drm_file *file, 45 const struct drm_mode_fb_cmd2 *cmd) 46 { 47 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 48 49 if (info->num_planes != 1) 50 return ERR_PTR(-EINVAL); 51 52 return drm_gem_fb_create(dev, file, cmd); 53 } 54 55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 56 .fb_create = mtk_drm_mode_fb_create, 57 .atomic_check = drm_atomic_helper_check, 58 .atomic_commit = drm_atomic_helper_commit, 59 }; 60 61 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 62 DDP_COMPONENT_OVL0, 63 DDP_COMPONENT_RDMA0, 64 DDP_COMPONENT_COLOR0, 65 DDP_COMPONENT_BLS, 66 DDP_COMPONENT_DSI0, 67 }; 68 69 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 70 DDP_COMPONENT_RDMA1, 71 DDP_COMPONENT_DPI0, 72 }; 73 74 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = { 75 DDP_COMPONENT_OVL0, 76 DDP_COMPONENT_RDMA0, 77 DDP_COMPONENT_COLOR0, 78 DDP_COMPONENT_BLS, 79 DDP_COMPONENT_DPI0, 80 }; 81 82 static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = { 83 DDP_COMPONENT_RDMA1, 84 DDP_COMPONENT_DSI0, 85 }; 86 87 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 88 DDP_COMPONENT_OVL0, 89 DDP_COMPONENT_COLOR0, 90 DDP_COMPONENT_AAL0, 91 DDP_COMPONENT_OD0, 92 DDP_COMPONENT_RDMA0, 93 DDP_COMPONENT_DPI0, 94 DDP_COMPONENT_PWM0, 95 }; 96 97 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 98 DDP_COMPONENT_OVL1, 99 DDP_COMPONENT_COLOR1, 100 DDP_COMPONENT_AAL1, 101 DDP_COMPONENT_OD1, 102 DDP_COMPONENT_RDMA1, 103 DDP_COMPONENT_DPI1, 104 DDP_COMPONENT_PWM1, 105 }; 106 107 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 108 DDP_COMPONENT_RDMA2, 109 DDP_COMPONENT_DSI3, 110 DDP_COMPONENT_PWM2, 111 }; 112 113 static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = { 114 DDP_COMPONENT_OVL0, 115 DDP_COMPONENT_COLOR0, 116 DDP_COMPONENT_CCORR, 117 DDP_COMPONENT_AAL0, 118 DDP_COMPONENT_GAMMA, 119 DDP_COMPONENT_DITHER, 120 DDP_COMPONENT_RDMA0, 121 DDP_COMPONENT_DSI0, 122 }; 123 124 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 125 DDP_COMPONENT_OVL0, 126 DDP_COMPONENT_COLOR0, 127 DDP_COMPONENT_AAL0, 128 DDP_COMPONENT_OD0, 129 DDP_COMPONENT_RDMA0, 130 DDP_COMPONENT_UFOE, 131 DDP_COMPONENT_DSI0, 132 DDP_COMPONENT_PWM0, 133 }; 134 135 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 136 DDP_COMPONENT_OVL1, 137 DDP_COMPONENT_COLOR1, 138 DDP_COMPONENT_GAMMA, 139 DDP_COMPONENT_RDMA1, 140 DDP_COMPONENT_DPI0, 141 }; 142 143 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { 144 DDP_COMPONENT_OVL0, 145 DDP_COMPONENT_OVL_2L0, 146 DDP_COMPONENT_RDMA0, 147 DDP_COMPONENT_COLOR0, 148 DDP_COMPONENT_CCORR, 149 DDP_COMPONENT_AAL0, 150 DDP_COMPONENT_GAMMA, 151 DDP_COMPONENT_DITHER, 152 DDP_COMPONENT_DSI0, 153 }; 154 155 static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { 156 DDP_COMPONENT_OVL_2L1, 157 DDP_COMPONENT_RDMA1, 158 DDP_COMPONENT_DPI0, 159 }; 160 161 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { 162 DDP_COMPONENT_OVL0, 163 DDP_COMPONENT_OVL_2L0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L2, 176 DDP_COMPONENT_RDMA4, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 181 .main_path = mt2701_mtk_ddp_main, 182 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 183 .ext_path = mt2701_mtk_ddp_ext, 184 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 185 .shadow_register = true, 186 }; 187 188 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 189 .main_path = mt7623_mtk_ddp_main, 190 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 191 .ext_path = mt7623_mtk_ddp_ext, 192 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 193 .shadow_register = true, 194 }; 195 196 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 197 .main_path = mt2712_mtk_ddp_main, 198 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 199 .ext_path = mt2712_mtk_ddp_ext, 200 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 201 .third_path = mt2712_mtk_ddp_third, 202 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 203 }; 204 205 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 206 .main_path = mt8167_mtk_ddp_main, 207 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 208 }; 209 210 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 211 .main_path = mt8173_mtk_ddp_main, 212 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 213 .ext_path = mt8173_mtk_ddp_ext, 214 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 215 }; 216 217 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 218 .main_path = mt8183_mtk_ddp_main, 219 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 220 .ext_path = mt8183_mtk_ddp_ext, 221 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 222 }; 223 224 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 225 .main_path = mt8192_mtk_ddp_main, 226 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 227 .ext_path = mt8192_mtk_ddp_ext, 228 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 229 }; 230 231 static int mtk_drm_kms_init(struct drm_device *drm) 232 { 233 struct mtk_drm_private *private = drm->dev_private; 234 struct platform_device *pdev; 235 struct device_node *np; 236 struct device *dma_dev; 237 int ret; 238 239 if (!iommu_present(&platform_bus_type)) 240 return -EPROBE_DEFER; 241 242 pdev = of_find_device_by_node(private->mutex_node); 243 if (!pdev) { 244 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 245 private->mutex_node); 246 of_node_put(private->mutex_node); 247 return -EPROBE_DEFER; 248 } 249 private->mutex_dev = &pdev->dev; 250 251 ret = drmm_mode_config_init(drm); 252 if (ret) 253 goto put_mutex_dev; 254 255 drm->mode_config.min_width = 64; 256 drm->mode_config.min_height = 64; 257 258 /* 259 * set max width and height as default value(4096x4096). 260 * this value would be used to check framebuffer size limitation 261 * at drm_mode_addfb(). 262 */ 263 drm->mode_config.max_width = 4096; 264 drm->mode_config.max_height = 4096; 265 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 266 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 267 268 ret = component_bind_all(drm->dev, drm); 269 if (ret) 270 goto put_mutex_dev; 271 272 /* 273 * We currently support two fixed data streams, each optional, 274 * and each statically assigned to a crtc: 275 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 276 */ 277 ret = mtk_drm_crtc_create(drm, private->data->main_path, 278 private->data->main_len); 279 if (ret < 0) 280 goto err_component_unbind; 281 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 282 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 283 private->data->ext_len); 284 if (ret < 0) 285 goto err_component_unbind; 286 287 ret = mtk_drm_crtc_create(drm, private->data->third_path, 288 private->data->third_len); 289 if (ret < 0) 290 goto err_component_unbind; 291 292 /* Use OVL device for all DMA memory allocations */ 293 np = private->comp_node[private->data->main_path[0]] ?: 294 private->comp_node[private->data->ext_path[0]]; 295 pdev = of_find_device_by_node(np); 296 if (!pdev) { 297 ret = -ENODEV; 298 dev_err(drm->dev, "Need at least one OVL device\n"); 299 goto err_component_unbind; 300 } 301 302 dma_dev = &pdev->dev; 303 private->dma_dev = dma_dev; 304 305 /* 306 * Configure the DMA segment size to make sure we get contiguous IOVA 307 * when importing PRIME buffers. 308 */ 309 ret = dma_set_max_seg_size(dma_dev, UINT_MAX); 310 if (ret) { 311 dev_err(dma_dev, "Failed to set DMA segment size\n"); 312 goto err_component_unbind; 313 } 314 315 ret = drm_vblank_init(drm, MAX_CRTC); 316 if (ret < 0) 317 goto err_component_unbind; 318 319 drm_kms_helper_poll_init(drm); 320 drm_mode_config_reset(drm); 321 322 return 0; 323 324 err_component_unbind: 325 component_unbind_all(drm->dev, drm); 326 put_mutex_dev: 327 put_device(private->mutex_dev); 328 return ret; 329 } 330 331 static void mtk_drm_kms_deinit(struct drm_device *drm) 332 { 333 drm_kms_helper_poll_fini(drm); 334 drm_atomic_helper_shutdown(drm); 335 336 component_unbind_all(drm->dev, drm); 337 } 338 339 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 340 341 /* 342 * We need to override this because the device used to import the memory is 343 * not dev->dev, as drm_gem_prime_import() expects. 344 */ 345 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 346 struct dma_buf *dma_buf) 347 { 348 struct mtk_drm_private *private = dev->dev_private; 349 350 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 351 } 352 353 static const struct drm_driver mtk_drm_driver = { 354 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 355 356 .dumb_create = mtk_drm_gem_dumb_create, 357 358 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 359 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 360 .gem_prime_import = mtk_drm_gem_prime_import, 361 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 362 .gem_prime_mmap = drm_gem_prime_mmap, 363 .fops = &mtk_drm_fops, 364 365 .name = DRIVER_NAME, 366 .desc = DRIVER_DESC, 367 .date = DRIVER_DATE, 368 .major = DRIVER_MAJOR, 369 .minor = DRIVER_MINOR, 370 }; 371 372 static int mtk_drm_bind(struct device *dev) 373 { 374 struct mtk_drm_private *private = dev_get_drvdata(dev); 375 struct drm_device *drm; 376 int ret; 377 378 drm = drm_dev_alloc(&mtk_drm_driver, dev); 379 if (IS_ERR(drm)) 380 return PTR_ERR(drm); 381 382 drm->dev_private = private; 383 private->drm = drm; 384 385 ret = mtk_drm_kms_init(drm); 386 if (ret < 0) 387 goto err_free; 388 389 ret = drm_dev_register(drm, 0); 390 if (ret < 0) 391 goto err_deinit; 392 393 drm_fbdev_generic_setup(drm, 32); 394 395 return 0; 396 397 err_deinit: 398 mtk_drm_kms_deinit(drm); 399 err_free: 400 drm_dev_put(drm); 401 return ret; 402 } 403 404 static void mtk_drm_unbind(struct device *dev) 405 { 406 struct mtk_drm_private *private = dev_get_drvdata(dev); 407 408 drm_dev_unregister(private->drm); 409 mtk_drm_kms_deinit(private->drm); 410 drm_dev_put(private->drm); 411 private->num_pipes = 0; 412 private->drm = NULL; 413 } 414 415 static const struct component_master_ops mtk_drm_ops = { 416 .bind = mtk_drm_bind, 417 .unbind = mtk_drm_unbind, 418 }; 419 420 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 421 { .compatible = "mediatek,mt8167-disp-aal", 422 .data = (void *)MTK_DISP_AAL}, 423 { .compatible = "mediatek,mt8173-disp-aal", 424 .data = (void *)MTK_DISP_AAL}, 425 { .compatible = "mediatek,mt8183-disp-aal", 426 .data = (void *)MTK_DISP_AAL}, 427 { .compatible = "mediatek,mt8192-disp-aal", 428 .data = (void *)MTK_DISP_AAL}, 429 { .compatible = "mediatek,mt8167-disp-ccorr", 430 .data = (void *)MTK_DISP_CCORR }, 431 { .compatible = "mediatek,mt8183-disp-ccorr", 432 .data = (void *)MTK_DISP_CCORR }, 433 { .compatible = "mediatek,mt8192-disp-ccorr", 434 .data = (void *)MTK_DISP_CCORR }, 435 { .compatible = "mediatek,mt2701-disp-color", 436 .data = (void *)MTK_DISP_COLOR }, 437 { .compatible = "mediatek,mt8167-disp-color", 438 .data = (void *)MTK_DISP_COLOR }, 439 { .compatible = "mediatek,mt8173-disp-color", 440 .data = (void *)MTK_DISP_COLOR }, 441 { .compatible = "mediatek,mt8167-disp-dither", 442 .data = (void *)MTK_DISP_DITHER }, 443 { .compatible = "mediatek,mt8183-disp-dither", 444 .data = (void *)MTK_DISP_DITHER }, 445 { .compatible = "mediatek,mt8167-disp-gamma", 446 .data = (void *)MTK_DISP_GAMMA, }, 447 { .compatible = "mediatek,mt8173-disp-gamma", 448 .data = (void *)MTK_DISP_GAMMA, }, 449 { .compatible = "mediatek,mt8183-disp-gamma", 450 .data = (void *)MTK_DISP_GAMMA, }, 451 { .compatible = "mediatek,mt2701-disp-mutex", 452 .data = (void *)MTK_DISP_MUTEX }, 453 { .compatible = "mediatek,mt2712-disp-mutex", 454 .data = (void *)MTK_DISP_MUTEX }, 455 { .compatible = "mediatek,mt8167-disp-mutex", 456 .data = (void *)MTK_DISP_MUTEX }, 457 { .compatible = "mediatek,mt8173-disp-mutex", 458 .data = (void *)MTK_DISP_MUTEX }, 459 { .compatible = "mediatek,mt8183-disp-mutex", 460 .data = (void *)MTK_DISP_MUTEX }, 461 { .compatible = "mediatek,mt8192-disp-mutex", 462 .data = (void *)MTK_DISP_MUTEX }, 463 { .compatible = "mediatek,mt8173-disp-od", 464 .data = (void *)MTK_DISP_OD }, 465 { .compatible = "mediatek,mt2701-disp-ovl", 466 .data = (void *)MTK_DISP_OVL }, 467 { .compatible = "mediatek,mt8167-disp-ovl", 468 .data = (void *)MTK_DISP_OVL }, 469 { .compatible = "mediatek,mt8173-disp-ovl", 470 .data = (void *)MTK_DISP_OVL }, 471 { .compatible = "mediatek,mt8183-disp-ovl", 472 .data = (void *)MTK_DISP_OVL }, 473 { .compatible = "mediatek,mt8192-disp-ovl", 474 .data = (void *)MTK_DISP_OVL }, 475 { .compatible = "mediatek,mt8183-disp-ovl-2l", 476 .data = (void *)MTK_DISP_OVL_2L }, 477 { .compatible = "mediatek,mt8192-disp-ovl-2l", 478 .data = (void *)MTK_DISP_OVL_2L }, 479 { .compatible = "mediatek,mt8192-disp-postmask", 480 .data = (void *)MTK_DISP_POSTMASK }, 481 { .compatible = "mediatek,mt2701-disp-pwm", 482 .data = (void *)MTK_DISP_BLS }, 483 { .compatible = "mediatek,mt8167-disp-pwm", 484 .data = (void *)MTK_DISP_PWM }, 485 { .compatible = "mediatek,mt8173-disp-pwm", 486 .data = (void *)MTK_DISP_PWM }, 487 { .compatible = "mediatek,mt2701-disp-rdma", 488 .data = (void *)MTK_DISP_RDMA }, 489 { .compatible = "mediatek,mt8167-disp-rdma", 490 .data = (void *)MTK_DISP_RDMA }, 491 { .compatible = "mediatek,mt8173-disp-rdma", 492 .data = (void *)MTK_DISP_RDMA }, 493 { .compatible = "mediatek,mt8183-disp-rdma", 494 .data = (void *)MTK_DISP_RDMA }, 495 { .compatible = "mediatek,mt8192-disp-rdma", 496 .data = (void *)MTK_DISP_RDMA }, 497 { .compatible = "mediatek,mt8173-disp-ufoe", 498 .data = (void *)MTK_DISP_UFOE }, 499 { .compatible = "mediatek,mt8173-disp-wdma", 500 .data = (void *)MTK_DISP_WDMA }, 501 { .compatible = "mediatek,mt2701-dpi", 502 .data = (void *)MTK_DPI }, 503 { .compatible = "mediatek,mt8167-dsi", 504 .data = (void *)MTK_DSI }, 505 { .compatible = "mediatek,mt8173-dpi", 506 .data = (void *)MTK_DPI }, 507 { .compatible = "mediatek,mt8183-dpi", 508 .data = (void *)MTK_DPI }, 509 { .compatible = "mediatek,mt2701-dsi", 510 .data = (void *)MTK_DSI }, 511 { .compatible = "mediatek,mt8173-dsi", 512 .data = (void *)MTK_DSI }, 513 { .compatible = "mediatek,mt8183-dsi", 514 .data = (void *)MTK_DSI }, 515 { } 516 }; 517 518 static const struct of_device_id mtk_drm_of_ids[] = { 519 { .compatible = "mediatek,mt2701-mmsys", 520 .data = &mt2701_mmsys_driver_data}, 521 { .compatible = "mediatek,mt7623-mmsys", 522 .data = &mt7623_mmsys_driver_data}, 523 { .compatible = "mediatek,mt2712-mmsys", 524 .data = &mt2712_mmsys_driver_data}, 525 { .compatible = "mediatek,mt8167-mmsys", 526 .data = &mt8167_mmsys_driver_data}, 527 { .compatible = "mediatek,mt8173-mmsys", 528 .data = &mt8173_mmsys_driver_data}, 529 { .compatible = "mediatek,mt8183-mmsys", 530 .data = &mt8183_mmsys_driver_data}, 531 { .compatible = "mediatek,mt8192-mmsys", 532 .data = &mt8192_mmsys_driver_data}, 533 { } 534 }; 535 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 536 537 static int mtk_drm_probe(struct platform_device *pdev) 538 { 539 struct device *dev = &pdev->dev; 540 struct device_node *phandle = dev->parent->of_node; 541 const struct of_device_id *of_id; 542 struct mtk_drm_private *private; 543 struct device_node *node; 544 struct component_match *match = NULL; 545 int ret; 546 int i; 547 548 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 549 if (!private) 550 return -ENOMEM; 551 552 private->mmsys_dev = dev->parent; 553 if (!private->mmsys_dev) { 554 dev_err(dev, "Failed to get MMSYS device\n"); 555 return -ENODEV; 556 } 557 558 of_id = of_match_node(mtk_drm_of_ids, phandle); 559 if (!of_id) 560 return -ENODEV; 561 562 private->data = of_id->data; 563 564 /* Iterate over sibling DISP function blocks */ 565 for_each_child_of_node(phandle->parent, node) { 566 const struct of_device_id *of_id; 567 enum mtk_ddp_comp_type comp_type; 568 int comp_id; 569 570 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 571 if (!of_id) 572 continue; 573 574 if (!of_device_is_available(node)) { 575 dev_dbg(dev, "Skipping disabled component %pOF\n", 576 node); 577 continue; 578 } 579 580 comp_type = (enum mtk_ddp_comp_type)of_id->data; 581 582 if (comp_type == MTK_DISP_MUTEX) { 583 private->mutex_node = of_node_get(node); 584 continue; 585 } 586 587 comp_id = mtk_ddp_comp_get_id(node, comp_type); 588 if (comp_id < 0) { 589 dev_warn(dev, "Skipping unknown component %pOF\n", 590 node); 591 continue; 592 } 593 594 private->comp_node[comp_id] = of_node_get(node); 595 596 /* 597 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI 598 * blocks have separate component platform drivers and initialize their own 599 * DDP component structure. The others are initialized here. 600 */ 601 if (comp_type == MTK_DISP_AAL || 602 comp_type == MTK_DISP_CCORR || 603 comp_type == MTK_DISP_COLOR || 604 comp_type == MTK_DISP_GAMMA || 605 comp_type == MTK_DISP_OVL || 606 comp_type == MTK_DISP_OVL_2L || 607 comp_type == MTK_DISP_RDMA || 608 comp_type == MTK_DPI || 609 comp_type == MTK_DSI) { 610 dev_info(dev, "Adding component match for %pOF\n", 611 node); 612 drm_of_component_match_add(dev, &match, component_compare_of, 613 node); 614 } 615 616 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 617 if (ret) { 618 of_node_put(node); 619 goto err_node; 620 } 621 } 622 623 if (!private->mutex_node) { 624 dev_err(dev, "Failed to find disp-mutex node\n"); 625 ret = -ENODEV; 626 goto err_node; 627 } 628 629 pm_runtime_enable(dev); 630 631 platform_set_drvdata(pdev, private); 632 633 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 634 if (ret) 635 goto err_pm; 636 637 return 0; 638 639 err_pm: 640 pm_runtime_disable(dev); 641 err_node: 642 of_node_put(private->mutex_node); 643 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) { 644 of_node_put(private->comp_node[i]); 645 if (private->ddp_comp[i].larb_dev) 646 put_device(private->ddp_comp[i].larb_dev); 647 } 648 return ret; 649 } 650 651 static int mtk_drm_remove(struct platform_device *pdev) 652 { 653 struct mtk_drm_private *private = platform_get_drvdata(pdev); 654 int i; 655 656 component_master_del(&pdev->dev, &mtk_drm_ops); 657 pm_runtime_disable(&pdev->dev); 658 of_node_put(private->mutex_node); 659 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 660 of_node_put(private->comp_node[i]); 661 662 return 0; 663 } 664 665 #ifdef CONFIG_PM_SLEEP 666 static int mtk_drm_sys_suspend(struct device *dev) 667 { 668 struct mtk_drm_private *private = dev_get_drvdata(dev); 669 struct drm_device *drm = private->drm; 670 int ret; 671 672 ret = drm_mode_config_helper_suspend(drm); 673 674 return ret; 675 } 676 677 static int mtk_drm_sys_resume(struct device *dev) 678 { 679 struct mtk_drm_private *private = dev_get_drvdata(dev); 680 struct drm_device *drm = private->drm; 681 int ret; 682 683 ret = drm_mode_config_helper_resume(drm); 684 685 return ret; 686 } 687 #endif 688 689 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 690 mtk_drm_sys_resume); 691 692 static struct platform_driver mtk_drm_platform_driver = { 693 .probe = mtk_drm_probe, 694 .remove = mtk_drm_remove, 695 .driver = { 696 .name = "mediatek-drm", 697 .pm = &mtk_drm_pm_ops, 698 }, 699 }; 700 701 static struct platform_driver * const mtk_drm_drivers[] = { 702 &mtk_disp_aal_driver, 703 &mtk_disp_ccorr_driver, 704 &mtk_disp_color_driver, 705 &mtk_disp_gamma_driver, 706 &mtk_disp_ovl_driver, 707 &mtk_disp_rdma_driver, 708 &mtk_dpi_driver, 709 &mtk_drm_platform_driver, 710 &mtk_dsi_driver, 711 }; 712 713 static int __init mtk_drm_init(void) 714 { 715 return platform_register_drivers(mtk_drm_drivers, 716 ARRAY_SIZE(mtk_drm_drivers)); 717 } 718 719 static void __exit mtk_drm_exit(void) 720 { 721 platform_unregister_drivers(mtk_drm_drivers, 722 ARRAY_SIZE(mtk_drm_drivers)); 723 } 724 725 module_init(mtk_drm_init); 726 module_exit(mtk_drm_exit); 727 728 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 729 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 730 MODULE_LICENSE("GPL v2"); 731