1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_graph.h> 14 #include <linux/platform_device.h> 15 #include <linux/types.h> 16 17 #include <video/videomode.h> 18 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_bridge.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_simple_kms_helper.h> 24 25 #include "mtk_dpi_regs.h" 26 #include "mtk_drm_ddp_comp.h" 27 28 enum mtk_dpi_out_bit_num { 29 MTK_DPI_OUT_BIT_NUM_8BITS, 30 MTK_DPI_OUT_BIT_NUM_10BITS, 31 MTK_DPI_OUT_BIT_NUM_12BITS, 32 MTK_DPI_OUT_BIT_NUM_16BITS 33 }; 34 35 enum mtk_dpi_out_yc_map { 36 MTK_DPI_OUT_YC_MAP_RGB, 37 MTK_DPI_OUT_YC_MAP_CYCY, 38 MTK_DPI_OUT_YC_MAP_YCYC, 39 MTK_DPI_OUT_YC_MAP_CY, 40 MTK_DPI_OUT_YC_MAP_YC 41 }; 42 43 enum mtk_dpi_out_channel_swap { 44 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 45 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 46 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 47 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 48 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 49 MTK_DPI_OUT_CHANNEL_SWAP_BGR 50 }; 51 52 enum mtk_dpi_out_color_format { 53 MTK_DPI_COLOR_FORMAT_RGB, 54 MTK_DPI_COLOR_FORMAT_RGB_FULL, 55 MTK_DPI_COLOR_FORMAT_YCBCR_444, 56 MTK_DPI_COLOR_FORMAT_YCBCR_422, 57 MTK_DPI_COLOR_FORMAT_XV_YCC, 58 MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL, 59 MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL 60 }; 61 62 struct mtk_dpi { 63 struct mtk_ddp_comp ddp_comp; 64 struct drm_encoder encoder; 65 struct drm_bridge *bridge; 66 void __iomem *regs; 67 struct device *dev; 68 struct clk *engine_clk; 69 struct clk *pixel_clk; 70 struct clk *tvd_clk; 71 int irq; 72 struct drm_display_mode mode; 73 const struct mtk_dpi_conf *conf; 74 enum mtk_dpi_out_color_format color_format; 75 enum mtk_dpi_out_yc_map yc_map; 76 enum mtk_dpi_out_bit_num bit_num; 77 enum mtk_dpi_out_channel_swap channel_swap; 78 int refcount; 79 }; 80 81 static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e) 82 { 83 return container_of(e, struct mtk_dpi, encoder); 84 } 85 86 enum mtk_dpi_polarity { 87 MTK_DPI_POLARITY_RISING, 88 MTK_DPI_POLARITY_FALLING, 89 }; 90 91 struct mtk_dpi_polarities { 92 enum mtk_dpi_polarity de_pol; 93 enum mtk_dpi_polarity ck_pol; 94 enum mtk_dpi_polarity hsync_pol; 95 enum mtk_dpi_polarity vsync_pol; 96 }; 97 98 struct mtk_dpi_sync_param { 99 u32 sync_width; 100 u32 front_porch; 101 u32 back_porch; 102 bool shift_half_line; 103 }; 104 105 struct mtk_dpi_yc_limit { 106 u16 y_top; 107 u16 y_bottom; 108 u16 c_top; 109 u16 c_bottom; 110 }; 111 112 struct mtk_dpi_conf { 113 unsigned int (*cal_factor)(int clock); 114 u32 reg_h_fre_con; 115 bool edge_sel_en; 116 }; 117 118 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 119 { 120 u32 tmp = readl(dpi->regs + offset) & ~mask; 121 122 tmp |= (val & mask); 123 writel(tmp, dpi->regs + offset); 124 } 125 126 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 127 { 128 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 129 } 130 131 static void mtk_dpi_enable(struct mtk_dpi *dpi) 132 { 133 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 134 } 135 136 static void mtk_dpi_disable(struct mtk_dpi *dpi) 137 { 138 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 139 } 140 141 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 142 struct mtk_dpi_sync_param *sync) 143 { 144 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, 145 sync->sync_width << HPW, HPW_MASK); 146 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, 147 sync->back_porch << HBP, HBP_MASK); 148 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 149 HFP_MASK); 150 } 151 152 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 153 struct mtk_dpi_sync_param *sync, 154 u32 width_addr, u32 porch_addr) 155 { 156 mtk_dpi_mask(dpi, width_addr, 157 sync->sync_width << VSYNC_WIDTH_SHIFT, 158 VSYNC_WIDTH_MASK); 159 mtk_dpi_mask(dpi, width_addr, 160 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 161 VSYNC_HALF_LINE_MASK); 162 mtk_dpi_mask(dpi, porch_addr, 163 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 164 VSYNC_BACK_PORCH_MASK); 165 mtk_dpi_mask(dpi, porch_addr, 166 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 167 VSYNC_FRONT_PORCH_MASK); 168 } 169 170 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 171 struct mtk_dpi_sync_param *sync) 172 { 173 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 174 } 175 176 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 177 struct mtk_dpi_sync_param *sync) 178 { 179 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 180 DPI_TGEN_VPORCH_LEVEN); 181 } 182 183 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 184 struct mtk_dpi_sync_param *sync) 185 { 186 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 187 DPI_TGEN_VPORCH_RODD); 188 } 189 190 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 191 struct mtk_dpi_sync_param *sync) 192 { 193 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 194 DPI_TGEN_VPORCH_REVEN); 195 } 196 197 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 198 struct mtk_dpi_polarities *dpi_pol) 199 { 200 unsigned int pol; 201 202 pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | 203 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | 204 (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 205 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 206 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, 207 CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); 208 } 209 210 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 211 { 212 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 213 } 214 215 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 216 { 217 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 218 } 219 220 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 221 { 222 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); 223 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); 224 } 225 226 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, 227 struct mtk_dpi_yc_limit *limit) 228 { 229 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, 230 Y_LIMINT_BOT_MASK); 231 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, 232 Y_LIMINT_TOP_MASK); 233 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, 234 C_LIMIT_BOT_MASK); 235 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, 236 C_LIMIT_TOP_MASK); 237 } 238 239 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 240 enum mtk_dpi_out_bit_num num) 241 { 242 u32 val; 243 244 switch (num) { 245 case MTK_DPI_OUT_BIT_NUM_8BITS: 246 val = OUT_BIT_8; 247 break; 248 case MTK_DPI_OUT_BIT_NUM_10BITS: 249 val = OUT_BIT_10; 250 break; 251 case MTK_DPI_OUT_BIT_NUM_12BITS: 252 val = OUT_BIT_12; 253 break; 254 case MTK_DPI_OUT_BIT_NUM_16BITS: 255 val = OUT_BIT_16; 256 break; 257 default: 258 val = OUT_BIT_8; 259 break; 260 } 261 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 262 OUT_BIT_MASK); 263 } 264 265 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 266 enum mtk_dpi_out_yc_map map) 267 { 268 u32 val; 269 270 switch (map) { 271 case MTK_DPI_OUT_YC_MAP_RGB: 272 val = YC_MAP_RGB; 273 break; 274 case MTK_DPI_OUT_YC_MAP_CYCY: 275 val = YC_MAP_CYCY; 276 break; 277 case MTK_DPI_OUT_YC_MAP_YCYC: 278 val = YC_MAP_YCYC; 279 break; 280 case MTK_DPI_OUT_YC_MAP_CY: 281 val = YC_MAP_CY; 282 break; 283 case MTK_DPI_OUT_YC_MAP_YC: 284 val = YC_MAP_YC; 285 break; 286 default: 287 val = YC_MAP_RGB; 288 break; 289 } 290 291 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 292 } 293 294 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 295 enum mtk_dpi_out_channel_swap swap) 296 { 297 u32 val; 298 299 switch (swap) { 300 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 301 val = SWAP_RGB; 302 break; 303 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 304 val = SWAP_GBR; 305 break; 306 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 307 val = SWAP_BRG; 308 break; 309 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 310 val = SWAP_RBG; 311 break; 312 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 313 val = SWAP_GRB; 314 break; 315 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 316 val = SWAP_BGR; 317 break; 318 default: 319 val = SWAP_RGB; 320 break; 321 } 322 323 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); 324 } 325 326 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 327 { 328 mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); 329 } 330 331 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 332 { 333 mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); 334 } 335 336 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 337 { 338 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 339 } 340 341 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 342 { 343 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 344 } 345 346 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 347 { 348 if (dpi->conf->edge_sel_en) 349 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 350 } 351 352 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 353 enum mtk_dpi_out_color_format format) 354 { 355 if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) || 356 (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { 357 mtk_dpi_config_yuv422_enable(dpi, false); 358 mtk_dpi_config_csc_enable(dpi, true); 359 mtk_dpi_config_swap_input(dpi, false); 360 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); 361 } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || 362 (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { 363 mtk_dpi_config_yuv422_enable(dpi, true); 364 mtk_dpi_config_csc_enable(dpi, true); 365 mtk_dpi_config_swap_input(dpi, true); 366 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 367 } else { 368 mtk_dpi_config_yuv422_enable(dpi, false); 369 mtk_dpi_config_csc_enable(dpi, false); 370 mtk_dpi_config_swap_input(dpi, false); 371 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 372 } 373 } 374 375 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 376 { 377 if (WARN_ON(dpi->refcount == 0)) 378 return; 379 380 if (--dpi->refcount != 0) 381 return; 382 383 mtk_dpi_disable(dpi); 384 clk_disable_unprepare(dpi->pixel_clk); 385 clk_disable_unprepare(dpi->engine_clk); 386 } 387 388 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 389 { 390 int ret; 391 392 if (++dpi->refcount != 1) 393 return 0; 394 395 ret = clk_prepare_enable(dpi->engine_clk); 396 if (ret) { 397 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 398 goto err_refcount; 399 } 400 401 ret = clk_prepare_enable(dpi->pixel_clk); 402 if (ret) { 403 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 404 goto err_pixel; 405 } 406 407 mtk_dpi_enable(dpi); 408 return 0; 409 410 err_pixel: 411 clk_disable_unprepare(dpi->engine_clk); 412 err_refcount: 413 dpi->refcount--; 414 return ret; 415 } 416 417 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 418 struct drm_display_mode *mode) 419 { 420 struct mtk_dpi_yc_limit limit; 421 struct mtk_dpi_polarities dpi_pol; 422 struct mtk_dpi_sync_param hsync; 423 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 424 struct mtk_dpi_sync_param vsync_leven = { 0 }; 425 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 426 struct mtk_dpi_sync_param vsync_reven = { 0 }; 427 struct videomode vm = { 0 }; 428 unsigned long pll_rate; 429 unsigned int factor; 430 431 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 432 factor = dpi->conf->cal_factor(mode->clock); 433 drm_display_mode_to_videomode(mode, &vm); 434 pll_rate = vm.pixelclock * factor; 435 436 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 437 pll_rate, vm.pixelclock); 438 439 clk_set_rate(dpi->tvd_clk, pll_rate); 440 pll_rate = clk_get_rate(dpi->tvd_clk); 441 442 vm.pixelclock = pll_rate / factor; 443 clk_set_rate(dpi->pixel_clk, vm.pixelclock); 444 vm.pixelclock = clk_get_rate(dpi->pixel_clk); 445 446 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 447 pll_rate, vm.pixelclock); 448 449 limit.c_bottom = 0x0010; 450 limit.c_top = 0x0FE0; 451 limit.y_bottom = 0x0010; 452 limit.y_top = 0x0FE0; 453 454 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 455 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 456 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 457 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 458 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 459 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 460 hsync.sync_width = vm.hsync_len; 461 hsync.back_porch = vm.hback_porch; 462 hsync.front_porch = vm.hfront_porch; 463 hsync.shift_half_line = false; 464 vsync_lodd.sync_width = vm.vsync_len; 465 vsync_lodd.back_porch = vm.vback_porch; 466 vsync_lodd.front_porch = vm.vfront_porch; 467 vsync_lodd.shift_half_line = false; 468 469 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 470 mode->flags & DRM_MODE_FLAG_3D_MASK) { 471 vsync_leven = vsync_lodd; 472 vsync_rodd = vsync_lodd; 473 vsync_reven = vsync_lodd; 474 vsync_leven.shift_half_line = true; 475 vsync_reven.shift_half_line = true; 476 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 477 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 478 vsync_leven = vsync_lodd; 479 vsync_leven.shift_half_line = true; 480 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 481 mode->flags & DRM_MODE_FLAG_3D_MASK) { 482 vsync_rodd = vsync_lodd; 483 } 484 mtk_dpi_sw_reset(dpi, true); 485 mtk_dpi_config_pol(dpi, &dpi_pol); 486 487 mtk_dpi_config_hsync(dpi, &hsync); 488 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 489 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 490 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 491 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 492 493 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 494 mtk_dpi_config_interface(dpi, !!(vm.flags & 495 DISPLAY_FLAGS_INTERLACED)); 496 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 497 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 498 else 499 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 500 501 mtk_dpi_config_channel_limit(dpi, &limit); 502 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 503 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 504 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 505 mtk_dpi_config_color_format(dpi, dpi->color_format); 506 mtk_dpi_config_2n_h_fre(dpi); 507 mtk_dpi_config_disable_edge(dpi); 508 mtk_dpi_sw_reset(dpi, false); 509 510 return 0; 511 } 512 513 static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder, 514 const struct drm_display_mode *mode, 515 struct drm_display_mode *adjusted_mode) 516 { 517 return true; 518 } 519 520 static void mtk_dpi_encoder_mode_set(struct drm_encoder *encoder, 521 struct drm_display_mode *mode, 522 struct drm_display_mode *adjusted_mode) 523 { 524 struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder); 525 526 drm_mode_copy(&dpi->mode, adjusted_mode); 527 } 528 529 static void mtk_dpi_encoder_disable(struct drm_encoder *encoder) 530 { 531 struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder); 532 533 mtk_dpi_power_off(dpi); 534 } 535 536 static void mtk_dpi_encoder_enable(struct drm_encoder *encoder) 537 { 538 struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder); 539 540 mtk_dpi_power_on(dpi); 541 mtk_dpi_set_display_mode(dpi, &dpi->mode); 542 } 543 544 static int mtk_dpi_atomic_check(struct drm_encoder *encoder, 545 struct drm_crtc_state *crtc_state, 546 struct drm_connector_state *conn_state) 547 { 548 return 0; 549 } 550 551 static const struct drm_encoder_helper_funcs mtk_dpi_encoder_helper_funcs = { 552 .mode_fixup = mtk_dpi_encoder_mode_fixup, 553 .mode_set = mtk_dpi_encoder_mode_set, 554 .disable = mtk_dpi_encoder_disable, 555 .enable = mtk_dpi_encoder_enable, 556 .atomic_check = mtk_dpi_atomic_check, 557 }; 558 559 static void mtk_dpi_start(struct mtk_ddp_comp *comp) 560 { 561 struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp); 562 563 mtk_dpi_power_on(dpi); 564 } 565 566 static void mtk_dpi_stop(struct mtk_ddp_comp *comp) 567 { 568 struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp); 569 570 mtk_dpi_power_off(dpi); 571 } 572 573 static const struct mtk_ddp_comp_funcs mtk_dpi_funcs = { 574 .start = mtk_dpi_start, 575 .stop = mtk_dpi_stop, 576 }; 577 578 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 579 { 580 struct mtk_dpi *dpi = dev_get_drvdata(dev); 581 struct drm_device *drm_dev = data; 582 int ret; 583 584 ret = mtk_ddp_comp_register(drm_dev, &dpi->ddp_comp); 585 if (ret < 0) { 586 dev_err(dev, "Failed to register component %pOF: %d\n", 587 dev->of_node, ret); 588 return ret; 589 } 590 591 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, 592 DRM_MODE_ENCODER_TMDS); 593 if (ret) { 594 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 595 goto err_unregister; 596 } 597 drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs); 598 599 /* Currently DPI0 is fixed to be driven by OVL1 */ 600 dpi->encoder.possible_crtcs = BIT(1); 601 602 ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0); 603 if (ret) { 604 dev_err(dev, "Failed to attach bridge: %d\n", ret); 605 goto err_cleanup; 606 } 607 608 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; 609 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; 610 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 611 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; 612 613 return 0; 614 615 err_cleanup: 616 drm_encoder_cleanup(&dpi->encoder); 617 err_unregister: 618 mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp); 619 return ret; 620 } 621 622 static void mtk_dpi_unbind(struct device *dev, struct device *master, 623 void *data) 624 { 625 struct mtk_dpi *dpi = dev_get_drvdata(dev); 626 struct drm_device *drm_dev = data; 627 628 drm_encoder_cleanup(&dpi->encoder); 629 mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp); 630 } 631 632 static const struct component_ops mtk_dpi_component_ops = { 633 .bind = mtk_dpi_bind, 634 .unbind = mtk_dpi_unbind, 635 }; 636 637 static unsigned int mt8173_calculate_factor(int clock) 638 { 639 if (clock <= 27000) 640 return 3 << 4; 641 else if (clock <= 84000) 642 return 3 << 3; 643 else if (clock <= 167000) 644 return 3 << 2; 645 else 646 return 3 << 1; 647 } 648 649 static unsigned int mt2701_calculate_factor(int clock) 650 { 651 if (clock <= 64000) 652 return 4; 653 else if (clock <= 128000) 654 return 2; 655 else 656 return 1; 657 } 658 659 static unsigned int mt8183_calculate_factor(int clock) 660 { 661 if (clock <= 27000) 662 return 8; 663 else if (clock <= 167000) 664 return 4; 665 else 666 return 2; 667 } 668 669 static const struct mtk_dpi_conf mt8173_conf = { 670 .cal_factor = mt8173_calculate_factor, 671 .reg_h_fre_con = 0xe0, 672 }; 673 674 static const struct mtk_dpi_conf mt2701_conf = { 675 .cal_factor = mt2701_calculate_factor, 676 .reg_h_fre_con = 0xb0, 677 .edge_sel_en = true, 678 }; 679 680 static const struct mtk_dpi_conf mt8183_conf = { 681 .cal_factor = mt8183_calculate_factor, 682 .reg_h_fre_con = 0xe0, 683 }; 684 685 static int mtk_dpi_probe(struct platform_device *pdev) 686 { 687 struct device *dev = &pdev->dev; 688 struct mtk_dpi *dpi; 689 struct resource *mem; 690 int comp_id; 691 int ret; 692 693 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); 694 if (!dpi) 695 return -ENOMEM; 696 697 dpi->dev = dev; 698 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 699 700 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 701 dpi->regs = devm_ioremap_resource(dev, mem); 702 if (IS_ERR(dpi->regs)) { 703 ret = PTR_ERR(dpi->regs); 704 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret); 705 return ret; 706 } 707 708 dpi->engine_clk = devm_clk_get(dev, "engine"); 709 if (IS_ERR(dpi->engine_clk)) { 710 ret = PTR_ERR(dpi->engine_clk); 711 dev_err(dev, "Failed to get engine clock: %d\n", ret); 712 return ret; 713 } 714 715 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 716 if (IS_ERR(dpi->pixel_clk)) { 717 ret = PTR_ERR(dpi->pixel_clk); 718 dev_err(dev, "Failed to get pixel clock: %d\n", ret); 719 return ret; 720 } 721 722 dpi->tvd_clk = devm_clk_get(dev, "pll"); 723 if (IS_ERR(dpi->tvd_clk)) { 724 ret = PTR_ERR(dpi->tvd_clk); 725 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret); 726 return ret; 727 } 728 729 dpi->irq = platform_get_irq(pdev, 0); 730 if (dpi->irq <= 0) { 731 dev_err(dev, "Failed to get irq: %d\n", dpi->irq); 732 return -EINVAL; 733 } 734 735 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 736 NULL, &dpi->bridge); 737 if (ret) 738 return ret; 739 740 dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge->of_node); 741 742 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI); 743 if (comp_id < 0) { 744 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 745 return comp_id; 746 } 747 748 ret = mtk_ddp_comp_init(dev, dev->of_node, &dpi->ddp_comp, comp_id, 749 &mtk_dpi_funcs); 750 if (ret) { 751 dev_err(dev, "Failed to initialize component: %d\n", ret); 752 return ret; 753 } 754 755 platform_set_drvdata(pdev, dpi); 756 757 ret = component_add(dev, &mtk_dpi_component_ops); 758 if (ret) { 759 dev_err(dev, "Failed to add component: %d\n", ret); 760 return ret; 761 } 762 763 return 0; 764 } 765 766 static int mtk_dpi_remove(struct platform_device *pdev) 767 { 768 component_del(&pdev->dev, &mtk_dpi_component_ops); 769 770 return 0; 771 } 772 773 static const struct of_device_id mtk_dpi_of_ids[] = { 774 { .compatible = "mediatek,mt2701-dpi", 775 .data = &mt2701_conf, 776 }, 777 { .compatible = "mediatek,mt8173-dpi", 778 .data = &mt8173_conf, 779 }, 780 { .compatible = "mediatek,mt8183-dpi", 781 .data = &mt8183_conf, 782 }, 783 { }, 784 }; 785 786 struct platform_driver mtk_dpi_driver = { 787 .probe = mtk_dpi_probe, 788 .remove = mtk_dpi_remove, 789 .driver = { 790 .name = "mediatek-dpi", 791 .of_match_table = mtk_dpi_of_ids, 792 }, 793 }; 794