1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/debugfs.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/of.h> 15 #include <linux/of_graph.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/soc/mediatek/mtk-mmsys.h> 19 #include <linux/types.h> 20 21 #include <video/videomode.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_bridge_connector.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_simple_kms_helper.h> 30 31 #include "mtk_ddp_comp.h" 32 #include "mtk_disp_drv.h" 33 #include "mtk_dpi_regs.h" 34 #include "mtk_drm_drv.h" 35 36 enum mtk_dpi_out_bit_num { 37 MTK_DPI_OUT_BIT_NUM_8BITS, 38 MTK_DPI_OUT_BIT_NUM_10BITS, 39 MTK_DPI_OUT_BIT_NUM_12BITS, 40 MTK_DPI_OUT_BIT_NUM_16BITS 41 }; 42 43 enum mtk_dpi_out_yc_map { 44 MTK_DPI_OUT_YC_MAP_RGB, 45 MTK_DPI_OUT_YC_MAP_CYCY, 46 MTK_DPI_OUT_YC_MAP_YCYC, 47 MTK_DPI_OUT_YC_MAP_CY, 48 MTK_DPI_OUT_YC_MAP_YC 49 }; 50 51 enum mtk_dpi_out_channel_swap { 52 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 53 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 54 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 55 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 56 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 57 MTK_DPI_OUT_CHANNEL_SWAP_BGR 58 }; 59 60 enum mtk_dpi_out_color_format { 61 MTK_DPI_COLOR_FORMAT_RGB, 62 MTK_DPI_COLOR_FORMAT_YCBCR_422 63 }; 64 65 struct mtk_dpi { 66 struct drm_encoder encoder; 67 struct drm_bridge bridge; 68 struct drm_bridge *next_bridge; 69 struct drm_connector *connector; 70 void __iomem *regs; 71 struct device *dev; 72 struct device *mmsys_dev; 73 struct clk *engine_clk; 74 struct clk *pixel_clk; 75 struct clk *tvd_clk; 76 int irq; 77 struct drm_display_mode mode; 78 const struct mtk_dpi_conf *conf; 79 enum mtk_dpi_out_color_format color_format; 80 enum mtk_dpi_out_yc_map yc_map; 81 enum mtk_dpi_out_bit_num bit_num; 82 enum mtk_dpi_out_channel_swap channel_swap; 83 struct pinctrl *pinctrl; 84 struct pinctrl_state *pins_gpio; 85 struct pinctrl_state *pins_dpi; 86 u32 output_fmt; 87 int refcount; 88 }; 89 90 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) 91 { 92 return container_of(b, struct mtk_dpi, bridge); 93 } 94 95 enum mtk_dpi_polarity { 96 MTK_DPI_POLARITY_RISING, 97 MTK_DPI_POLARITY_FALLING, 98 }; 99 100 struct mtk_dpi_polarities { 101 enum mtk_dpi_polarity de_pol; 102 enum mtk_dpi_polarity ck_pol; 103 enum mtk_dpi_polarity hsync_pol; 104 enum mtk_dpi_polarity vsync_pol; 105 }; 106 107 struct mtk_dpi_sync_param { 108 u32 sync_width; 109 u32 front_porch; 110 u32 back_porch; 111 bool shift_half_line; 112 }; 113 114 struct mtk_dpi_yc_limit { 115 u16 y_top; 116 u16 y_bottom; 117 u16 c_top; 118 u16 c_bottom; 119 }; 120 121 struct mtk_dpi_factor { 122 u32 clock; 123 u8 factor; 124 }; 125 126 /** 127 * struct mtk_dpi_conf - Configuration of mediatek dpi. 128 * @dpi_factor: SoC-specific pixel clock PLL factor values. 129 * @num_dpi_factor: Number of pixel clock PLL factor values. 130 * @reg_h_fre_con: Register address of frequency control. 131 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. 132 * @edge_sel_en: Enable of edge selection. 133 * @output_fmts: Array of supported output formats. 134 * @num_output_fmts: Quantity of supported output formats. 135 * @is_ck_de_pol: Support CK/DE polarity. 136 * @swap_input_support: Support input swap function. 137 * @support_direct_pin: IP supports direct connection to dpi panels. 138 * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH 139 * (no shift). 140 * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). 141 * @channel_swap_shift: Shift value of channel swap. 142 * @yuv422_en_bit: Enable bit of yuv422. 143 * @csc_enable_bit: Enable bit of CSC. 144 * @input_2p_en_bit: Enable bit for input two pixel per round feature. 145 * If present, implies that the feature must be enabled. 146 * @pixels_per_iter: Quantity of transferred pixels per iteration. 147 * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. 148 * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed 149 * for DPI registers access. 150 * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per 151 * round, the DPI hardware will internally transform it to 1T1P. 152 */ 153 struct mtk_dpi_conf { 154 const struct mtk_dpi_factor *dpi_factor; 155 const u8 num_dpi_factor; 156 u32 reg_h_fre_con; 157 u32 max_clock_khz; 158 bool edge_sel_en; 159 const u32 *output_fmts; 160 u32 num_output_fmts; 161 bool is_ck_de_pol; 162 bool swap_input_support; 163 bool support_direct_pin; 164 u32 dimension_mask; 165 u32 hvsize_mask; 166 u32 channel_swap_shift; 167 u32 yuv422_en_bit; 168 u32 csc_enable_bit; 169 u32 input_2p_en_bit; 170 u32 pixels_per_iter; 171 bool edge_cfg_in_mmsys; 172 bool clocked_by_hdmi; 173 bool output_1pixel; 174 }; 175 176 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 177 { 178 u32 tmp = readl(dpi->regs + offset) & ~mask; 179 180 tmp |= (val & mask); 181 writel(tmp, dpi->regs + offset); 182 } 183 184 static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable) 185 { 186 u32 val; 187 188 if (enable) 189 val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN; 190 else 191 val = 0; 192 193 mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN); 194 } 195 196 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 197 { 198 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 199 } 200 201 static void mtk_dpi_enable(struct mtk_dpi *dpi) 202 { 203 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 204 } 205 206 static void mtk_dpi_disable(struct mtk_dpi *dpi) 207 { 208 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 209 } 210 211 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 212 struct mtk_dpi_sync_param *sync) 213 { 214 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, 215 dpi->conf->dimension_mask << HPW); 216 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, 217 dpi->conf->dimension_mask << HBP); 218 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 219 dpi->conf->dimension_mask << HFP); 220 } 221 222 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 223 struct mtk_dpi_sync_param *sync, 224 u32 width_addr, u32 porch_addr) 225 { 226 mtk_dpi_mask(dpi, width_addr, 227 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 228 VSYNC_HALF_LINE_MASK); 229 mtk_dpi_mask(dpi, width_addr, 230 sync->sync_width << VSYNC_WIDTH_SHIFT, 231 dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); 232 mtk_dpi_mask(dpi, porch_addr, 233 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 234 dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); 235 mtk_dpi_mask(dpi, porch_addr, 236 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 237 dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); 238 } 239 240 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 241 struct mtk_dpi_sync_param *sync) 242 { 243 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 244 } 245 246 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 247 struct mtk_dpi_sync_param *sync) 248 { 249 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 250 DPI_TGEN_VPORCH_LEVEN); 251 } 252 253 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 254 struct mtk_dpi_sync_param *sync) 255 { 256 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 257 DPI_TGEN_VPORCH_RODD); 258 } 259 260 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 261 struct mtk_dpi_sync_param *sync) 262 { 263 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 264 DPI_TGEN_VPORCH_REVEN); 265 } 266 267 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 268 struct mtk_dpi_polarities *dpi_pol) 269 { 270 unsigned int pol; 271 unsigned int mask; 272 273 mask = HSYNC_POL | VSYNC_POL; 274 pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 275 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 276 if (dpi->conf->is_ck_de_pol) { 277 mask |= CK_POL | DE_POL; 278 pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 279 0 : CK_POL) | 280 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 281 0 : DE_POL); 282 } 283 284 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); 285 } 286 287 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 288 { 289 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 290 } 291 292 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 293 { 294 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 295 } 296 297 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 298 { 299 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, 300 dpi->conf->hvsize_mask << HSIZE); 301 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, 302 dpi->conf->hvsize_mask << VSIZE); 303 } 304 305 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) 306 { 307 struct mtk_dpi_yc_limit limit; 308 309 if (drm_default_rgb_quant_range(&dpi->mode) == 310 HDMI_QUANTIZATION_RANGE_LIMITED) { 311 limit.y_bottom = 0x10; 312 limit.y_top = 0xfe0; 313 limit.c_bottom = 0x10; 314 limit.c_top = 0xfe0; 315 } else { 316 limit.y_bottom = 0; 317 limit.y_top = 0xfff; 318 limit.c_bottom = 0; 319 limit.c_top = 0xfff; 320 } 321 322 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, 323 Y_LIMINT_BOT_MASK); 324 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, 325 Y_LIMINT_TOP_MASK); 326 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, 327 C_LIMIT_BOT_MASK); 328 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, 329 C_LIMIT_TOP_MASK); 330 } 331 332 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 333 enum mtk_dpi_out_bit_num num) 334 { 335 u32 val; 336 337 switch (num) { 338 case MTK_DPI_OUT_BIT_NUM_8BITS: 339 val = OUT_BIT_8; 340 break; 341 case MTK_DPI_OUT_BIT_NUM_10BITS: 342 val = OUT_BIT_10; 343 break; 344 case MTK_DPI_OUT_BIT_NUM_12BITS: 345 val = OUT_BIT_12; 346 break; 347 case MTK_DPI_OUT_BIT_NUM_16BITS: 348 val = OUT_BIT_16; 349 break; 350 default: 351 val = OUT_BIT_8; 352 break; 353 } 354 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 355 OUT_BIT_MASK); 356 } 357 358 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 359 enum mtk_dpi_out_yc_map map) 360 { 361 u32 val; 362 363 switch (map) { 364 case MTK_DPI_OUT_YC_MAP_RGB: 365 val = YC_MAP_RGB; 366 break; 367 case MTK_DPI_OUT_YC_MAP_CYCY: 368 val = YC_MAP_CYCY; 369 break; 370 case MTK_DPI_OUT_YC_MAP_YCYC: 371 val = YC_MAP_YCYC; 372 break; 373 case MTK_DPI_OUT_YC_MAP_CY: 374 val = YC_MAP_CY; 375 break; 376 case MTK_DPI_OUT_YC_MAP_YC: 377 val = YC_MAP_YC; 378 break; 379 default: 380 val = YC_MAP_RGB; 381 break; 382 } 383 384 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 385 } 386 387 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 388 enum mtk_dpi_out_channel_swap swap) 389 { 390 u32 val; 391 392 switch (swap) { 393 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 394 val = SWAP_RGB; 395 break; 396 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 397 val = SWAP_GBR; 398 break; 399 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 400 val = SWAP_BRG; 401 break; 402 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 403 val = SWAP_RBG; 404 break; 405 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 406 val = SWAP_GRB; 407 break; 408 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 409 val = SWAP_BGR; 410 break; 411 default: 412 val = SWAP_RGB; 413 break; 414 } 415 416 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 417 val << dpi->conf->channel_swap_shift, 418 CH_SWAP_MASK << dpi->conf->channel_swap_shift); 419 } 420 421 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 422 { 423 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, 424 dpi->conf->yuv422_en_bit); 425 } 426 427 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 428 { 429 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, 430 dpi->conf->csc_enable_bit); 431 } 432 433 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 434 { 435 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 436 } 437 438 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 439 { 440 if (dpi->conf->reg_h_fre_con) 441 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 442 } 443 444 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 445 { 446 if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con) 447 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 448 } 449 450 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 451 enum mtk_dpi_out_color_format format) 452 { 453 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 454 455 if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) { 456 mtk_dpi_config_yuv422_enable(dpi, true); 457 mtk_dpi_config_csc_enable(dpi, true); 458 459 /* 460 * If height is smaller than 720, we need to use RGB_TO_BT601 461 * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG. 462 */ 463 mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ? 464 MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG, 465 INT_MATRIX_SEL_MASK); 466 } else { 467 mtk_dpi_config_yuv422_enable(dpi, false); 468 mtk_dpi_config_csc_enable(dpi, false); 469 if (dpi->conf->swap_input_support) 470 mtk_dpi_config_swap_input(dpi, false); 471 } 472 } 473 474 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) 475 { 476 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 477 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) { 478 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 479 DDR_EN | DDR_4PHASE); 480 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 481 dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? 482 EDGE_SEL : 0, EDGE_SEL); 483 if (dpi->conf->edge_cfg_in_mmsys) 484 mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_DDR_CON); 485 } else { 486 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); 487 if (dpi->conf->edge_cfg_in_mmsys) 488 mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, MTK_DPI_RGB888_SDR_CON); 489 } 490 } 491 492 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 493 { 494 if (WARN_ON(dpi->refcount == 0)) 495 return; 496 497 if (--dpi->refcount != 0) 498 return; 499 500 mtk_dpi_disable(dpi); 501 clk_disable_unprepare(dpi->pixel_clk); 502 clk_disable_unprepare(dpi->tvd_clk); 503 clk_disable_unprepare(dpi->engine_clk); 504 } 505 506 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 507 { 508 int ret; 509 510 if (++dpi->refcount != 1) 511 return 0; 512 513 ret = clk_prepare_enable(dpi->engine_clk); 514 if (ret) { 515 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 516 goto err_refcount; 517 } 518 519 ret = clk_prepare_enable(dpi->tvd_clk); 520 if (ret) { 521 dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); 522 goto err_engine; 523 } 524 525 ret = clk_prepare_enable(dpi->pixel_clk); 526 if (ret) { 527 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 528 goto err_pixel; 529 } 530 531 return 0; 532 533 err_pixel: 534 clk_disable_unprepare(dpi->tvd_clk); 535 err_engine: 536 clk_disable_unprepare(dpi->engine_clk); 537 err_refcount: 538 dpi->refcount--; 539 return ret; 540 } 541 542 static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk) 543 { 544 const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor; 545 int i; 546 547 for (i = 0; i < dpi->conf->num_dpi_factor; i++) { 548 if (mode_clk <= dpi_factor[i].clock) 549 return dpi_factor[i].factor; 550 } 551 552 /* If no match try the lowest possible factor */ 553 return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; 554 } 555 556 static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk) 557 { 558 unsigned long pll_rate; 559 unsigned int factor; 560 561 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 562 factor = mtk_dpi_calculate_factor(dpi, mode_clk); 563 pll_rate = vm->pixelclock * factor; 564 565 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 566 pll_rate, vm->pixelclock); 567 568 clk_set_rate(dpi->tvd_clk, pll_rate); 569 pll_rate = clk_get_rate(dpi->tvd_clk); 570 571 /* 572 * Depending on the IP version, we may output a different amount of 573 * pixels for each iteration: divide the clock by this number and 574 * adjust the display porches accordingly. 575 */ 576 vm->pixelclock = pll_rate / factor; 577 vm->pixelclock /= dpi->conf->pixels_per_iter; 578 579 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 580 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) 581 clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); 582 else 583 clk_set_rate(dpi->pixel_clk, vm->pixelclock); 584 585 vm->pixelclock = clk_get_rate(dpi->pixel_clk); 586 587 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 588 pll_rate, vm->pixelclock); 589 } 590 591 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 592 struct drm_display_mode *mode) 593 { 594 struct mtk_dpi_polarities dpi_pol; 595 struct mtk_dpi_sync_param hsync; 596 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 597 struct mtk_dpi_sync_param vsync_leven = { 0 }; 598 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 599 struct mtk_dpi_sync_param vsync_reven = { 0 }; 600 struct videomode vm = { 0 }; 601 602 drm_display_mode_to_videomode(mode, &vm); 603 604 if (!dpi->conf->clocked_by_hdmi) 605 mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); 606 607 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 608 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 609 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 610 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 611 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 612 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 613 614 /* 615 * Depending on the IP version, we may output a different amount of 616 * pixels for each iteration: divide the clock by this number and 617 * adjust the display porches accordingly. 618 */ 619 hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter; 620 hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter; 621 hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter; 622 623 hsync.shift_half_line = false; 624 vsync_lodd.sync_width = vm.vsync_len; 625 vsync_lodd.back_porch = vm.vback_porch; 626 vsync_lodd.front_porch = vm.vfront_porch; 627 vsync_lodd.shift_half_line = false; 628 629 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 630 mode->flags & DRM_MODE_FLAG_3D_MASK) { 631 vsync_leven = vsync_lodd; 632 vsync_rodd = vsync_lodd; 633 vsync_reven = vsync_lodd; 634 vsync_leven.shift_half_line = true; 635 vsync_reven.shift_half_line = true; 636 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 637 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 638 vsync_leven = vsync_lodd; 639 vsync_leven.shift_half_line = true; 640 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 641 mode->flags & DRM_MODE_FLAG_3D_MASK) { 642 vsync_rodd = vsync_lodd; 643 } 644 mtk_dpi_sw_reset(dpi, true); 645 mtk_dpi_config_pol(dpi, &dpi_pol); 646 647 mtk_dpi_config_hsync(dpi, &hsync); 648 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 649 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 650 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 651 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 652 653 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 654 mtk_dpi_config_interface(dpi, !!(vm.flags & 655 DISPLAY_FLAGS_INTERLACED)); 656 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 657 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 658 else 659 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 660 661 mtk_dpi_config_channel_limit(dpi); 662 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 663 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 664 mtk_dpi_config_color_format(dpi, dpi->color_format); 665 if (dpi->conf->support_direct_pin) { 666 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 667 mtk_dpi_config_2n_h_fre(dpi); 668 669 /* DPI can connect to either an external bridge or the internal HDMI encoder */ 670 if (dpi->conf->output_1pixel) 671 mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN); 672 else 673 mtk_dpi_dual_edge(dpi); 674 675 mtk_dpi_config_disable_edge(dpi); 676 } 677 if (dpi->conf->input_2p_en_bit) { 678 mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit, 679 dpi->conf->input_2p_en_bit); 680 } 681 mtk_dpi_sw_reset(dpi, false); 682 683 return 0; 684 } 685 686 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 687 struct drm_bridge_state *bridge_state, 688 struct drm_crtc_state *crtc_state, 689 struct drm_connector_state *conn_state, 690 unsigned int *num_output_fmts) 691 { 692 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 693 u32 *output_fmts; 694 695 *num_output_fmts = 0; 696 697 if (!dpi->conf->output_fmts) { 698 dev_err(dpi->dev, "output_fmts should not be null\n"); 699 return NULL; 700 } 701 702 output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts), 703 GFP_KERNEL); 704 if (!output_fmts) 705 return NULL; 706 707 *num_output_fmts = dpi->conf->num_output_fmts; 708 709 memcpy(output_fmts, dpi->conf->output_fmts, 710 sizeof(*output_fmts) * dpi->conf->num_output_fmts); 711 712 return output_fmts; 713 } 714 715 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 716 struct drm_bridge_state *bridge_state, 717 struct drm_crtc_state *crtc_state, 718 struct drm_connector_state *conn_state, 719 u32 output_fmt, 720 unsigned int *num_input_fmts) 721 { 722 u32 *input_fmts; 723 724 *num_input_fmts = 0; 725 726 input_fmts = kcalloc(1, sizeof(*input_fmts), 727 GFP_KERNEL); 728 if (!input_fmts) 729 return NULL; 730 731 *num_input_fmts = 1; 732 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 733 734 return input_fmts; 735 } 736 737 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, 738 struct drm_bridge_state *bridge_state, 739 struct drm_crtc_state *crtc_state, 740 struct drm_connector_state *conn_state) 741 { 742 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 743 unsigned int out_bus_format; 744 745 out_bus_format = bridge_state->output_bus_cfg.format; 746 747 if (out_bus_format == MEDIA_BUS_FMT_FIXED) 748 if (dpi->conf->num_output_fmts) 749 out_bus_format = dpi->conf->output_fmts[0]; 750 751 dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", 752 bridge_state->input_bus_cfg.format, 753 bridge_state->output_bus_cfg.format); 754 755 dpi->output_fmt = out_bus_format; 756 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; 757 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; 758 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 759 if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) 760 dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422; 761 else 762 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; 763 764 return 0; 765 } 766 767 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, 768 struct drm_encoder *encoder, 769 enum drm_bridge_attach_flags flags) 770 { 771 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 772 int ret; 773 774 dpi->next_bridge = devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node, 1, -1); 775 if (IS_ERR(dpi->next_bridge)) { 776 ret = PTR_ERR(dpi->next_bridge); 777 if (ret == -EPROBE_DEFER) 778 return ret; 779 780 /* Old devicetree has only one endpoint */ 781 dpi->next_bridge = devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node, 0, 0); 782 if (IS_ERR(dpi->next_bridge)) 783 return dev_err_probe(dpi->dev, PTR_ERR(dpi->next_bridge), 784 "Failed to get bridge\n"); 785 } 786 787 return drm_bridge_attach(encoder, dpi->next_bridge, 788 &dpi->bridge, flags); 789 } 790 791 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, 792 const struct drm_display_mode *mode, 793 const struct drm_display_mode *adjusted_mode) 794 { 795 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 796 797 drm_mode_copy(&dpi->mode, adjusted_mode); 798 } 799 800 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) 801 { 802 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 803 804 mtk_dpi_power_off(dpi); 805 806 if (dpi->pinctrl && dpi->pins_gpio) 807 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 808 } 809 810 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) 811 { 812 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 813 814 if (dpi->pinctrl && dpi->pins_dpi) 815 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); 816 817 mtk_dpi_power_on(dpi); 818 mtk_dpi_set_display_mode(dpi, &dpi->mode); 819 mtk_dpi_enable(dpi); 820 } 821 822 static enum drm_mode_status 823 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, 824 const struct drm_display_info *info, 825 const struct drm_display_mode *mode) 826 { 827 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 828 829 if (mode->clock > dpi->conf->max_clock_khz) 830 return MODE_CLOCK_HIGH; 831 832 return MODE_OK; 833 } 834 835 static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg) 836 { 837 struct mtk_dpi *dpi = m->private; 838 bool en; 839 u32 val; 840 841 if (!dpi) 842 return -EINVAL; 843 844 val = readl(dpi->regs + DPI_PATTERN0); 845 en = val & DPI_PAT_EN; 846 val = FIELD_GET(DPI_PAT_SEL, val); 847 848 seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled"); 849 850 if (en) { 851 seq_printf(m, "Internal pattern %d: ", val); 852 switch (val) { 853 case 0: 854 seq_puts(m, "256 Vertical Gray\n"); 855 break; 856 case 1: 857 seq_puts(m, "1024 Vertical Gray\n"); 858 break; 859 case 2: 860 seq_puts(m, "256 Horizontal Gray\n"); 861 break; 862 case 3: 863 seq_puts(m, "1024 Horizontal Gray\n"); 864 break; 865 case 4: 866 seq_puts(m, "Vertical Color bars\n"); 867 break; 868 case 6: 869 seq_puts(m, "Frame border\n"); 870 break; 871 case 7: 872 seq_puts(m, "Dot moire\n"); 873 break; 874 default: 875 seq_puts(m, "Invalid selection\n"); 876 break; 877 } 878 } 879 880 return 0; 881 } 882 883 static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf, 884 size_t len, loff_t *offp) 885 { 886 struct seq_file *m = file->private_data; 887 u32 en, type; 888 char buf[6]; 889 890 if (!m || !m->private || *offp || len > sizeof(buf) - 1) 891 return -EINVAL; 892 893 memset(buf, 0, sizeof(buf)); 894 if (copy_from_user(buf, ubuf, len)) 895 return -EFAULT; 896 897 if (sscanf(buf, "%u %u", &en, &type) != 2) 898 return -EINVAL; 899 900 if (en < 0 || en > 1 || type < 0 || type > 7) 901 return -EINVAL; 902 903 mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en); 904 return len; 905 } 906 907 static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file) 908 { 909 return single_open(file, mtk_dpi_debug_tp_show, inode->i_private); 910 } 911 912 static const struct file_operations mtk_dpi_debug_tp_fops = { 913 .owner = THIS_MODULE, 914 .open = mtk_dpi_debug_tp_open, 915 .read = seq_read, 916 .write = mtk_dpi_debug_tp_write, 917 .llseek = seq_lseek, 918 .release = single_release, 919 }; 920 921 static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 922 { 923 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 924 925 debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops); 926 } 927 928 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { 929 .attach = mtk_dpi_bridge_attach, 930 .mode_set = mtk_dpi_bridge_mode_set, 931 .mode_valid = mtk_dpi_bridge_mode_valid, 932 .disable = mtk_dpi_bridge_disable, 933 .enable = mtk_dpi_bridge_enable, 934 .atomic_check = mtk_dpi_bridge_atomic_check, 935 .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, 936 .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, 937 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 938 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 939 .atomic_reset = drm_atomic_helper_bridge_reset, 940 .debugfs_init = mtk_dpi_debugfs_init, 941 }; 942 943 void mtk_dpi_start(struct device *dev) 944 { 945 struct mtk_dpi *dpi = dev_get_drvdata(dev); 946 947 if (!dpi->conf->clocked_by_hdmi) 948 mtk_dpi_power_on(dpi); 949 } 950 951 void mtk_dpi_stop(struct device *dev) 952 { 953 struct mtk_dpi *dpi = dev_get_drvdata(dev); 954 955 if (!dpi->conf->clocked_by_hdmi) 956 mtk_dpi_power_off(dpi); 957 } 958 959 unsigned int mtk_dpi_encoder_index(struct device *dev) 960 { 961 struct mtk_dpi *dpi = dev_get_drvdata(dev); 962 unsigned int encoder_index = drm_encoder_index(&dpi->encoder); 963 964 dev_dbg(dev, "encoder index:%d\n", encoder_index); 965 return encoder_index; 966 } 967 968 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 969 { 970 struct mtk_dpi *dpi = dev_get_drvdata(dev); 971 struct drm_device *drm_dev = data; 972 struct mtk_drm_private *priv = drm_dev->dev_private; 973 int ret; 974 975 dpi->mmsys_dev = priv->mmsys_dev; 976 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, 977 DRM_MODE_ENCODER_TMDS); 978 if (ret) { 979 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 980 return ret; 981 } 982 983 ret = mtk_find_possible_crtcs(drm_dev, dpi->dev); 984 if (ret < 0) 985 goto err_cleanup; 986 dpi->encoder.possible_crtcs = ret; 987 988 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 989 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 990 if (ret) 991 goto err_cleanup; 992 993 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); 994 if (IS_ERR(dpi->connector)) { 995 dev_err(dev, "Unable to create bridge connector\n"); 996 ret = PTR_ERR(dpi->connector); 997 goto err_cleanup; 998 } 999 drm_connector_attach_encoder(dpi->connector, &dpi->encoder); 1000 1001 return 0; 1002 1003 err_cleanup: 1004 drm_encoder_cleanup(&dpi->encoder); 1005 return ret; 1006 } 1007 1008 static void mtk_dpi_unbind(struct device *dev, struct device *master, 1009 void *data) 1010 { 1011 struct mtk_dpi *dpi = dev_get_drvdata(dev); 1012 1013 drm_encoder_cleanup(&dpi->encoder); 1014 } 1015 1016 static const struct component_ops mtk_dpi_component_ops = { 1017 .bind = mtk_dpi_bind, 1018 .unbind = mtk_dpi_unbind, 1019 }; 1020 1021 static const u32 mt8173_output_fmts[] = { 1022 MEDIA_BUS_FMT_RGB888_1X24, 1023 }; 1024 1025 static const u32 mt8183_output_fmts[] = { 1026 MEDIA_BUS_FMT_RGB888_2X12_LE, 1027 MEDIA_BUS_FMT_RGB888_2X12_BE, 1028 }; 1029 1030 static const u32 mt8195_output_fmts[] = { 1031 MEDIA_BUS_FMT_RGB888_1X24, 1032 MEDIA_BUS_FMT_YUYV8_1X16, 1033 }; 1034 1035 static const struct mtk_dpi_factor dpi_factor_mt2701[] = { 1036 { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 } 1037 }; 1038 1039 static const struct mtk_dpi_factor dpi_factor_mt8173[] = { 1040 { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 } 1041 }; 1042 1043 static const struct mtk_dpi_factor dpi_factor_mt8183[] = { 1044 { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 } 1045 }; 1046 1047 static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = { 1048 { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 } 1049 }; 1050 1051 static const struct mtk_dpi_conf mt8173_conf = { 1052 .dpi_factor = dpi_factor_mt8173, 1053 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173), 1054 .reg_h_fre_con = 0xe0, 1055 .max_clock_khz = 300000, 1056 .output_fmts = mt8173_output_fmts, 1057 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 1058 .pixels_per_iter = 1, 1059 .is_ck_de_pol = true, 1060 .swap_input_support = true, 1061 .support_direct_pin = true, 1062 .dimension_mask = HPW_MASK, 1063 .hvsize_mask = HSIZE_MASK, 1064 .channel_swap_shift = CH_SWAP, 1065 .yuv422_en_bit = YUV422_EN, 1066 .csc_enable_bit = CSC_ENABLE, 1067 }; 1068 1069 static const struct mtk_dpi_conf mt2701_conf = { 1070 .dpi_factor = dpi_factor_mt2701, 1071 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701), 1072 .reg_h_fre_con = 0xb0, 1073 .edge_sel_en = true, 1074 .max_clock_khz = 150000, 1075 .output_fmts = mt8173_output_fmts, 1076 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 1077 .pixels_per_iter = 1, 1078 .is_ck_de_pol = true, 1079 .swap_input_support = true, 1080 .support_direct_pin = true, 1081 .dimension_mask = HPW_MASK, 1082 .hvsize_mask = HSIZE_MASK, 1083 .channel_swap_shift = CH_SWAP, 1084 .yuv422_en_bit = YUV422_EN, 1085 .csc_enable_bit = CSC_ENABLE, 1086 }; 1087 1088 static const struct mtk_dpi_conf mt8183_conf = { 1089 .dpi_factor = dpi_factor_mt8183, 1090 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1091 .reg_h_fre_con = 0xe0, 1092 .max_clock_khz = 100000, 1093 .output_fmts = mt8183_output_fmts, 1094 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1095 .pixels_per_iter = 1, 1096 .is_ck_de_pol = true, 1097 .swap_input_support = true, 1098 .support_direct_pin = true, 1099 .dimension_mask = HPW_MASK, 1100 .hvsize_mask = HSIZE_MASK, 1101 .channel_swap_shift = CH_SWAP, 1102 .yuv422_en_bit = YUV422_EN, 1103 .csc_enable_bit = CSC_ENABLE, 1104 }; 1105 1106 static const struct mtk_dpi_conf mt8186_conf = { 1107 .dpi_factor = dpi_factor_mt8183, 1108 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1109 .reg_h_fre_con = 0xe0, 1110 .max_clock_khz = 150000, 1111 .output_fmts = mt8183_output_fmts, 1112 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1113 .edge_cfg_in_mmsys = true, 1114 .pixels_per_iter = 1, 1115 .is_ck_de_pol = true, 1116 .swap_input_support = true, 1117 .support_direct_pin = true, 1118 .dimension_mask = HPW_MASK, 1119 .hvsize_mask = HSIZE_MASK, 1120 .channel_swap_shift = CH_SWAP, 1121 .yuv422_en_bit = YUV422_EN, 1122 .csc_enable_bit = CSC_ENABLE, 1123 }; 1124 1125 static const struct mtk_dpi_conf mt8192_conf = { 1126 .dpi_factor = dpi_factor_mt8183, 1127 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), 1128 .reg_h_fre_con = 0xe0, 1129 .max_clock_khz = 150000, 1130 .output_fmts = mt8183_output_fmts, 1131 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1132 .pixels_per_iter = 1, 1133 .is_ck_de_pol = true, 1134 .swap_input_support = true, 1135 .support_direct_pin = true, 1136 .dimension_mask = HPW_MASK, 1137 .hvsize_mask = HSIZE_MASK, 1138 .channel_swap_shift = CH_SWAP, 1139 .yuv422_en_bit = YUV422_EN, 1140 .csc_enable_bit = CSC_ENABLE, 1141 }; 1142 1143 static const struct mtk_dpi_conf mt8195_conf = { 1144 .max_clock_khz = 594000, 1145 .output_fmts = mt8183_output_fmts, 1146 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 1147 .pixels_per_iter = 1, 1148 .is_ck_de_pol = true, 1149 .swap_input_support = true, 1150 .support_direct_pin = true, 1151 .dimension_mask = HPW_MASK, 1152 .hvsize_mask = HSIZE_MASK, 1153 .channel_swap_shift = CH_SWAP, 1154 .yuv422_en_bit = YUV422_EN, 1155 .csc_enable_bit = CSC_ENABLE, 1156 .input_2p_en_bit = DPI_INPUT_2P_EN, 1157 .clocked_by_hdmi = true, 1158 .output_1pixel = true, 1159 }; 1160 1161 static const struct mtk_dpi_conf mt8195_dpintf_conf = { 1162 .dpi_factor = dpi_factor_mt8195_dp_intf, 1163 .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), 1164 .max_clock_khz = 600000, 1165 .output_fmts = mt8195_output_fmts, 1166 .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), 1167 .pixels_per_iter = 4, 1168 .dimension_mask = DPINTF_HPW_MASK, 1169 .hvsize_mask = DPINTF_HSIZE_MASK, 1170 .channel_swap_shift = DPINTF_CH_SWAP, 1171 .yuv422_en_bit = DPINTF_YUV422_EN, 1172 .csc_enable_bit = DPINTF_CSC_ENABLE, 1173 .input_2p_en_bit = DPINTF_INPUT_2P_EN, 1174 }; 1175 1176 static int mtk_dpi_probe(struct platform_device *pdev) 1177 { 1178 struct device *dev = &pdev->dev; 1179 struct mtk_dpi *dpi; 1180 int ret; 1181 1182 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); 1183 if (!dpi) 1184 return -ENOMEM; 1185 1186 dpi->dev = dev; 1187 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 1188 dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 1189 1190 dpi->pinctrl = devm_pinctrl_get(&pdev->dev); 1191 if (IS_ERR(dpi->pinctrl)) { 1192 dpi->pinctrl = NULL; 1193 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); 1194 } 1195 if (dpi->pinctrl) { 1196 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep"); 1197 if (IS_ERR(dpi->pins_gpio)) { 1198 dpi->pins_gpio = NULL; 1199 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); 1200 } 1201 if (dpi->pins_gpio) 1202 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 1203 1204 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default"); 1205 if (IS_ERR(dpi->pins_dpi)) { 1206 dpi->pins_dpi = NULL; 1207 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); 1208 } 1209 } 1210 dpi->regs = devm_platform_ioremap_resource(pdev, 0); 1211 if (IS_ERR(dpi->regs)) 1212 return dev_err_probe(dev, PTR_ERR(dpi->regs), 1213 "Failed to ioremap mem resource\n"); 1214 1215 dpi->engine_clk = devm_clk_get(dev, "engine"); 1216 if (IS_ERR(dpi->engine_clk)) 1217 return dev_err_probe(dev, PTR_ERR(dpi->engine_clk), 1218 "Failed to get engine clock\n"); 1219 1220 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 1221 if (IS_ERR(dpi->pixel_clk)) 1222 return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), 1223 "Failed to get pixel clock\n"); 1224 1225 dpi->tvd_clk = devm_clk_get(dev, "pll"); 1226 if (IS_ERR(dpi->tvd_clk)) 1227 return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk), 1228 "Failed to get tvdpll clock\n"); 1229 1230 dpi->irq = platform_get_irq(pdev, 0); 1231 if (dpi->irq < 0) 1232 return dpi->irq; 1233 1234 platform_set_drvdata(pdev, dpi); 1235 1236 dpi->bridge.funcs = &mtk_dpi_bridge_funcs; 1237 dpi->bridge.of_node = dev->of_node; 1238 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; 1239 1240 ret = devm_drm_bridge_add(dev, &dpi->bridge); 1241 if (ret) 1242 return ret; 1243 1244 ret = component_add(dev, &mtk_dpi_component_ops); 1245 if (ret) 1246 return dev_err_probe(dev, ret, "Failed to add component.\n"); 1247 1248 return 0; 1249 } 1250 1251 static void mtk_dpi_remove(struct platform_device *pdev) 1252 { 1253 component_del(&pdev->dev, &mtk_dpi_component_ops); 1254 } 1255 1256 static const struct of_device_id mtk_dpi_of_ids[] = { 1257 { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf }, 1258 { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf }, 1259 { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf }, 1260 { .compatible = "mediatek,mt8186-dpi", .data = &mt8186_conf }, 1261 { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, 1262 { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, 1263 { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, 1264 { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf }, 1265 { /* sentinel */ }, 1266 }; 1267 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); 1268 1269 struct platform_driver mtk_dpi_driver = { 1270 .probe = mtk_dpi_probe, 1271 .remove = mtk_dpi_remove, 1272 .driver = { 1273 .name = "mediatek-dpi", 1274 .of_match_table = mtk_dpi_of_ids, 1275 }, 1276 }; 1277