1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <drm/drm_blend.h> 7 #include <drm/drm_fourcc.h> 8 #include <drm/drm_framebuffer.h> 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/soc/mediatek/mtk-cmdq.h> 17 18 #include "mtk_crtc.h" 19 #include "mtk_ddp_comp.h" 20 #include "mtk_disp_drv.h" 21 #include "mtk_drm_drv.h" 22 23 #define DISP_REG_OVL_INTEN 0x0004 24 #define OVL_FME_CPL_INT BIT(1) 25 #define DISP_REG_OVL_INTSTA 0x0008 26 #define DISP_REG_OVL_EN 0x000c 27 #define DISP_REG_OVL_RST 0x0014 28 #define DISP_REG_OVL_ROI_SIZE 0x0020 29 #define DISP_REG_OVL_DATAPATH_CON 0x0024 30 #define OVL_LAYER_SMI_ID_EN BIT(0) 31 #define OVL_BGCLR_SEL_IN BIT(2) 32 #define OVL_LAYER_AFBC_EN(n) BIT(4+n) 33 #define DISP_REG_OVL_ROI_BGCLR 0x0028 34 #define DISP_REG_OVL_SRC_CON 0x002c 35 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 36 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 37 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 38 #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) 39 #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) 40 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 41 #define OVL_CONST_BLEND BIT(28) 42 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 43 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 44 #define DISP_REG_OVL_ADDR_MT2701 0x0040 45 #define DISP_REG_OVL_CLRFMT_EXT 0x02d0 46 #define OVL_CON_CLRFMT_BIT_DEPTH_MASK(n) (GENMASK(1, 0) << (4 * (n))) 47 #define OVL_CON_CLRFMT_BIT_DEPTH(depth, n) ((depth) << (4 * (n))) 48 #define OVL_CON_CLRFMT_8_BIT (0) 49 #define OVL_CON_CLRFMT_10_BIT (1) 50 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 51 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 52 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) 53 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08) 54 55 #define GMC_THRESHOLD_BITS 16 56 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) 57 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) 58 59 #define OVL_CON_BYTE_SWAP BIT(24) 60 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) 61 #define OVL_CON_CLRFMT_RGB (1 << 12) 62 #define OVL_CON_CLRFMT_ARGB8888 (2 << 12) 63 #define OVL_CON_CLRFMT_RGBA8888 (3 << 12) 64 #define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP) 65 #define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP) 66 #define OVL_CON_CLRFMT_UYVY (4 << 12) 67 #define OVL_CON_CLRFMT_YUYV (5 << 12) 68 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 69 0 : OVL_CON_CLRFMT_RGB) 70 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 71 OVL_CON_CLRFMT_RGB : 0) 72 #define OVL_CON_AEN BIT(8) 73 #define OVL_CON_ALPHA 0xff 74 #define OVL_CON_VIRT_FLIP BIT(9) 75 #define OVL_CON_HORZ_FLIP BIT(10) 76 77 #define OVL_COLOR_ALPHA GENMASK(31, 24) 78 79 static inline bool is_10bit_rgb(u32 fmt) 80 { 81 switch (fmt) { 82 case DRM_FORMAT_XRGB2101010: 83 case DRM_FORMAT_ARGB2101010: 84 case DRM_FORMAT_RGBX1010102: 85 case DRM_FORMAT_RGBA1010102: 86 case DRM_FORMAT_XBGR2101010: 87 case DRM_FORMAT_ABGR2101010: 88 case DRM_FORMAT_BGRX1010102: 89 case DRM_FORMAT_BGRA1010102: 90 return true; 91 } 92 return false; 93 } 94 95 static const u32 mt8173_formats[] = { 96 DRM_FORMAT_XRGB8888, 97 DRM_FORMAT_ARGB8888, 98 DRM_FORMAT_BGRX8888, 99 DRM_FORMAT_BGRA8888, 100 DRM_FORMAT_ABGR8888, 101 DRM_FORMAT_XBGR8888, 102 DRM_FORMAT_RGB888, 103 DRM_FORMAT_BGR888, 104 DRM_FORMAT_RGB565, 105 DRM_FORMAT_UYVY, 106 DRM_FORMAT_YUYV, 107 }; 108 109 static const u32 mt8195_formats[] = { 110 DRM_FORMAT_XRGB8888, 111 DRM_FORMAT_ARGB8888, 112 DRM_FORMAT_XRGB2101010, 113 DRM_FORMAT_ARGB2101010, 114 DRM_FORMAT_BGRX8888, 115 DRM_FORMAT_BGRA8888, 116 DRM_FORMAT_BGRX1010102, 117 DRM_FORMAT_BGRA1010102, 118 DRM_FORMAT_ABGR8888, 119 DRM_FORMAT_XBGR8888, 120 DRM_FORMAT_XBGR2101010, 121 DRM_FORMAT_ABGR2101010, 122 DRM_FORMAT_RGBX8888, 123 DRM_FORMAT_RGBA8888, 124 DRM_FORMAT_RGBX1010102, 125 DRM_FORMAT_RGBA1010102, 126 DRM_FORMAT_RGB888, 127 DRM_FORMAT_BGR888, 128 DRM_FORMAT_RGB565, 129 DRM_FORMAT_UYVY, 130 DRM_FORMAT_YUYV, 131 }; 132 133 struct mtk_disp_ovl_data { 134 unsigned int addr; 135 unsigned int gmc_bits; 136 unsigned int layer_nr; 137 bool fmt_rgb565_is_0; 138 bool smi_id_en; 139 bool supports_afbc; 140 const u32 *formats; 141 size_t num_formats; 142 bool supports_clrfmt_ext; 143 }; 144 145 /* 146 * struct mtk_disp_ovl - DISP_OVL driver structure 147 * @crtc: associated crtc to report vblank events to 148 * @data: platform data 149 */ 150 struct mtk_disp_ovl { 151 struct drm_crtc *crtc; 152 struct clk *clk; 153 void __iomem *regs; 154 struct cmdq_client_reg cmdq_reg; 155 const struct mtk_disp_ovl_data *data; 156 void (*vblank_cb)(void *data); 157 void *vblank_cb_data; 158 }; 159 160 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 161 { 162 struct mtk_disp_ovl *priv = dev_id; 163 164 /* Clear frame completion interrupt */ 165 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); 166 167 if (!priv->vblank_cb) 168 return IRQ_NONE; 169 170 priv->vblank_cb(priv->vblank_cb_data); 171 172 return IRQ_HANDLED; 173 } 174 175 void mtk_ovl_register_vblank_cb(struct device *dev, 176 void (*vblank_cb)(void *), 177 void *vblank_cb_data) 178 { 179 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 180 181 ovl->vblank_cb = vblank_cb; 182 ovl->vblank_cb_data = vblank_cb_data; 183 } 184 185 void mtk_ovl_unregister_vblank_cb(struct device *dev) 186 { 187 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 188 189 ovl->vblank_cb = NULL; 190 ovl->vblank_cb_data = NULL; 191 } 192 193 void mtk_ovl_enable_vblank(struct device *dev) 194 { 195 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 196 197 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 198 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); 199 } 200 201 void mtk_ovl_disable_vblank(struct device *dev) 202 { 203 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 204 205 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); 206 } 207 208 const u32 *mtk_ovl_get_formats(struct device *dev) 209 { 210 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 211 212 return ovl->data->formats; 213 } 214 215 size_t mtk_ovl_get_num_formats(struct device *dev) 216 { 217 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 218 219 return ovl->data->num_formats; 220 } 221 222 int mtk_ovl_clk_enable(struct device *dev) 223 { 224 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 225 226 return clk_prepare_enable(ovl->clk); 227 } 228 229 void mtk_ovl_clk_disable(struct device *dev) 230 { 231 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 232 233 clk_disable_unprepare(ovl->clk); 234 } 235 236 void mtk_ovl_start(struct device *dev) 237 { 238 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 239 240 if (ovl->data->smi_id_en) { 241 unsigned int reg; 242 243 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 244 reg = reg | OVL_LAYER_SMI_ID_EN; 245 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 246 } 247 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); 248 } 249 250 void mtk_ovl_stop(struct device *dev) 251 { 252 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 253 254 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); 255 if (ovl->data->smi_id_en) { 256 unsigned int reg; 257 258 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 259 reg = reg & ~OVL_LAYER_SMI_ID_EN; 260 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 261 } 262 } 263 264 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt, 265 int idx, bool enabled) 266 { 267 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0, 268 &ovl->cmdq_reg, ovl->regs, 269 DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); 270 } 271 272 static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, 273 struct cmdq_pkt *cmdq_pkt) 274 { 275 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 276 unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; 277 278 if (!ovl->data->supports_clrfmt_ext) 279 return; 280 281 if (is_10bit_rgb(format)) 282 bit_depth = OVL_CON_CLRFMT_10_BIT; 283 284 mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx), 285 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT, 286 OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx)); 287 } 288 289 void mtk_ovl_config(struct device *dev, unsigned int w, 290 unsigned int h, unsigned int vrefresh, 291 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 292 { 293 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 294 295 if (w != 0 && h != 0) 296 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, 297 DISP_REG_OVL_ROI_SIZE); 298 299 /* 300 * The background color must be opaque black (ARGB), 301 * otherwise the alpha blending will have no effect 302 */ 303 mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, 304 ovl->regs, DISP_REG_OVL_ROI_BGCLR); 305 306 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); 307 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); 308 } 309 310 unsigned int mtk_ovl_layer_nr(struct device *dev) 311 { 312 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 313 314 return ovl->data->layer_nr; 315 } 316 317 unsigned int mtk_ovl_supported_rotations(struct device *dev) 318 { 319 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 320 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 321 } 322 323 int mtk_ovl_layer_check(struct device *dev, unsigned int idx, 324 struct mtk_plane_state *mtk_state) 325 { 326 struct drm_plane_state *state = &mtk_state->base; 327 328 /* check if any unsupported rotation is set */ 329 if (state->rotation & ~mtk_ovl_supported_rotations(dev)) 330 return -EINVAL; 331 332 /* 333 * TODO: Rotating/reflecting YUV buffers is not supported at this time. 334 * Only RGB[AX] variants are supported. 335 * Since DRM_MODE_ROTATE_0 means "no rotation", we should not 336 * reject layers with this property. 337 */ 338 if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) 339 return -EINVAL; 340 341 return 0; 342 } 343 344 void mtk_ovl_layer_on(struct device *dev, unsigned int idx, 345 struct cmdq_pkt *cmdq_pkt) 346 { 347 unsigned int gmc_thrshd_l; 348 unsigned int gmc_thrshd_h; 349 unsigned int gmc_value; 350 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 351 352 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, 353 DISP_REG_OVL_RDMA_CTRL(idx)); 354 gmc_thrshd_l = GMC_THRESHOLD_LOW >> 355 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 356 gmc_thrshd_h = GMC_THRESHOLD_HIGH >> 357 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 358 if (ovl->data->gmc_bits == 10) 359 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; 360 else 361 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | 362 gmc_thrshd_h << 16 | gmc_thrshd_h << 24; 363 mtk_ddp_write(cmdq_pkt, gmc_value, 364 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); 365 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, 366 DISP_REG_OVL_SRC_CON, BIT(idx)); 367 } 368 369 void mtk_ovl_layer_off(struct device *dev, unsigned int idx, 370 struct cmdq_pkt *cmdq_pkt) 371 { 372 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 373 374 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, 375 DISP_REG_OVL_SRC_CON, BIT(idx)); 376 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, 377 DISP_REG_OVL_RDMA_CTRL(idx)); 378 } 379 380 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 381 { 382 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 383 * is defined in mediatek HW data sheet. 384 * The alphabet order in XXX is no relation to data 385 * arrangement in memory. 386 */ 387 switch (fmt) { 388 default: 389 case DRM_FORMAT_RGB565: 390 return OVL_CON_CLRFMT_RGB565(ovl); 391 case DRM_FORMAT_BGR565: 392 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; 393 case DRM_FORMAT_RGB888: 394 return OVL_CON_CLRFMT_RGB888(ovl); 395 case DRM_FORMAT_BGR888: 396 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; 397 case DRM_FORMAT_RGBX8888: 398 case DRM_FORMAT_RGBA8888: 399 case DRM_FORMAT_RGBX1010102: 400 case DRM_FORMAT_RGBA1010102: 401 return OVL_CON_CLRFMT_RGBA8888; 402 case DRM_FORMAT_BGRX8888: 403 case DRM_FORMAT_BGRA8888: 404 case DRM_FORMAT_BGRX1010102: 405 case DRM_FORMAT_BGRA1010102: 406 return OVL_CON_CLRFMT_BGRA8888; 407 case DRM_FORMAT_XRGB8888: 408 case DRM_FORMAT_ARGB8888: 409 case DRM_FORMAT_XRGB2101010: 410 case DRM_FORMAT_ARGB2101010: 411 return OVL_CON_CLRFMT_ARGB8888; 412 case DRM_FORMAT_XBGR8888: 413 case DRM_FORMAT_ABGR8888: 414 case DRM_FORMAT_XBGR2101010: 415 case DRM_FORMAT_ABGR2101010: 416 return OVL_CON_CLRFMT_ABGR8888; 417 case DRM_FORMAT_UYVY: 418 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; 419 case DRM_FORMAT_YUYV: 420 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; 421 } 422 } 423 424 void mtk_ovl_layer_config(struct device *dev, unsigned int idx, 425 struct mtk_plane_state *state, 426 struct cmdq_pkt *cmdq_pkt) 427 { 428 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 429 struct mtk_plane_pending_state *pending = &state->pending; 430 unsigned int addr = pending->addr; 431 unsigned int hdr_addr = pending->hdr_addr; 432 unsigned int pitch = pending->pitch; 433 unsigned int hdr_pitch = pending->hdr_pitch; 434 unsigned int fmt = pending->format; 435 unsigned int offset = (pending->y << 16) | pending->x; 436 unsigned int src_size = (pending->height << 16) | pending->width; 437 unsigned int ignore_pixel_alpha = 0; 438 unsigned int con; 439 bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; 440 union overlay_pitch { 441 struct split_pitch { 442 u16 lsb; 443 u16 msb; 444 } split_pitch; 445 u32 pitch; 446 } overlay_pitch; 447 448 overlay_pitch.pitch = pitch; 449 450 if (!pending->enable) { 451 mtk_ovl_layer_off(dev, idx, cmdq_pkt); 452 return; 453 } 454 455 con = ovl_fmt_convert(ovl, fmt); 456 if (state->base.fb) { 457 con |= OVL_CON_AEN; 458 con |= state->base.alpha & OVL_CON_ALPHA; 459 } 460 461 /* CONST_BLD must be enabled for XRGB formats although the alpha channel 462 * can be ignored, or OVL will still read the value from memory. 463 * For RGB888 related formats, whether CONST_BLD is enabled or not won't 464 * affect the result. Therefore we use !has_alpha as the condition. 465 */ 466 if (state->base.fb && !state->base.fb->format->has_alpha) 467 ignore_pixel_alpha = OVL_CONST_BLEND; 468 469 if (pending->rotation & DRM_MODE_REFLECT_Y) { 470 con |= OVL_CON_VIRT_FLIP; 471 addr += (pending->height - 1) * pending->pitch; 472 } 473 474 if (pending->rotation & DRM_MODE_REFLECT_X) { 475 con |= OVL_CON_HORZ_FLIP; 476 addr += pending->pitch - 1; 477 } 478 479 if (ovl->data->supports_afbc) 480 mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc); 481 482 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, 483 DISP_REG_OVL_CON(idx)); 484 mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha, 485 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); 486 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, 487 DISP_REG_OVL_SRC_SIZE(idx)); 488 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, 489 DISP_REG_OVL_OFFSET(idx)); 490 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, 491 DISP_REG_OVL_ADDR(ovl, idx)); 492 493 if (is_afbc) { 494 mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs, 495 DISP_REG_OVL_HDR_ADDR(ovl, idx)); 496 mtk_ddp_write_relaxed(cmdq_pkt, 497 OVL_PITCH_MSB_2ND_SUBBUF | overlay_pitch.split_pitch.msb, 498 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); 499 mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs, 500 DISP_REG_OVL_HDR_PITCH(ovl, idx)); 501 } else { 502 mtk_ddp_write_relaxed(cmdq_pkt, 503 overlay_pitch.split_pitch.msb, 504 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); 505 } 506 507 mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); 508 mtk_ovl_layer_on(dev, idx, cmdq_pkt); 509 } 510 511 void mtk_ovl_bgclr_in_on(struct device *dev) 512 { 513 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 514 unsigned int reg; 515 516 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 517 reg = reg | OVL_BGCLR_SEL_IN; 518 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 519 } 520 521 void mtk_ovl_bgclr_in_off(struct device *dev) 522 { 523 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 524 unsigned int reg; 525 526 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 527 reg = reg & ~OVL_BGCLR_SEL_IN; 528 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 529 } 530 531 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 532 void *data) 533 { 534 return 0; 535 } 536 537 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 538 void *data) 539 { 540 } 541 542 static const struct component_ops mtk_disp_ovl_component_ops = { 543 .bind = mtk_disp_ovl_bind, 544 .unbind = mtk_disp_ovl_unbind, 545 }; 546 547 static int mtk_disp_ovl_probe(struct platform_device *pdev) 548 { 549 struct device *dev = &pdev->dev; 550 struct mtk_disp_ovl *priv; 551 struct resource *res; 552 int irq; 553 int ret; 554 555 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 556 if (!priv) 557 return -ENOMEM; 558 559 irq = platform_get_irq(pdev, 0); 560 if (irq < 0) 561 return irq; 562 563 priv->clk = devm_clk_get(dev, NULL); 564 if (IS_ERR(priv->clk)) 565 return dev_err_probe(dev, PTR_ERR(priv->clk), 566 "failed to get ovl clk\n"); 567 568 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 569 priv->regs = devm_ioremap_resource(dev, res); 570 if (IS_ERR(priv->regs)) 571 return dev_err_probe(dev, PTR_ERR(priv->regs), 572 "failed to ioremap ovl\n"); 573 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 574 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); 575 if (ret) 576 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 577 #endif 578 579 priv->data = of_device_get_match_data(dev); 580 platform_set_drvdata(pdev, priv); 581 582 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 583 IRQF_TRIGGER_NONE, dev_name(dev), priv); 584 if (ret < 0) 585 return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq); 586 587 pm_runtime_enable(dev); 588 589 ret = component_add(dev, &mtk_disp_ovl_component_ops); 590 if (ret) { 591 pm_runtime_disable(dev); 592 return dev_err_probe(dev, ret, "Failed to add component\n"); 593 } 594 595 return 0; 596 } 597 598 static void mtk_disp_ovl_remove(struct platform_device *pdev) 599 { 600 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); 601 pm_runtime_disable(&pdev->dev); 602 } 603 604 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { 605 .addr = DISP_REG_OVL_ADDR_MT2701, 606 .gmc_bits = 8, 607 .layer_nr = 4, 608 .fmt_rgb565_is_0 = false, 609 .formats = mt8173_formats, 610 .num_formats = ARRAY_SIZE(mt8173_formats), 611 }; 612 613 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 614 .addr = DISP_REG_OVL_ADDR_MT8173, 615 .gmc_bits = 8, 616 .layer_nr = 4, 617 .fmt_rgb565_is_0 = true, 618 .formats = mt8173_formats, 619 .num_formats = ARRAY_SIZE(mt8173_formats), 620 }; 621 622 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { 623 .addr = DISP_REG_OVL_ADDR_MT8173, 624 .gmc_bits = 10, 625 .layer_nr = 4, 626 .fmt_rgb565_is_0 = true, 627 .formats = mt8173_formats, 628 .num_formats = ARRAY_SIZE(mt8173_formats), 629 }; 630 631 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { 632 .addr = DISP_REG_OVL_ADDR_MT8173, 633 .gmc_bits = 10, 634 .layer_nr = 2, 635 .fmt_rgb565_is_0 = true, 636 .formats = mt8173_formats, 637 .num_formats = ARRAY_SIZE(mt8173_formats), 638 }; 639 640 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { 641 .addr = DISP_REG_OVL_ADDR_MT8173, 642 .gmc_bits = 10, 643 .layer_nr = 4, 644 .fmt_rgb565_is_0 = true, 645 .smi_id_en = true, 646 .formats = mt8173_formats, 647 .num_formats = ARRAY_SIZE(mt8173_formats), 648 }; 649 650 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { 651 .addr = DISP_REG_OVL_ADDR_MT8173, 652 .gmc_bits = 10, 653 .layer_nr = 2, 654 .fmt_rgb565_is_0 = true, 655 .smi_id_en = true, 656 .formats = mt8173_formats, 657 .num_formats = ARRAY_SIZE(mt8173_formats), 658 }; 659 660 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { 661 .addr = DISP_REG_OVL_ADDR_MT8173, 662 .gmc_bits = 10, 663 .layer_nr = 4, 664 .fmt_rgb565_is_0 = true, 665 .smi_id_en = true, 666 .supports_afbc = true, 667 .formats = mt8195_formats, 668 .num_formats = ARRAY_SIZE(mt8195_formats), 669 .supports_clrfmt_ext = true, 670 }; 671 672 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 673 { .compatible = "mediatek,mt2701-disp-ovl", 674 .data = &mt2701_ovl_driver_data}, 675 { .compatible = "mediatek,mt8173-disp-ovl", 676 .data = &mt8173_ovl_driver_data}, 677 { .compatible = "mediatek,mt8183-disp-ovl", 678 .data = &mt8183_ovl_driver_data}, 679 { .compatible = "mediatek,mt8183-disp-ovl-2l", 680 .data = &mt8183_ovl_2l_driver_data}, 681 { .compatible = "mediatek,mt8192-disp-ovl", 682 .data = &mt8192_ovl_driver_data}, 683 { .compatible = "mediatek,mt8192-disp-ovl-2l", 684 .data = &mt8192_ovl_2l_driver_data}, 685 { .compatible = "mediatek,mt8195-disp-ovl", 686 .data = &mt8195_ovl_driver_data}, 687 {}, 688 }; 689 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 690 691 struct platform_driver mtk_disp_ovl_driver = { 692 .probe = mtk_disp_ovl_probe, 693 .remove_new = mtk_disp_ovl_remove, 694 .driver = { 695 .name = "mediatek-disp-ovl", 696 .of_match_table = mtk_disp_ovl_driver_dt_match, 697 }, 698 }; 699