1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <drm/drmP.h> 15 #include <linux/clk.h> 16 #include <linux/component.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 21 #include "mtk_drm_crtc.h" 22 #include "mtk_drm_ddp_comp.h" 23 24 #define DISP_REG_OVL_INTEN 0x0004 25 #define OVL_FME_CPL_INT BIT(1) 26 #define DISP_REG_OVL_INTSTA 0x0008 27 #define DISP_REG_OVL_EN 0x000c 28 #define DISP_REG_OVL_RST 0x0014 29 #define DISP_REG_OVL_ROI_SIZE 0x0020 30 #define DISP_REG_OVL_ROI_BGCLR 0x0028 31 #define DISP_REG_OVL_SRC_CON 0x002c 32 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 33 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 34 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 35 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 36 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 37 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 38 #define DISP_REG_OVL_ADDR_MT2701 0x0040 39 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 41 42 #define OVL_RDMA_MEM_GMC 0x40402020 43 44 #define OVL_CON_BYTE_SWAP BIT(24) 45 #define OVL_CON_CLRFMT_RGB (1 << 12) 46 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) 47 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) 48 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 49 0 : OVL_CON_CLRFMT_RGB) 50 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 51 OVL_CON_CLRFMT_RGB : 0) 52 #define OVL_CON_AEN BIT(8) 53 #define OVL_CON_ALPHA 0xff 54 55 struct mtk_disp_ovl_data { 56 unsigned int addr; 57 bool fmt_rgb565_is_0; 58 }; 59 60 /** 61 * struct mtk_disp_ovl - DISP_OVL driver structure 62 * @ddp_comp - structure containing type enum and hardware resources 63 * @crtc - associated crtc to report vblank events to 64 */ 65 struct mtk_disp_ovl { 66 struct mtk_ddp_comp ddp_comp; 67 struct drm_crtc *crtc; 68 const struct mtk_disp_ovl_data *data; 69 }; 70 71 static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp) 72 { 73 return container_of(comp, struct mtk_disp_ovl, ddp_comp); 74 } 75 76 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 77 { 78 struct mtk_disp_ovl *priv = dev_id; 79 struct mtk_ddp_comp *ovl = &priv->ddp_comp; 80 81 /* Clear frame completion interrupt */ 82 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 83 84 if (!priv->crtc) 85 return IRQ_NONE; 86 87 mtk_crtc_ddp_irq(priv->crtc, ovl); 88 89 return IRQ_HANDLED; 90 } 91 92 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, 93 struct drm_crtc *crtc) 94 { 95 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 96 97 ovl->crtc = crtc; 98 writel(0x0, comp->regs + DISP_REG_OVL_INTSTA); 99 writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); 100 } 101 102 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) 103 { 104 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 105 106 ovl->crtc = NULL; 107 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); 108 } 109 110 static void mtk_ovl_start(struct mtk_ddp_comp *comp) 111 { 112 writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); 113 } 114 115 static void mtk_ovl_stop(struct mtk_ddp_comp *comp) 116 { 117 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); 118 } 119 120 static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, 121 unsigned int h, unsigned int vrefresh, 122 unsigned int bpc) 123 { 124 if (w != 0 && h != 0) 125 writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE); 126 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR); 127 128 writel(0x1, comp->regs + DISP_REG_OVL_RST); 129 writel(0x0, comp->regs + DISP_REG_OVL_RST); 130 } 131 132 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) 133 { 134 unsigned int reg; 135 136 writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 137 writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); 138 139 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 140 reg = reg | BIT(idx); 141 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 142 } 143 144 static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) 145 { 146 unsigned int reg; 147 148 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 149 reg = reg & ~BIT(idx); 150 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 151 152 writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 153 } 154 155 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 156 { 157 switch (fmt) { 158 default: 159 case DRM_FORMAT_RGB565: 160 return OVL_CON_CLRFMT_RGB565(ovl); 161 case DRM_FORMAT_BGR565: 162 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; 163 case DRM_FORMAT_RGB888: 164 return OVL_CON_CLRFMT_RGB888(ovl); 165 case DRM_FORMAT_BGR888: 166 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; 167 case DRM_FORMAT_RGBX8888: 168 case DRM_FORMAT_RGBA8888: 169 return OVL_CON_CLRFMT_ARGB8888; 170 case DRM_FORMAT_BGRX8888: 171 case DRM_FORMAT_BGRA8888: 172 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; 173 case DRM_FORMAT_XRGB8888: 174 case DRM_FORMAT_ARGB8888: 175 return OVL_CON_CLRFMT_RGBA8888; 176 case DRM_FORMAT_XBGR8888: 177 case DRM_FORMAT_ABGR8888: 178 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 179 } 180 } 181 182 static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 183 struct mtk_plane_state *state) 184 { 185 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 186 struct mtk_plane_pending_state *pending = &state->pending; 187 unsigned int addr = pending->addr; 188 unsigned int pitch = pending->pitch & 0xffff; 189 unsigned int fmt = pending->format; 190 unsigned int offset = (pending->y << 16) | pending->x; 191 unsigned int src_size = (pending->height << 16) | pending->width; 192 unsigned int con; 193 194 if (!pending->enable) 195 mtk_ovl_layer_off(comp, idx); 196 197 con = ovl_fmt_convert(ovl, fmt); 198 if (idx != 0) 199 con |= OVL_CON_AEN | OVL_CON_ALPHA; 200 201 writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); 202 writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); 203 writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); 204 writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx)); 205 writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx)); 206 207 if (pending->enable) 208 mtk_ovl_layer_on(comp, idx); 209 } 210 211 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { 212 .config = mtk_ovl_config, 213 .start = mtk_ovl_start, 214 .stop = mtk_ovl_stop, 215 .enable_vblank = mtk_ovl_enable_vblank, 216 .disable_vblank = mtk_ovl_disable_vblank, 217 .layer_on = mtk_ovl_layer_on, 218 .layer_off = mtk_ovl_layer_off, 219 .layer_config = mtk_ovl_layer_config, 220 }; 221 222 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 223 void *data) 224 { 225 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 226 struct drm_device *drm_dev = data; 227 int ret; 228 229 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 230 if (ret < 0) { 231 dev_err(dev, "Failed to register component %s: %d\n", 232 dev->of_node->full_name, ret); 233 return ret; 234 } 235 236 return 0; 237 } 238 239 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 240 void *data) 241 { 242 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 243 struct drm_device *drm_dev = data; 244 245 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 246 } 247 248 static const struct component_ops mtk_disp_ovl_component_ops = { 249 .bind = mtk_disp_ovl_bind, 250 .unbind = mtk_disp_ovl_unbind, 251 }; 252 253 static int mtk_disp_ovl_probe(struct platform_device *pdev) 254 { 255 struct device *dev = &pdev->dev; 256 struct mtk_disp_ovl *priv; 257 int comp_id; 258 int irq; 259 int ret; 260 261 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 262 if (!priv) 263 return -ENOMEM; 264 265 irq = platform_get_irq(pdev, 0); 266 if (irq < 0) 267 return irq; 268 269 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL); 270 if (comp_id < 0) { 271 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 272 return comp_id; 273 } 274 275 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 276 &mtk_disp_ovl_funcs); 277 if (ret) { 278 dev_err(dev, "Failed to initialize component: %d\n", ret); 279 return ret; 280 } 281 282 priv->data = of_device_get_match_data(dev); 283 284 platform_set_drvdata(pdev, priv); 285 286 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 287 IRQF_TRIGGER_NONE, dev_name(dev), priv); 288 if (ret < 0) { 289 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 290 return ret; 291 } 292 293 ret = component_add(dev, &mtk_disp_ovl_component_ops); 294 if (ret) 295 dev_err(dev, "Failed to add component: %d\n", ret); 296 297 return ret; 298 } 299 300 static int mtk_disp_ovl_remove(struct platform_device *pdev) 301 { 302 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); 303 304 return 0; 305 } 306 307 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { 308 .addr = DISP_REG_OVL_ADDR_MT2701, 309 .fmt_rgb565_is_0 = false, 310 }; 311 312 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 313 .addr = DISP_REG_OVL_ADDR_MT8173, 314 .fmt_rgb565_is_0 = true, 315 }; 316 317 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 318 { .compatible = "mediatek,mt2701-disp-ovl", 319 .data = &mt2701_ovl_driver_data}, 320 { .compatible = "mediatek,mt8173-disp-ovl", 321 .data = &mt8173_ovl_driver_data}, 322 {}, 323 }; 324 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 325 326 struct platform_driver mtk_disp_ovl_driver = { 327 .probe = mtk_disp_ovl_probe, 328 .remove = mtk_disp_ovl_remove, 329 .driver = { 330 .name = "mediatek-disp-ovl", 331 .owner = THIS_MODULE, 332 .of_match_table = mtk_disp_ovl_driver_dt_match, 333 }, 334 }; 335