1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/of_device.h> 9 #include <linux/of_irq.h> 10 #include <linux/platform_device.h> 11 #include <linux/reset.h> 12 #include <linux/soc/mediatek/mtk-cmdq.h> 13 14 #include "mtk_drm_ddp_comp.h" 15 #include "mtk_drm_drv.h" 16 #include "mtk_disp_drv.h" 17 18 #define DISP_REG_MERGE_CTRL 0x000 19 #define MERGE_EN 1 20 #define DISP_REG_MERGE_CFG_0 0x010 21 #define DISP_REG_MERGE_CFG_1 0x014 22 #define DISP_REG_MERGE_CFG_4 0x020 23 #define DISP_REG_MERGE_CFG_10 0x038 24 /* no swap */ 25 #define SWAP_MODE 0 26 #define FLD_SWAP_MODE GENMASK(4, 0) 27 #define DISP_REG_MERGE_CFG_12 0x040 28 #define CFG_10_10_1PI_2PO_BUF_MODE 6 29 #define CFG_10_10_2PI_2PO_BUF_MODE 8 30 #define CFG_11_10_1PI_2PO_MERGE 18 31 #define FLD_CFG_MERGE_MODE GENMASK(4, 0) 32 #define DISP_REG_MERGE_CFG_24 0x070 33 #define DISP_REG_MERGE_CFG_25 0x074 34 #define DISP_REG_MERGE_CFG_26 0x078 35 #define DISP_REG_MERGE_CFG_27 0x07c 36 #define DISP_REG_MERGE_CFG_36 0x0a0 37 #define ULTRA_EN BIT(0) 38 #define PREULTRA_EN BIT(4) 39 #define DISP_REG_MERGE_CFG_37 0x0a4 40 /* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */ 41 #define BUFFER_MODE 3 42 #define FLD_BUFFER_MODE GENMASK(1, 0) 43 /* 44 * For the ultra and preultra settings, 6us ~ 9us is experience value 45 * and the maximum frequency of mmsys clock is 594MHz. 46 */ 47 #define DISP_REG_MERGE_CFG_40 0x0b0 48 /* 6 us, 594M pixel/sec */ 49 #define ULTRA_TH_LOW (6 * 594) 50 /* 8 us, 594M pixel/sec */ 51 #define ULTRA_TH_HIGH (8 * 594) 52 #define FLD_ULTRA_TH_LOW GENMASK(15, 0) 53 #define FLD_ULTRA_TH_HIGH GENMASK(31, 16) 54 #define DISP_REG_MERGE_CFG_41 0x0b4 55 /* 8 us, 594M pixel/sec */ 56 #define PREULTRA_TH_LOW (8 * 594) 57 /* 9 us, 594M pixel/sec */ 58 #define PREULTRA_TH_HIGH (9 * 594) 59 #define FLD_PREULTRA_TH_LOW GENMASK(15, 0) 60 #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16) 61 62 #define DISP_REG_MERGE_MUTE_0 0xf00 63 64 struct mtk_disp_merge { 65 void __iomem *regs; 66 struct clk *clk; 67 struct clk *async_clk; 68 struct cmdq_client_reg cmdq_reg; 69 bool fifo_en; 70 bool mute_support; 71 struct reset_control *reset_ctl; 72 }; 73 74 void mtk_merge_start(struct device *dev) 75 { 76 mtk_merge_start_cmdq(dev, NULL); 77 } 78 79 void mtk_merge_stop(struct device *dev) 80 { 81 mtk_merge_stop_cmdq(dev, NULL); 82 } 83 84 void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) 85 { 86 struct mtk_disp_merge *priv = dev_get_drvdata(dev); 87 88 if (priv->mute_support) 89 mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, 90 DISP_REG_MERGE_MUTE_0); 91 92 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, 93 DISP_REG_MERGE_CTRL); 94 } 95 96 void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) 97 { 98 struct mtk_disp_merge *priv = dev_get_drvdata(dev); 99 100 if (priv->mute_support) 101 mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs, 102 DISP_REG_MERGE_MUTE_0); 103 104 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, 105 DISP_REG_MERGE_CTRL); 106 107 if (priv->async_clk) 108 reset_control_reset(priv->reset_ctl); 109 } 110 111 static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, 112 struct cmdq_pkt *cmdq_pkt) 113 { 114 mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN, 115 &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36); 116 117 mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE, 118 &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37, 119 FLD_BUFFER_MODE); 120 121 mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16, 122 &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40, 123 FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH); 124 125 mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16, 126 &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41, 127 FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH); 128 } 129 130 void mtk_merge_config(struct device *dev, unsigned int w, 131 unsigned int h, unsigned int vrefresh, 132 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 133 { 134 mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt); 135 } 136 137 void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w, 138 unsigned int h, unsigned int vrefresh, unsigned int bpc, 139 struct cmdq_pkt *cmdq_pkt) 140 { 141 struct mtk_disp_merge *priv = dev_get_drvdata(dev); 142 unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE; 143 144 if (!h || !l_w) { 145 dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h); 146 return; 147 } 148 149 if (priv->fifo_en) { 150 mtk_merge_fifo_setting(priv, cmdq_pkt); 151 mode = CFG_10_10_2PI_2PO_BUF_MODE; 152 } 153 154 if (r_w) 155 mode = CFG_11_10_1PI_2PO_MERGE; 156 157 mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, 158 DISP_REG_MERGE_CFG_0); 159 mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, 160 DISP_REG_MERGE_CFG_1); 161 mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs, 162 DISP_REG_MERGE_CFG_4); 163 /* 164 * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h 165 * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h. 166 * If r_w > 0, the merge is in merge mode (input0 and input1 merge together), 167 * the input0 goes to SRAM0, and input1 goes to SRAM1. 168 * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and 169 * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size. 170 */ 171 mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, 172 DISP_REG_MERGE_CFG_24); 173 if (r_w) 174 mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, 175 DISP_REG_MERGE_CFG_25); 176 else 177 mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, 178 DISP_REG_MERGE_CFG_25); 179 180 /* 181 * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge. 182 * Only take effect when the merge is setting to merge mode. 183 */ 184 mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs, 185 DISP_REG_MERGE_CFG_26); 186 mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs, 187 DISP_REG_MERGE_CFG_27); 188 189 mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs, 190 DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE); 191 mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs, 192 DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE); 193 } 194 195 int mtk_merge_clk_enable(struct device *dev) 196 { 197 int ret = 0; 198 struct mtk_disp_merge *priv = dev_get_drvdata(dev); 199 200 ret = clk_prepare_enable(priv->clk); 201 if (ret) { 202 dev_err(dev, "merge clk prepare enable failed\n"); 203 return ret; 204 } 205 206 ret = clk_prepare_enable(priv->async_clk); 207 if (ret) { 208 /* should clean up the state of priv->clk */ 209 clk_disable_unprepare(priv->clk); 210 211 dev_err(dev, "async clk prepare enable failed\n"); 212 return ret; 213 } 214 215 return ret; 216 } 217 218 void mtk_merge_clk_disable(struct device *dev) 219 { 220 struct mtk_disp_merge *priv = dev_get_drvdata(dev); 221 222 clk_disable_unprepare(priv->async_clk); 223 clk_disable_unprepare(priv->clk); 224 } 225 226 static int mtk_disp_merge_bind(struct device *dev, struct device *master, 227 void *data) 228 { 229 return 0; 230 } 231 232 static void mtk_disp_merge_unbind(struct device *dev, struct device *master, 233 void *data) 234 { 235 } 236 237 static const struct component_ops mtk_disp_merge_component_ops = { 238 .bind = mtk_disp_merge_bind, 239 .unbind = mtk_disp_merge_unbind, 240 }; 241 242 static int mtk_disp_merge_probe(struct platform_device *pdev) 243 { 244 struct device *dev = &pdev->dev; 245 struct resource *res; 246 struct mtk_disp_merge *priv; 247 int ret; 248 249 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 250 if (!priv) 251 return -ENOMEM; 252 253 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 254 priv->regs = devm_ioremap_resource(dev, res); 255 if (IS_ERR(priv->regs)) { 256 dev_err(dev, "failed to ioremap merge\n"); 257 return PTR_ERR(priv->regs); 258 } 259 260 priv->clk = devm_clk_get(dev, NULL); 261 if (IS_ERR(priv->clk)) { 262 dev_err(dev, "failed to get merge clk\n"); 263 return PTR_ERR(priv->clk); 264 } 265 266 priv->async_clk = devm_clk_get_optional(dev, "merge_async"); 267 if (IS_ERR(priv->async_clk)) { 268 dev_err(dev, "failed to get merge async clock\n"); 269 return PTR_ERR(priv->async_clk); 270 } 271 272 if (priv->async_clk) { 273 priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL); 274 if (IS_ERR(priv->reset_ctl)) 275 return PTR_ERR(priv->reset_ctl); 276 } 277 278 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 279 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); 280 if (ret) 281 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 282 #endif 283 284 priv->fifo_en = of_property_read_bool(dev->of_node, 285 "mediatek,merge-fifo-en"); 286 287 priv->mute_support = of_property_read_bool(dev->of_node, 288 "mediatek,merge-mute"); 289 platform_set_drvdata(pdev, priv); 290 291 ret = component_add(dev, &mtk_disp_merge_component_ops); 292 if (ret != 0) 293 dev_err(dev, "Failed to add component: %d\n", ret); 294 295 return ret; 296 } 297 298 static int mtk_disp_merge_remove(struct platform_device *pdev) 299 { 300 component_del(&pdev->dev, &mtk_disp_merge_component_ops); 301 302 return 0; 303 } 304 305 static const struct of_device_id mtk_disp_merge_driver_dt_match[] = { 306 { .compatible = "mediatek,mt8195-disp-merge", }, 307 {}, 308 }; 309 310 MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match); 311 312 struct platform_driver mtk_disp_merge_driver = { 313 .probe = mtk_disp_merge_probe, 314 .remove = mtk_disp_merge_remove, 315 .driver = { 316 .name = "mediatek-disp-merge", 317 .owner = THIS_MODULE, 318 .of_match_table = mtk_disp_merge_driver_dt_match, 319 }, 320 }; 321