1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/clk.h> 3 #include <linux/component.h> 4 #include <linux/delay.h> 5 #include <linux/io.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/regulator/consumer.h> 12 #include <video/mipi_display.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_bridge.h> 16 #include <drm/drm_device.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_encoder.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_modeset_helper_vtables.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 26 #include "mcde_drm.h" 27 #include "mcde_dsi_regs.h" 28 29 #define DSI_DEFAULT_LP_FREQ_HZ 19200000 30 #define DSI_DEFAULT_HS_FREQ_HZ 420160000 31 32 /* PRCMU DSI reset registers */ 33 #define PRCM_DSI_SW_RESET 0x324 34 #define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) 35 #define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) 36 #define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) 37 38 struct mcde_dsi { 39 struct device *dev; 40 struct mcde *mcde; 41 struct drm_bridge bridge; 42 struct drm_panel *panel; 43 struct mipi_dsi_host dsi_host; 44 struct mipi_dsi_device *mdsi; 45 const struct drm_display_mode *mode; 46 struct clk *hs_clk; 47 struct clk *lp_clk; 48 unsigned long hs_freq; 49 unsigned long lp_freq; 50 bool unused; 51 52 void __iomem *regs; 53 struct regmap *prcmu; 54 }; 55 56 static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge) 57 { 58 return container_of(bridge, struct mcde_dsi, bridge); 59 } 60 61 static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h) 62 { 63 return container_of(h, struct mcde_dsi, dsi_host); 64 } 65 66 bool mcde_dsi_irq(struct mipi_dsi_device *mdsi) 67 { 68 struct mcde_dsi *d; 69 u32 val; 70 bool te_received = false; 71 72 d = host_to_mcde_dsi(mdsi->host); 73 74 dev_dbg(d->dev, "%s called\n", __func__); 75 76 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); 77 if (val) 78 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); 79 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 80 dev_dbg(d->dev, "direct command write completed\n"); 81 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { 82 te_received = true; 83 dev_dbg(d->dev, "direct command TE received\n"); 84 } 85 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) 86 dev_err(d->dev, "direct command ACK ERR received\n"); 87 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) 88 dev_err(d->dev, "direct command read ERR received\n"); 89 /* Mask off the ACK value and clear status */ 90 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); 91 92 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); 93 if (val) 94 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val); 95 if (val & DSI_CMD_MODE_STS_ERR_NO_TE) 96 /* This happens all the time (safe to ignore) */ 97 dev_dbg(d->dev, "CMD mode no TE\n"); 98 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS) 99 /* This happens all the time (safe to ignore) */ 100 dev_dbg(d->dev, "CMD mode TE miss\n"); 101 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN) 102 dev_err(d->dev, "CMD mode SD1 underrun\n"); 103 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN) 104 dev_err(d->dev, "CMD mode SD2 underrun\n"); 105 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD) 106 dev_err(d->dev, "CMD mode unwanted RD\n"); 107 writel(val, d->regs + DSI_CMD_MODE_STS_CLR); 108 109 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG); 110 if (val) 111 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val); 112 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR); 113 114 val = readl(d->regs + DSI_TG_STS_FLAG); 115 if (val) 116 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val); 117 writel(val, d->regs + DSI_TG_STS_CLR); 118 119 val = readl(d->regs + DSI_VID_MODE_STS_FLAG); 120 if (val) 121 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val); 122 if (val & DSI_VID_MODE_STS_VSG_RUNNING) 123 dev_dbg(d->dev, "VID mode VSG running\n"); 124 if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA) 125 dev_err(d->dev, "VID mode missing data\n"); 126 if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC) 127 dev_err(d->dev, "VID mode missing HSYNC\n"); 128 if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC) 129 dev_err(d->dev, "VID mode missing VSYNC\n"); 130 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH) 131 dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n"); 132 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT) 133 dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n"); 134 if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE | 135 DSI_VID_MODE_STS_ERR_LINEWRITE | 136 DSI_VID_MODE_STS_ERR_LONGREAD)) 137 dev_err(d->dev, "VID mode read/write error\n"); 138 if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH) 139 dev_err(d->dev, "VID mode received packets differ from expected size\n"); 140 if (val & DSI_VID_MODE_STS_VSG_RECOVERY) 141 dev_err(d->dev, "VID mode VSG in recovery mode\n"); 142 writel(val, d->regs + DSI_VID_MODE_STS_CLR); 143 144 return te_received; 145 } 146 147 static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d) 148 { 149 d->mcde->mdsi = d->mdsi; 150 151 /* 152 * Select the way the DSI data flow is pushing to the display: 153 * currently we just support video or command mode depending 154 * on the type of display. Video mode defaults to using the 155 * formatter itself for synchronization (stateless video panel). 156 * 157 * FIXME: add flags to struct mipi_dsi_device .flags to indicate 158 * displays that require BTA (bus turn around) so we can handle 159 * such displays as well. Figure out how to properly handle 160 * single frame on-demand updates with DRM for command mode 161 * displays (MCDE_COMMAND_ONESHOT_FLOW). 162 */ 163 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) 164 d->mcde->flow_mode = MCDE_VIDEO_FORMATTER_FLOW; 165 else 166 d->mcde->flow_mode = MCDE_COMMAND_TE_FLOW; 167 } 168 169 static int mcde_dsi_host_attach(struct mipi_dsi_host *host, 170 struct mipi_dsi_device *mdsi) 171 { 172 struct mcde_dsi *d = host_to_mcde_dsi(host); 173 174 if (mdsi->lanes < 1 || mdsi->lanes > 2) { 175 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n"); 176 return -EINVAL; 177 } 178 179 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes); 180 /* MIPI_DSI_FMT_RGB88 etc */ 181 dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format, 182 mipi_dsi_pixel_format_to_bpp(mdsi->format)); 183 dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags); 184 185 d->mdsi = mdsi; 186 if (d->mcde) 187 mcde_dsi_attach_to_mcde(d); 188 189 return 0; 190 } 191 192 static int mcde_dsi_host_detach(struct mipi_dsi_host *host, 193 struct mipi_dsi_device *mdsi) 194 { 195 struct mcde_dsi *d = host_to_mcde_dsi(host); 196 197 d->mdsi = NULL; 198 if (d->mcde) 199 d->mcde->mdsi = NULL; 200 201 return 0; 202 } 203 204 #define MCDE_DSI_HOST_IS_READ(type) \ 205 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 206 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 207 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 208 (type == MIPI_DSI_DCS_READ)) 209 210 static int mcde_dsi_execute_transfer(struct mcde_dsi *d, 211 const struct mipi_dsi_msg *msg) 212 { 213 const u32 loop_delay_us = 10; /* us */ 214 u32 loop_counter; 215 size_t txlen = msg->tx_len; 216 size_t rxlen = msg->rx_len; 217 int i; 218 u32 val; 219 int ret; 220 221 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 222 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 223 /* Send command */ 224 writel(1, d->regs + DSI_DIRECT_CMD_SEND); 225 226 loop_counter = 1000 * 1000 / loop_delay_us; 227 if (MCDE_DSI_HOST_IS_READ(msg->type)) { 228 /* Read command */ 229 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 230 (DSI_DIRECT_CMD_STS_READ_COMPLETED | 231 DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)) 232 && --loop_counter) 233 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 234 if (!loop_counter) { 235 dev_err(d->dev, "DSI read timeout!\n"); 236 /* Set exit code and retry */ 237 return -ETIME; 238 } 239 } else { 240 /* Writing only */ 241 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 242 DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 243 && --loop_counter) 244 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 245 246 if (!loop_counter) { 247 /* Set exit code and retry */ 248 dev_err(d->dev, "DSI write timeout!\n"); 249 return -ETIME; 250 } 251 } 252 253 val = readl(d->regs + DSI_DIRECT_CMD_STS); 254 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { 255 dev_err(d->dev, "read completed with error\n"); 256 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT); 257 return -EIO; 258 } 259 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { 260 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; 261 dev_err(d->dev, "error during transmission: %04x\n", 262 val); 263 return -EIO; 264 } 265 266 if (!MCDE_DSI_HOST_IS_READ(msg->type)) { 267 /* Return number of bytes written */ 268 ret = txlen; 269 } else { 270 /* OK this is a read command, get the response */ 271 u32 rdsz; 272 u32 rddat; 273 u8 *rx = msg->rx_buf; 274 275 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY); 276 rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK; 277 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT); 278 if (rdsz < rxlen) { 279 dev_err(d->dev, "read error, requested %zd got %d\n", 280 rxlen, rdsz); 281 return -EIO; 282 } 283 /* FIXME: read more than 4 bytes */ 284 for (i = 0; i < 4 && i < rxlen; i++) 285 rx[i] = (rddat >> (i * 8)) & 0xff; 286 ret = rdsz; 287 } 288 289 /* Successful transmission */ 290 return ret; 291 } 292 293 static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, 294 const struct mipi_dsi_msg *msg) 295 { 296 struct mcde_dsi *d = host_to_mcde_dsi(host); 297 const u8 *tx = msg->tx_buf; 298 size_t txlen = msg->tx_len; 299 size_t rxlen = msg->rx_len; 300 unsigned int retries = 0; 301 u32 val; 302 int ret; 303 int i; 304 305 if (txlen > 16) { 306 dev_err(d->dev, 307 "dunno how to write more than 16 bytes yet\n"); 308 return -EIO; 309 } 310 if (rxlen > 4) { 311 dev_err(d->dev, 312 "dunno how to read more than 4 bytes yet\n"); 313 return -EIO; 314 } 315 316 dev_dbg(d->dev, 317 "message to channel %d, write %zd bytes read %zd bytes\n", 318 msg->channel, txlen, rxlen); 319 320 /* Command "nature" */ 321 if (MCDE_DSI_HOST_IS_READ(msg->type)) 322 /* MCTL_MAIN_DATA_CTL already set up */ 323 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ; 324 else 325 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE; 326 /* 327 * More than 2 bytes will not fit in a single packet, so it's 328 * time to set the "long not short" bit. One byte is used by 329 * the MIPI DCS command leaving just one byte for the payload 330 * in a short package. 331 */ 332 if (mipi_dsi_packet_format_is_long(msg->type)) 333 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; 334 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 335 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 336 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 337 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 338 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 339 340 /* MIPI DCS command is part of the data */ 341 if (txlen > 0) { 342 val = 0; 343 for (i = 0; i < 4 && i < txlen; i++) 344 val |= tx[i] << (i * 8); 345 } 346 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0); 347 if (txlen > 4) { 348 val = 0; 349 for (i = 0; i < 4 && (i + 4) < txlen; i++) 350 val |= tx[i + 4] << (i * 8); 351 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1); 352 } 353 if (txlen > 8) { 354 val = 0; 355 for (i = 0; i < 4 && (i + 8) < txlen; i++) 356 val |= tx[i + 8] << (i * 8); 357 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2); 358 } 359 if (txlen > 12) { 360 val = 0; 361 for (i = 0; i < 4 && (i + 12) < txlen; i++) 362 val |= tx[i + 12] << (i * 8); 363 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3); 364 } 365 366 while (retries < 3) { 367 ret = mcde_dsi_execute_transfer(d, msg); 368 if (ret >= 0) 369 break; 370 retries++; 371 } 372 if (ret < 0 && retries) 373 dev_err(d->dev, "gave up after %d retries\n", retries); 374 375 /* Clear any errors */ 376 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 377 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 378 379 return ret; 380 } 381 382 static const struct mipi_dsi_host_ops mcde_dsi_host_ops = { 383 .attach = mcde_dsi_host_attach, 384 .detach = mcde_dsi_host_detach, 385 .transfer = mcde_dsi_host_transfer, 386 }; 387 388 /* This sends a direct (short) command to request TE */ 389 void mcde_dsi_te_request(struct mipi_dsi_device *mdsi) 390 { 391 struct mcde_dsi *d; 392 u32 val; 393 394 d = host_to_mcde_dsi(mdsi->host); 395 396 /* Command "nature" TE request */ 397 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ; 398 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 399 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 400 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 401 val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM << 402 DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 403 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 404 405 /* Clear TE reveived and error status bits and enables them */ 406 writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR | 407 DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, 408 d->regs + DSI_DIRECT_CMD_STS_CLR); 409 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL); 410 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN; 411 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN; 412 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL); 413 414 /* Clear and enable no TE or TE missing status */ 415 writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR | 416 DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR, 417 d->regs + DSI_CMD_MODE_STS_CLR); 418 val = readl(d->regs + DSI_CMD_MODE_STS_CTL); 419 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN; 420 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN; 421 writel(val, d->regs + DSI_CMD_MODE_STS_CTL); 422 423 /* Send this TE request command */ 424 writel(1, d->regs + DSI_DIRECT_CMD_SEND); 425 } 426 427 static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, 428 const struct drm_display_mode *mode) 429 { 430 /* cpp, characters per pixel, number of bytes per pixel */ 431 u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8; 432 u64 pclk; 433 u64 bpl; 434 int hfp; 435 int hbp; 436 int hsa; 437 u32 blkline_pck, line_duration; 438 u32 val; 439 440 val = 0; 441 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 442 val |= DSI_VID_MAIN_CTL_BURST_MODE; 443 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 444 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; 445 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; 446 } 447 /* RGB header and pixel mode */ 448 switch (d->mdsi->format) { 449 case MIPI_DSI_FMT_RGB565: 450 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << 451 DSI_VID_MAIN_CTL_HEADER_SHIFT; 452 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; 453 break; 454 case MIPI_DSI_FMT_RGB666_PACKED: 455 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << 456 DSI_VID_MAIN_CTL_HEADER_SHIFT; 457 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; 458 break; 459 case MIPI_DSI_FMT_RGB666: 460 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 461 << DSI_VID_MAIN_CTL_HEADER_SHIFT; 462 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; 463 break; 464 case MIPI_DSI_FMT_RGB888: 465 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << 466 DSI_VID_MAIN_CTL_HEADER_SHIFT; 467 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; 468 break; 469 default: 470 dev_err(d->dev, "unknown pixel mode\n"); 471 return; 472 } 473 474 /* TODO: TVG (test video generator) could be enabled here */ 475 476 /* 477 * During vertical blanking: go to LP mode 478 * Like with the EOL setting, if this is not set, the EOL area will be 479 * filled with NULL or blanking packets in the vblank area. 480 * FIXME: some Samsung phones and display panels such as s6e63m0 use 481 * DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING here instead, 482 * figure out how to properly configure that from the panel. 483 */ 484 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; 485 /* 486 * During EOL: go to LP mode. If this is not set, the EOL area will be 487 * filled with NULL or blanking packets. 488 */ 489 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; 490 /* Recovery mode 1 */ 491 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; 492 /* All other fields zero */ 493 writel(val, d->regs + DSI_VID_MAIN_CTL); 494 495 /* Vertical frame parameters are pretty straight-forward */ 496 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT; 497 /* vertical front porch */ 498 val |= (mode->vsync_start - mode->vdisplay) 499 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT; 500 /* vertical sync active */ 501 val |= (mode->vsync_end - mode->vsync_start) 502 << DSI_VID_VSIZE_VSA_LENGTH_SHIFT; 503 /* vertical back porch */ 504 val |= (mode->vtotal - mode->vsync_end) 505 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT; 506 writel(val, d->regs + DSI_VID_VSIZE); 507 508 /* 509 * Horizontal frame parameters: 510 * horizontal resolution is given in pixels but must be re-calculated 511 * into bytes since this is what the hardware expects, these registers 512 * define the payload size of the packet. 513 * 514 * hfp = horizontal front porch in bytes 515 * hbp = horizontal back porch in bytes 516 * hsa = horizontal sync active in bytes 517 * 518 * 6 + 2 is HFP header + checksum 519 */ 520 hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2; 521 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 522 /* 523 * Use sync pulse for sync: explicit HSA time 524 * 6 is HBP header + checksum 525 * 4 is RGB header + checksum 526 */ 527 hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6; 528 /* 529 * 6 is HBP header + checksum 530 * 4 is HSW packet bytes 531 * 4 is RGB header + checksum 532 */ 533 hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6; 534 } else { 535 /* 536 * Use event for sync: HBP includes both back porch and sync 537 * 6 is HBP header + checksum 538 * 4 is HSW packet bytes 539 * 4 is RGB header + checksum 540 */ 541 hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6; 542 /* HSA is not present in this mode and set to 0 */ 543 hsa = 0; 544 } 545 if (hfp < 0) { 546 dev_info(d->dev, "hfp negative, set to 0\n"); 547 hfp = 0; 548 } 549 if (hbp < 0) { 550 dev_info(d->dev, "hbp negative, set to 0\n"); 551 hbp = 0; 552 } 553 if (hsa < 0) { 554 dev_info(d->dev, "hsa negative, set to 0\n"); 555 hsa = 0; 556 } 557 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n", 558 hfp, hbp, hsa); 559 560 /* Frame parameters: horizontal sync active */ 561 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; 562 /* horizontal back porch */ 563 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; 564 /* horizontal front porch */ 565 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; 566 writel(val, d->regs + DSI_VID_HSIZE1); 567 568 /* RGB data length (visible bytes on one scanline) */ 569 val = mode->hdisplay * cpp; 570 writel(val, d->regs + DSI_VID_HSIZE2); 571 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val); 572 573 /* 574 * Calculate the time between two pixels in picoseconds using 575 * the supplied refresh rate and total resolution including 576 * porches and sync. 577 */ 578 /* (ps/s) / (pixels/s) = ps/pixels */ 579 pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000)); 580 dev_dbg(d->dev, "picoseconds between two pixels: %llu\n", 581 pclk); 582 583 /* 584 * How many bytes per line will this update frequency yield? 585 * 586 * Calculate the number of picoseconds for one scanline (1), then 587 * divide by 1000000000000 (2) to get in pixels per second we 588 * want to output. 589 * 590 * Multiply with number of bytes per second at this video display 591 * frequency (3) to get number of bytes transferred during this 592 * time. Notice that we use the frequency the display wants, 593 * not what we actually get from the DSI PLL, which is hs_freq. 594 * 595 * These arithmetics are done in a different order to avoid 596 * overflow. 597 */ 598 bpl = pclk * mode->htotal; /* (1) picoseconds per line */ 599 dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl); 600 /* Multiply with bytes per second (3) */ 601 bpl *= (d->mdsi->hs_rate / 8); 602 /* Pixels per second (2) */ 603 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */ 604 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */ 605 /* parallel transactions in all lanes */ 606 bpl *= d->mdsi->lanes; 607 dev_dbg(d->dev, 608 "calculated bytes per line: %llu @ %d Hz with HS %lu Hz\n", 609 bpl, drm_mode_vrefresh(mode), d->mdsi->hs_rate); 610 611 /* 612 * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes 613 * 4 is short packet for vsync/hsync 614 */ 615 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 616 /* Set the event packet size to 0 (not used) */ 617 writel(0, d->regs + DSI_VID_BLKSIZE1); 618 /* 619 * FIXME: isn't the hsync width in pixels? The porch and 620 * sync area size is in pixels here, but this -6 621 * seems to be for bytes. It looks like this in the vendor 622 * code though. Is it completely untested? 623 */ 624 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6; 625 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; 626 writel(val, d->regs + DSI_VID_BLKSIZE2); 627 } else { 628 /* Set the sync pulse packet size to 0 (not used) */ 629 writel(0, d->regs + DSI_VID_BLKSIZE2); 630 /* Specifying payload size in bytes (-4-6 from manual) */ 631 blkline_pck = bpl - 4 - 6; 632 if (blkline_pck > 0x1FFF) 633 dev_err(d->dev, "blkline_pck too big %d bytes\n", 634 blkline_pck); 635 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; 636 val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK; 637 writel(val, d->regs + DSI_VID_BLKSIZE1); 638 } 639 640 /* 641 * The line duration is used to scale back the frequency from 642 * the max frequency supported by the HS clock to the desired 643 * update frequency in vrefresh. 644 */ 645 line_duration = blkline_pck + 6; 646 /* 647 * The datasheet contains this complex condition to decreasing 648 * the line duration by 1 under very specific circumstances. 649 * Here we also imply that LP is used during burst EOL. 650 */ 651 if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01) 652 && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) 653 line_duration--; 654 line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes); 655 dev_dbg(d->dev, "line duration %u bytes\n", line_duration); 656 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; 657 /* 658 * This is the time to perform LP->HS on D-PHY 659 * FIXME: nowhere to get this from: DT property on the DSI? 660 * The manual says this is "system dependent". 661 * values like 48 and 72 seen in the vendor code. 662 */ 663 val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; 664 writel(val, d->regs + DSI_VID_DPHY_TIME); 665 666 /* 667 * See the manual figure 657 page 2203 for understanding the impact 668 * of the different burst mode settings. 669 */ 670 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 671 int blkeol_pck, blkeol_duration; 672 /* 673 * Packet size at EOL for burst mode, this is only used 674 * if DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is NOT set, 675 * but we instead send NULL or blanking packets at EOL. 676 * This is given in number of bytes. 677 * 678 * See the manual page 2198 for the 13 reg_blkeol_pck bits. 679 */ 680 blkeol_pck = bpl - (mode->htotal * cpp) - 6; 681 if (blkeol_pck < 0) { 682 dev_err(d->dev, "video block does not fit on line!\n"); 683 dev_err(d->dev, 684 "calculated bytes per line: %llu @ %d Hz\n", 685 bpl, drm_mode_vrefresh(mode)); 686 dev_err(d->dev, 687 "bytes per line (blkline_pck) %u bytes\n", 688 blkline_pck); 689 dev_err(d->dev, 690 "blkeol_pck becomes %d bytes\n", blkeol_pck); 691 return; 692 } 693 dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck); 694 695 val = readl(d->regs + DSI_VID_BLKSIZE1); 696 val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK; 697 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; 698 writel(val, d->regs + DSI_VID_BLKSIZE1); 699 /* Use the same value for exact burst limit */ 700 val = blkeol_pck << 701 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT; 702 val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK; 703 writel(val, d->regs + DSI_VID_VCA_SETTING2); 704 /* 705 * This BLKEOL duration is claimed to be the duration in clock 706 * cycles of the BLLP end-of-line (EOL) period for each line if 707 * DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is set. 708 * 709 * It is hard to trust the manuals' claim that this is in clock 710 * cycles as we mimic the behaviour of the vendor code, which 711 * appears to write a number of bytes that would have been 712 * transferred on a single lane. 713 * 714 * See the manual figure 657 page 2203 and page 2198 for the 13 715 * reg_blkeol_duration bits. 716 * 717 * FIXME: should this also be set up also for non-burst mode 718 * according to figure 565 page 2202? 719 */ 720 blkeol_duration = DIV_ROUND_CLOSEST(blkeol_pck + 6, 721 d->mdsi->lanes); 722 dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n", 723 blkeol_duration); 724 725 val = readl(d->regs + DSI_VID_PCK_TIME); 726 val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK; 727 val |= blkeol_duration << 728 DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT; 729 writel(val, d->regs + DSI_VID_PCK_TIME); 730 731 /* Max burst limit, this is given in bytes */ 732 val = readl(d->regs + DSI_VID_VCA_SETTING1); 733 val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK; 734 val |= (blkeol_pck - 6) << 735 DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT; 736 writel(val, d->regs + DSI_VID_VCA_SETTING1); 737 } 738 739 /* Maximum line limit */ 740 val = readl(d->regs + DSI_VID_VCA_SETTING2); 741 val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK; 742 val |= (blkline_pck - 6) << 743 DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT; 744 writel(val, d->regs + DSI_VID_VCA_SETTING2); 745 dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6); 746 } 747 748 static void mcde_dsi_start(struct mcde_dsi *d) 749 { 750 unsigned long hs_freq; 751 u32 val; 752 int i; 753 754 /* No integration mode */ 755 writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE); 756 757 /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */ 758 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN | 759 DSI_MCTL_MAIN_DATA_CTL_BTA_EN | 760 DSI_MCTL_MAIN_DATA_CTL_READ_EN | 761 DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN; 762 if (!(d->mdsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 763 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN; 764 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 765 766 /* Set a high command timeout, clear other fields */ 767 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT; 768 writel(val, d->regs + DSI_CMD_MODE_CTL); 769 770 /* 771 * UI_X4 is described as "unit interval times four" 772 * I guess since DSI packets are 4 bytes wide, one unit 773 * is one byte. 774 */ 775 hs_freq = clk_get_rate(d->hs_clk); 776 hs_freq /= 1000000; /* MHz */ 777 val = 4000 / hs_freq; 778 dev_dbg(d->dev, "UI value: %d\n", val); 779 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT; 780 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK; 781 writel(val, d->regs + DSI_MCTL_DPHY_STATIC); 782 783 /* 784 * Enable clocking: 0x0f (something?) between each burst, 785 * enable the second lane if needed, enable continuous clock if 786 * needed, enable switch into ULPM (ultra-low power mode) on 787 * all the lines. 788 */ 789 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT; 790 if (d->mdsi->lanes == 2) 791 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN; 792 if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 793 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS; 794 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN | 795 DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN | 796 DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN; 797 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL); 798 799 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) | 800 (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT); 801 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME); 802 803 writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90, 804 d->regs + DSI_DPHY_LANES_TRIM); 805 806 /* High PHY timeout */ 807 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) | 808 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) | 809 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT); 810 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT); 811 812 val = DSI_MCTL_MAIN_EN_PLL_START | 813 DSI_MCTL_MAIN_EN_CKLANE_EN | 814 DSI_MCTL_MAIN_EN_DAT1_EN | 815 DSI_MCTL_MAIN_EN_IF1_EN; 816 if (d->mdsi->lanes == 2) 817 val |= DSI_MCTL_MAIN_EN_DAT2_EN; 818 writel(val, d->regs + DSI_MCTL_MAIN_EN); 819 820 /* Wait for the PLL to lock and the clock and data lines to come up */ 821 i = 0; 822 val = DSI_MCTL_MAIN_STS_PLL_LOCK | 823 DSI_MCTL_MAIN_STS_CLKLANE_READY | 824 DSI_MCTL_MAIN_STS_DAT1_READY; 825 if (d->mdsi->lanes == 2) 826 val |= DSI_MCTL_MAIN_STS_DAT2_READY; 827 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) { 828 /* Sleep for a millisecond */ 829 usleep_range(1000, 1500); 830 if (i++ == 100) { 831 dev_warn(d->dev, "DSI lanes did not start up\n"); 832 return; 833 } 834 } 835 836 /* TODO needed? */ 837 838 /* Command mode, clear IF1 ID */ 839 val = readl(d->regs + DSI_CMD_MODE_CTL); 840 /* 841 * If we enable low-power mode here, 842 * then display updates become really slow. 843 */ 844 if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM) 845 val |= DSI_CMD_MODE_CTL_IF1_LP_EN; 846 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 847 writel(val, d->regs + DSI_CMD_MODE_CTL); 848 849 /* Wait for DSI PHY to initialize */ 850 usleep_range(100, 200); 851 dev_info(d->dev, "DSI link enabled\n"); 852 } 853 854 /* 855 * Notice that this is called from inside the display controller 856 * and not from the bridge callbacks. 857 */ 858 void mcde_dsi_enable(struct drm_bridge *bridge) 859 { 860 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 861 unsigned long hs_freq, lp_freq; 862 u32 val; 863 int ret; 864 865 /* Copy maximum clock frequencies */ 866 if (d->mdsi->lp_rate) 867 lp_freq = d->mdsi->lp_rate; 868 else 869 lp_freq = DSI_DEFAULT_LP_FREQ_HZ; 870 if (d->mdsi->hs_rate) 871 hs_freq = d->mdsi->hs_rate; 872 else 873 hs_freq = DSI_DEFAULT_HS_FREQ_HZ; 874 875 /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */ 876 d->lp_freq = clk_round_rate(d->lp_clk, lp_freq); 877 ret = clk_set_rate(d->lp_clk, d->lp_freq); 878 if (ret) 879 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n", 880 d->lp_freq); 881 882 d->hs_freq = clk_round_rate(d->hs_clk, hs_freq); 883 ret = clk_set_rate(d->hs_clk, d->hs_freq); 884 if (ret) 885 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n", 886 d->hs_freq); 887 888 /* Start clocks */ 889 ret = clk_prepare_enable(d->lp_clk); 890 if (ret) 891 dev_err(d->dev, "failed to enable LP clock\n"); 892 else 893 dev_info(d->dev, "DSI LP clock rate %lu Hz\n", 894 d->lp_freq); 895 ret = clk_prepare_enable(d->hs_clk); 896 if (ret) 897 dev_err(d->dev, "failed to enable HS clock\n"); 898 else 899 dev_info(d->dev, "DSI HS clock rate %lu Hz\n", 900 d->hs_freq); 901 902 /* Assert RESET through the PRCMU, active low */ 903 /* FIXME: which DSI block? */ 904 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 905 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 906 907 usleep_range(100, 200); 908 909 /* De-assert RESET again */ 910 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 911 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 912 PRCM_DSI_SW_RESET_DSI0_SW_RESETN); 913 914 /* Start up the hardware */ 915 mcde_dsi_start(d); 916 917 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 918 /* Set up the video mode from the DRM mode */ 919 mcde_dsi_setup_video_mode(d, d->mode); 920 921 /* Put IF1 into video mode */ 922 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 923 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; 924 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 925 926 /* Disable command mode on IF1 */ 927 val = readl(d->regs + DSI_CMD_MODE_CTL); 928 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; 929 writel(val, d->regs + DSI_CMD_MODE_CTL); 930 931 /* Enable some error interrupts */ 932 val = readl(d->regs + DSI_VID_MODE_STS_CTL); 933 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; 934 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; 935 writel(val, d->regs + DSI_VID_MODE_STS_CTL); 936 937 /* Enable video mode */ 938 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 939 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; 940 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 941 } else { 942 /* Command mode, clear IF1 ID */ 943 val = readl(d->regs + DSI_CMD_MODE_CTL); 944 /* 945 * If we enable low-power mode here 946 * the display updates become really slow. 947 */ 948 if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM) 949 val |= DSI_CMD_MODE_CTL_IF1_LP_EN; 950 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 951 writel(val, d->regs + DSI_CMD_MODE_CTL); 952 } 953 954 dev_info(d->dev, "enabled MCDE DSI master\n"); 955 } 956 957 static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge, 958 const struct drm_display_mode *mode, 959 const struct drm_display_mode *adj) 960 { 961 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 962 963 if (!d->mdsi) { 964 dev_err(d->dev, "no DSI device attached to encoder!\n"); 965 return; 966 } 967 968 d->mode = mode; 969 970 dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n", 971 mode->hdisplay, mode->vdisplay, mode->clock * 1000, 972 (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD" 973 ); 974 } 975 976 static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d) 977 { 978 u32 val; 979 int i; 980 981 /* 982 * Wait until we get out of command mode 983 * CSM = Command State Machine 984 */ 985 i = 0; 986 val = DSI_CMD_MODE_STS_CSM_RUNNING; 987 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) { 988 /* Sleep for a millisecond */ 989 usleep_range(1000, 2000); 990 if (i++ == 100) { 991 dev_warn(d->dev, 992 "could not get out of command mode\n"); 993 return; 994 } 995 } 996 } 997 998 static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d) 999 { 1000 u32 val; 1001 int i; 1002 1003 /* Wait until we get out og video mode */ 1004 i = 0; 1005 val = DSI_VID_MODE_STS_VSG_RUNNING; 1006 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) { 1007 /* Sleep for a millisecond */ 1008 usleep_range(1000, 2000); 1009 if (i++ == 100) { 1010 dev_warn(d->dev, 1011 "could not get out of video mode\n"); 1012 return; 1013 } 1014 } 1015 } 1016 1017 /* 1018 * Notice that this is called from inside the display controller 1019 * and not from the bridge callbacks. 1020 */ 1021 void mcde_dsi_disable(struct drm_bridge *bridge) 1022 { 1023 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 1024 u32 val; 1025 1026 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 1027 /* Stop video mode */ 1028 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 1029 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN; 1030 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 1031 mcde_dsi_wait_for_video_mode_stop(d); 1032 } else { 1033 /* Stop command mode */ 1034 mcde_dsi_wait_for_command_mode_stop(d); 1035 } 1036 1037 /* 1038 * Stop clocks and terminate any DSI traffic here so the panel can 1039 * send commands to shut down the display using DSI direct write until 1040 * this point. 1041 */ 1042 1043 /* Disable all error interrupts */ 1044 writel(0, d->regs + DSI_VID_MODE_STS_CTL); 1045 clk_disable_unprepare(d->hs_clk); 1046 clk_disable_unprepare(d->lp_clk); 1047 } 1048 1049 static int mcde_dsi_bridge_attach(struct drm_bridge *bridge, 1050 struct drm_encoder *encoder, 1051 enum drm_bridge_attach_flags flags) 1052 { 1053 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 1054 struct drm_device *drm = bridge->dev; 1055 1056 if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { 1057 dev_err(d->dev, "we need atomic updates\n"); 1058 return -ENOTSUPP; 1059 } 1060 1061 /* Attach the DSI bridge to the output (panel etc) bridge */ 1062 return drm_bridge_attach(encoder, d->bridge.next_bridge, bridge, flags); 1063 } 1064 1065 static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = { 1066 .attach = mcde_dsi_bridge_attach, 1067 .mode_set = mcde_dsi_bridge_mode_set, 1068 }; 1069 1070 static int mcde_dsi_bind(struct device *dev, struct device *master, 1071 void *data) 1072 { 1073 struct drm_device *drm = data; 1074 struct mcde *mcde = to_mcde(drm); 1075 struct mcde_dsi *d = dev_get_drvdata(dev); 1076 struct device_node *child; 1077 struct drm_panel *panel = NULL; 1078 struct drm_bridge *bridge __free(drm_bridge_put) = NULL; 1079 1080 if (!of_get_available_child_count(dev->of_node)) { 1081 dev_info(dev, "unused DSI interface\n"); 1082 d->unused = true; 1083 return 0; 1084 } 1085 d->mcde = mcde; 1086 /* If the display attached before binding, set this up */ 1087 if (d->mdsi) 1088 mcde_dsi_attach_to_mcde(d); 1089 1090 /* Obtain the clocks */ 1091 d->hs_clk = devm_clk_get(dev, "hs"); 1092 if (IS_ERR(d->hs_clk)) { 1093 dev_err(dev, "unable to get HS clock\n"); 1094 return PTR_ERR(d->hs_clk); 1095 } 1096 1097 d->lp_clk = devm_clk_get(dev, "lp"); 1098 if (IS_ERR(d->lp_clk)) { 1099 dev_err(dev, "unable to get LP clock\n"); 1100 return PTR_ERR(d->lp_clk); 1101 } 1102 1103 /* Look for a panel as a child to this node */ 1104 for_each_available_child_of_node(dev->of_node, child) { 1105 panel = of_drm_find_panel(child); 1106 if (IS_ERR(panel)) { 1107 dev_err(dev, "failed to find panel try bridge (%ld)\n", 1108 PTR_ERR(panel)); 1109 panel = NULL; 1110 1111 bridge = of_drm_find_and_get_bridge(child); 1112 if (!bridge) { 1113 dev_err(dev, "failed to find bridge\n"); 1114 of_node_put(child); 1115 return -EINVAL; 1116 } 1117 } 1118 1119 if (panel || bridge) { 1120 of_node_put(child); 1121 break; 1122 } 1123 } 1124 if (panel) { 1125 bridge = drm_panel_bridge_add_typed(panel, 1126 DRM_MODE_CONNECTOR_DSI); 1127 if (IS_ERR(bridge)) { 1128 dev_err(dev, "error adding panel bridge\n"); 1129 return PTR_ERR(bridge); 1130 } 1131 drm_bridge_get(bridge); 1132 dev_info(dev, "connected to panel\n"); 1133 d->panel = panel; 1134 } else if (bridge) { 1135 /* TODO: AV8100 HDMI encoder goes here for example */ 1136 dev_info(dev, "connected to non-panel bridge (unsupported)\n"); 1137 return -ENODEV; 1138 } else { 1139 dev_err(dev, "no panel or bridge\n"); 1140 return -ENODEV; 1141 } 1142 1143 d->bridge.next_bridge = drm_bridge_get(bridge); 1144 1145 /* Create a bridge for this DSI channel */ 1146 d->bridge.of_node = dev->of_node; 1147 drm_bridge_add(&d->bridge); 1148 1149 /* TODO: first come first serve, use a list */ 1150 mcde->bridge = &d->bridge; 1151 1152 dev_info(dev, "initialized MCDE DSI bridge\n"); 1153 1154 return 0; 1155 } 1156 1157 static void mcde_dsi_unbind(struct device *dev, struct device *master, 1158 void *data) 1159 { 1160 struct mcde_dsi *d = dev_get_drvdata(dev); 1161 1162 if (d->panel) 1163 drm_panel_bridge_remove(d->bridge.next_bridge); 1164 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 1165 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 1166 } 1167 1168 static const struct component_ops mcde_dsi_component_ops = { 1169 .bind = mcde_dsi_bind, 1170 .unbind = mcde_dsi_unbind, 1171 }; 1172 1173 static int mcde_dsi_probe(struct platform_device *pdev) 1174 { 1175 struct device *dev = &pdev->dev; 1176 struct mcde_dsi *d; 1177 struct mipi_dsi_host *host; 1178 u32 dsi_id; 1179 int ret; 1180 1181 d = devm_drm_bridge_alloc(dev, struct mcde_dsi, bridge, &mcde_dsi_bridge_funcs); 1182 if (IS_ERR(d)) 1183 return PTR_ERR(d); 1184 d->dev = dev; 1185 platform_set_drvdata(pdev, d); 1186 1187 /* Get a handle on the PRCMU so we can do reset */ 1188 d->prcmu = 1189 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu"); 1190 if (IS_ERR(d->prcmu)) { 1191 dev_err(dev, "no PRCMU regmap\n"); 1192 return PTR_ERR(d->prcmu); 1193 } 1194 1195 d->regs = devm_platform_ioremap_resource(pdev, 0); 1196 if (IS_ERR(d->regs)) 1197 return PTR_ERR(d->regs); 1198 1199 dsi_id = readl(d->regs + DSI_ID_REG); 1200 dev_info(dev, "HW revision 0x%08x\n", dsi_id); 1201 1202 host = &d->dsi_host; 1203 host->dev = dev; 1204 host->ops = &mcde_dsi_host_ops; 1205 ret = mipi_dsi_host_register(host); 1206 if (ret < 0) { 1207 dev_err(dev, "failed to register DSI host: %d\n", ret); 1208 return ret; 1209 } 1210 dev_info(dev, "registered DSI host\n"); 1211 1212 platform_set_drvdata(pdev, d); 1213 return component_add(dev, &mcde_dsi_component_ops); 1214 } 1215 1216 static void mcde_dsi_remove(struct platform_device *pdev) 1217 { 1218 struct mcde_dsi *d = platform_get_drvdata(pdev); 1219 1220 component_del(&pdev->dev, &mcde_dsi_component_ops); 1221 mipi_dsi_host_unregister(&d->dsi_host); 1222 } 1223 1224 static const struct of_device_id mcde_dsi_of_match[] = { 1225 { 1226 .compatible = "ste,mcde-dsi", 1227 }, 1228 {}, 1229 }; 1230 1231 struct platform_driver mcde_dsi_driver = { 1232 .driver = { 1233 .name = "mcde-dsi", 1234 .of_match_table = mcde_dsi_of_match, 1235 }, 1236 .probe = mcde_dsi_probe, 1237 .remove = mcde_dsi_remove, 1238 }; 1239