xref: /linux/drivers/gpu/drm/mcde/mcde_drv.c (revision 145ff1ec090dce9beb5a9590b5dc288e7bb2e65d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org>
4  * Parts of this file were based on the MCDE driver by Marcus Lorentzon
5  * (C) ST-Ericsson SA 2013
6  */
7 
8 /**
9  * DOC: ST-Ericsson MCDE Driver
10  *
11  * The MCDE (short for multi-channel display engine) is a graphics
12  * controller found in the Ux500 chipsets, such as NovaThor U8500.
13  * It was initially conceptualized by ST Microelectronics for the
14  * successor of the Nomadik line, STn8500 but productified in the
15  * ST-Ericsson U8500 where is was used for mass-market deployments
16  * in Android phones from Samsung and Sony Ericsson.
17  *
18  * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for
19  * panels with or without frame buffering and can convert most
20  * input formats including most variants of RGB and YUV.
21  *
22  * The hardware has four display pipes, and the layout is a little
23  * bit like this::
24  *
25  *   Memory     -> Overlay -> Channel -> FIFO -> 5 formatters -> DSI/DPI
26  *   External      0..5       0..3       A,B,    3 x DSI         bridge
27  *   source 0..9                         C0,C1   2 x DPI
28  *
29  * FIFOs A and B are for LCD and HDMI while FIFO CO/C1 are for
30  * panels with embedded buffer.
31  * 3 of the formatters are for DSI.
32  * 2 of the formatters are for DPI.
33  *
34  * Behind the formatters are the DSI or DPI ports that route to
35  * the external pins of the chip. As there are 3 DSI ports and one
36  * DPI port, it is possible to configure up to 4 display pipelines
37  * (effectively using channels 0..3) for concurrent use.
38  *
39  * In the current DRM/KMS setup, we use one external source, one overlay,
40  * one FIFO and one formatter which we connect to the simple CMA framebuffer
41  * helpers. We then provide a bridge to the DSI port, and on the DSI port
42  * bridge we connect hang a panel bridge or other bridge. This may be subject
43  * to change as we exploit more of the hardware capabilities.
44  *
45  * TODO:
46  *
47  * - Enabled damaged rectangles using drm_plane_enable_fb_damage_clips()
48  *   so we can selectively just transmit the damaged area to a
49  *   command-only display.
50  * - Enable mixing of more planes, possibly at the cost of moving away
51  *   from using the simple framebuffer pipeline.
52  * - Enable output to bridges such as the AV8100 HDMI encoder from
53  *   the DSI bridge.
54  */
55 
56 #include <linux/clk.h>
57 #include <linux/component.h>
58 #include <linux/dma-buf.h>
59 #include <linux/irq.h>
60 #include <linux/io.h>
61 #include <linux/module.h>
62 #include <linux/of_platform.h>
63 #include <linux/platform_device.h>
64 #include <linux/regulator/consumer.h>
65 #include <linux/slab.h>
66 
67 #include <drm/drm_atomic_helper.h>
68 #include <drm/drm_bridge.h>
69 #include <drm/drm_drv.h>
70 #include <drm/drm_fb_cma_helper.h>
71 #include <drm/drm_fb_helper.h>
72 #include <drm/drm_gem.h>
73 #include <drm/drm_gem_cma_helper.h>
74 #include <drm/drm_gem_framebuffer_helper.h>
75 #include <drm/drm_managed.h>
76 #include <drm/drm_of.h>
77 #include <drm/drm_probe_helper.h>
78 #include <drm/drm_panel.h>
79 #include <drm/drm_vblank.h>
80 
81 #include "mcde_drm.h"
82 
83 #define DRIVER_DESC	"DRM module for MCDE"
84 
85 #define MCDE_CR 0x00000000
86 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
87 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
88 #define MCDE_CR_IFIFOCTRLEN BIT(15)
89 #define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16)
90 #define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17)
91 #define MCDE_CR_AUTOCLKG_EN BIT(30)
92 #define MCDE_CR_MCDEEN BIT(31)
93 
94 #define MCDE_CONF0 0x00000004
95 #define MCDE_CONF0_SYNCMUX0 BIT(0)
96 #define MCDE_CONF0_SYNCMUX1 BIT(1)
97 #define MCDE_CONF0_SYNCMUX2 BIT(2)
98 #define MCDE_CONF0_SYNCMUX3 BIT(3)
99 #define MCDE_CONF0_SYNCMUX4 BIT(4)
100 #define MCDE_CONF0_SYNCMUX5 BIT(5)
101 #define MCDE_CONF0_SYNCMUX6 BIT(6)
102 #define MCDE_CONF0_SYNCMUX7 BIT(7)
103 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
104 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
105 #define MCDE_CONF0_OUTMUX0_SHIFT 16
106 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
107 #define MCDE_CONF0_OUTMUX1_SHIFT 19
108 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
109 #define MCDE_CONF0_OUTMUX2_SHIFT 22
110 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
111 #define MCDE_CONF0_OUTMUX3_SHIFT 25
112 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
113 #define MCDE_CONF0_OUTMUX4_SHIFT 28
114 #define MCDE_CONF0_OUTMUX4_MASK 0x70000000
115 
116 #define MCDE_SSP 0x00000008
117 #define MCDE_AIS 0x00000100
118 #define MCDE_IMSCERR 0x00000110
119 #define MCDE_RISERR 0x00000120
120 #define MCDE_MISERR 0x00000130
121 #define MCDE_SISERR 0x00000140
122 
123 #define MCDE_PID 0x000001FC
124 #define MCDE_PID_METALFIX_VERSION_SHIFT 0
125 #define MCDE_PID_METALFIX_VERSION_MASK 0x000000FF
126 #define MCDE_PID_DEVELOPMENT_VERSION_SHIFT 8
127 #define MCDE_PID_DEVELOPMENT_VERSION_MASK 0x0000FF00
128 #define MCDE_PID_MINOR_VERSION_SHIFT 16
129 #define MCDE_PID_MINOR_VERSION_MASK 0x00FF0000
130 #define MCDE_PID_MAJOR_VERSION_SHIFT 24
131 #define MCDE_PID_MAJOR_VERSION_MASK 0xFF000000
132 
133 static const struct drm_mode_config_funcs mcde_mode_config_funcs = {
134 	.fb_create = drm_gem_fb_create_with_dirty,
135 	.atomic_check = drm_atomic_helper_check,
136 	.atomic_commit = drm_atomic_helper_commit,
137 };
138 
139 static const struct drm_mode_config_helper_funcs mcde_mode_config_helpers = {
140 	/*
141 	 * Using this function is necessary to commit atomic updates
142 	 * that need the CRTC to be enabled before a commit, as is
143 	 * the case with e.g. DSI displays.
144 	 */
145 	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
146 };
147 
148 static irqreturn_t mcde_irq(int irq, void *data)
149 {
150 	struct mcde *mcde = data;
151 	u32 val;
152 
153 	val = readl(mcde->regs + MCDE_MISERR);
154 
155 	mcde_display_irq(mcde);
156 
157 	if (val)
158 		dev_info(mcde->dev, "some error IRQ\n");
159 	writel(val, mcde->regs + MCDE_RISERR);
160 
161 	return IRQ_HANDLED;
162 }
163 
164 static int mcde_modeset_init(struct drm_device *drm)
165 {
166 	struct drm_mode_config *mode_config;
167 	struct mcde *mcde = to_mcde(drm);
168 	int ret;
169 
170 	if (!mcde->bridge) {
171 		dev_err(drm->dev, "no display output bridge yet\n");
172 		return -EPROBE_DEFER;
173 	}
174 
175 	mode_config = &drm->mode_config;
176 	mode_config->funcs = &mcde_mode_config_funcs;
177 	mode_config->helper_private = &mcde_mode_config_helpers;
178 	/* This hardware can do 1080p */
179 	mode_config->min_width = 1;
180 	mode_config->max_width = 1920;
181 	mode_config->min_height = 1;
182 	mode_config->max_height = 1080;
183 
184 	ret = drm_vblank_init(drm, 1);
185 	if (ret) {
186 		dev_err(drm->dev, "failed to init vblank\n");
187 		return ret;
188 	}
189 
190 	ret = mcde_display_init(drm);
191 	if (ret) {
192 		dev_err(drm->dev, "failed to init display\n");
193 		return ret;
194 	}
195 
196 	/*
197 	 * Attach the DSI bridge
198 	 *
199 	 * TODO: when adding support for the DPI bridge or several DSI bridges,
200 	 * we selectively connect the bridge(s) here instead of this simple
201 	 * attachment.
202 	 */
203 	ret = drm_simple_display_pipe_attach_bridge(&mcde->pipe,
204 						    mcde->bridge);
205 	if (ret) {
206 		dev_err(drm->dev, "failed to attach display output bridge\n");
207 		return ret;
208 	}
209 
210 	drm_mode_config_reset(drm);
211 	drm_kms_helper_poll_init(drm);
212 
213 	return 0;
214 }
215 
216 DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
217 
218 static struct drm_driver mcde_drm_driver = {
219 	.driver_features =
220 		DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
221 	.lastclose = drm_fb_helper_lastclose,
222 	.ioctls = NULL,
223 	.fops = &drm_fops,
224 	.name = "mcde",
225 	.desc = DRIVER_DESC,
226 	.date = "20180529",
227 	.major = 1,
228 	.minor = 0,
229 	.patchlevel = 0,
230 	.dumb_create = drm_gem_cma_dumb_create,
231 	.gem_free_object_unlocked = drm_gem_cma_free_object,
232 	.gem_vm_ops = &drm_gem_cma_vm_ops,
233 
234 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
235 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
236 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
237 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
238 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
239 	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
240 	.gem_prime_mmap = drm_gem_cma_prime_mmap,
241 };
242 
243 static int mcde_drm_bind(struct device *dev)
244 {
245 	struct drm_device *drm = dev_get_drvdata(dev);
246 	int ret;
247 
248 	ret = drmm_mode_config_init(drm);
249 	if (ret)
250 		return ret;
251 
252 	ret = component_bind_all(drm->dev, drm);
253 	if (ret) {
254 		dev_err(dev, "can't bind component devices\n");
255 		return ret;
256 	}
257 
258 	ret = mcde_modeset_init(drm);
259 	if (ret)
260 		goto unbind;
261 
262 	ret = drm_dev_register(drm, 0);
263 	if (ret < 0)
264 		goto unbind;
265 
266 	drm_fbdev_generic_setup(drm, 32);
267 
268 	return 0;
269 
270 unbind:
271 	component_unbind_all(drm->dev, drm);
272 	return ret;
273 }
274 
275 static void mcde_drm_unbind(struct device *dev)
276 {
277 	struct drm_device *drm = dev_get_drvdata(dev);
278 
279 	drm_dev_unregister(drm);
280 	drm_atomic_helper_shutdown(drm);
281 	component_unbind_all(drm->dev, drm);
282 }
283 
284 static const struct component_master_ops mcde_drm_comp_ops = {
285 	.bind = mcde_drm_bind,
286 	.unbind = mcde_drm_unbind,
287 };
288 
289 static struct platform_driver *const mcde_component_drivers[] = {
290 	&mcde_dsi_driver,
291 };
292 
293 static int mcde_compare_dev(struct device *dev, void *data)
294 {
295 	return dev == data;
296 }
297 
298 static int mcde_probe(struct platform_device *pdev)
299 {
300 	struct device *dev = &pdev->dev;
301 	struct drm_device *drm;
302 	struct mcde *mcde;
303 	struct component_match *match = NULL;
304 	struct resource *res;
305 	u32 pid;
306 	u32 val;
307 	int irq;
308 	int ret;
309 	int i;
310 
311 	mcde = devm_drm_dev_alloc(dev, &mcde_drm_driver, struct mcde, drm);
312 	if (IS_ERR(mcde))
313 		return PTR_ERR(mcde);
314 	drm = &mcde->drm;
315 	mcde->dev = dev;
316 	platform_set_drvdata(pdev, drm);
317 
318 	/* Enable continuous updates: this is what Linux' framebuffer expects */
319 	mcde->oneshot_mode = false;
320 
321 	/* First obtain and turn on the main power */
322 	mcde->epod = devm_regulator_get(dev, "epod");
323 	if (IS_ERR(mcde->epod)) {
324 		ret = PTR_ERR(mcde->epod);
325 		dev_err(dev, "can't get EPOD regulator\n");
326 		return ret;
327 	}
328 	ret = regulator_enable(mcde->epod);
329 	if (ret) {
330 		dev_err(dev, "can't enable EPOD regulator\n");
331 		return ret;
332 	}
333 	mcde->vana = devm_regulator_get(dev, "vana");
334 	if (IS_ERR(mcde->vana)) {
335 		ret = PTR_ERR(mcde->vana);
336 		dev_err(dev, "can't get VANA regulator\n");
337 		goto regulator_epod_off;
338 	}
339 	ret = regulator_enable(mcde->vana);
340 	if (ret) {
341 		dev_err(dev, "can't enable VANA regulator\n");
342 		goto regulator_epod_off;
343 	}
344 	/*
345 	 * The vendor code uses ESRAM (onchip RAM) and need to activate
346 	 * the v-esram34 regulator, but we don't use that yet
347 	 */
348 
349 	/* Clock the silicon so we can access the registers */
350 	mcde->mcde_clk = devm_clk_get(dev, "mcde");
351 	if (IS_ERR(mcde->mcde_clk)) {
352 		dev_err(dev, "unable to get MCDE main clock\n");
353 		ret = PTR_ERR(mcde->mcde_clk);
354 		goto regulator_off;
355 	}
356 	ret = clk_prepare_enable(mcde->mcde_clk);
357 	if (ret) {
358 		dev_err(dev, "failed to enable MCDE main clock\n");
359 		goto regulator_off;
360 	}
361 	dev_info(dev, "MCDE clk rate %lu Hz\n", clk_get_rate(mcde->mcde_clk));
362 
363 	mcde->lcd_clk = devm_clk_get(dev, "lcd");
364 	if (IS_ERR(mcde->lcd_clk)) {
365 		dev_err(dev, "unable to get LCD clock\n");
366 		ret = PTR_ERR(mcde->lcd_clk);
367 		goto clk_disable;
368 	}
369 	mcde->hdmi_clk = devm_clk_get(dev, "hdmi");
370 	if (IS_ERR(mcde->hdmi_clk)) {
371 		dev_err(dev, "unable to get HDMI clock\n");
372 		ret = PTR_ERR(mcde->hdmi_clk);
373 		goto clk_disable;
374 	}
375 
376 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
377 	mcde->regs = devm_ioremap_resource(dev, res);
378 	if (IS_ERR(mcde->regs)) {
379 		dev_err(dev, "no MCDE regs\n");
380 		ret = -EINVAL;
381 		goto clk_disable;
382 	}
383 
384 	irq = platform_get_irq(pdev, 0);
385 	if (!irq) {
386 		ret = -EINVAL;
387 		goto clk_disable;
388 	}
389 
390 	ret = devm_request_irq(dev, irq, mcde_irq, 0, "mcde", mcde);
391 	if (ret) {
392 		dev_err(dev, "failed to request irq %d\n", ret);
393 		goto clk_disable;
394 	}
395 
396 	/*
397 	 * Check hardware revision, we only support U8500v2 version
398 	 * as this was the only version used for mass market deployment,
399 	 * but surely you can add more versions if you have them and
400 	 * need them.
401 	 */
402 	pid = readl(mcde->regs + MCDE_PID);
403 	dev_info(dev, "found MCDE HW revision %d.%d (dev %d, metal fix %d)\n",
404 		 (pid & MCDE_PID_MAJOR_VERSION_MASK)
405 		 >> MCDE_PID_MAJOR_VERSION_SHIFT,
406 		 (pid & MCDE_PID_MINOR_VERSION_MASK)
407 		 >> MCDE_PID_MINOR_VERSION_SHIFT,
408 		 (pid & MCDE_PID_DEVELOPMENT_VERSION_MASK)
409 		 >> MCDE_PID_DEVELOPMENT_VERSION_SHIFT,
410 		 (pid & MCDE_PID_METALFIX_VERSION_MASK)
411 		 >> MCDE_PID_METALFIX_VERSION_SHIFT);
412 	if (pid != 0x03000800) {
413 		dev_err(dev, "unsupported hardware revision\n");
414 		ret = -ENODEV;
415 		goto clk_disable;
416 	}
417 
418 	/* Set up the main control, watermark level at 7 */
419 	val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT;
420 	/* 24 bits DPI: connect LSB Ch B to D[0:7] */
421 	val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT;
422 	/* TV out: connect LSB Ch B to D[8:15] */
423 	val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT;
424 	/* Don't care about this muxing */
425 	val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT;
426 	/* 24 bits DPI: connect MID Ch B to D[24:31] */
427 	val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT;
428 	/* 5: 24 bits DPI: connect MSB Ch B to D[32:39] */
429 	val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT;
430 	/* Syncmux bits zero: DPI channel A and B on output pins A and B resp */
431 	writel(val, mcde->regs + MCDE_CONF0);
432 
433 	/* Enable automatic clock gating */
434 	val = readl(mcde->regs + MCDE_CR);
435 	val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN;
436 	writel(val, mcde->regs + MCDE_CR);
437 
438 	/* Clear any pending interrupts */
439 	mcde_display_disable_irqs(mcde);
440 	writel(0, mcde->regs + MCDE_IMSCERR);
441 	writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
442 
443 	/* Spawn child devices for the DSI ports */
444 	devm_of_platform_populate(dev);
445 
446 	/* Create something that will match the subdrivers when we bind */
447 	for (i = 0; i < ARRAY_SIZE(mcde_component_drivers); i++) {
448 		struct device_driver *drv = &mcde_component_drivers[i]->driver;
449 		struct device *p = NULL, *d;
450 
451 		while ((d = platform_find_device_by_driver(p, drv))) {
452 			put_device(p);
453 			component_match_add(dev, &match, mcde_compare_dev, d);
454 			p = d;
455 		}
456 		put_device(p);
457 	}
458 	if (!match) {
459 		dev_err(dev, "no matching components\n");
460 		ret = -ENODEV;
461 		goto clk_disable;
462 	}
463 	if (IS_ERR(match)) {
464 		dev_err(dev, "could not create component match\n");
465 		ret = PTR_ERR(match);
466 		goto clk_disable;
467 	}
468 	ret = component_master_add_with_match(&pdev->dev, &mcde_drm_comp_ops,
469 					      match);
470 	if (ret) {
471 		dev_err(dev, "failed to add component master\n");
472 		goto clk_disable;
473 	}
474 	return 0;
475 
476 clk_disable:
477 	clk_disable_unprepare(mcde->mcde_clk);
478 regulator_off:
479 	regulator_disable(mcde->vana);
480 regulator_epod_off:
481 	regulator_disable(mcde->epod);
482 	return ret;
483 
484 }
485 
486 static int mcde_remove(struct platform_device *pdev)
487 {
488 	struct drm_device *drm = platform_get_drvdata(pdev);
489 	struct mcde *mcde = to_mcde(drm);
490 
491 	component_master_del(&pdev->dev, &mcde_drm_comp_ops);
492 	clk_disable_unprepare(mcde->mcde_clk);
493 	regulator_disable(mcde->vana);
494 	regulator_disable(mcde->epod);
495 
496 	return 0;
497 }
498 
499 static const struct of_device_id mcde_of_match[] = {
500 	{
501 		.compatible = "ste,mcde",
502 	},
503 	{},
504 };
505 
506 static struct platform_driver mcde_driver = {
507 	.driver = {
508 		.name           = "mcde",
509 		.of_match_table = of_match_ptr(mcde_of_match),
510 	},
511 	.probe = mcde_probe,
512 	.remove = mcde_remove,
513 };
514 
515 static struct platform_driver *const component_drivers[] = {
516 	&mcde_dsi_driver,
517 };
518 
519 static int __init mcde_drm_register(void)
520 {
521 	int ret;
522 
523 	ret = platform_register_drivers(component_drivers,
524 					ARRAY_SIZE(component_drivers));
525 	if (ret)
526 		return ret;
527 
528 	return platform_driver_register(&mcde_driver);
529 }
530 
531 static void __exit mcde_drm_unregister(void)
532 {
533 	platform_unregister_drivers(component_drivers,
534 				    ARRAY_SIZE(component_drivers));
535 	platform_driver_unregister(&mcde_driver);
536 }
537 
538 module_init(mcde_drm_register);
539 module_exit(mcde_drm_unregister);
540 
541 MODULE_ALIAS("platform:mcde-drm");
542 MODULE_DESCRIPTION(DRIVER_DESC);
543 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
544 MODULE_LICENSE("GPL");
545