15fc537bfSLinus Walleij /* SPDX-License-Identifier: GPL-2.0 */ 25fc537bfSLinus Walleij #ifndef __DRM_MCDE_DISPLAY_REGS 35fc537bfSLinus Walleij #define __DRM_MCDE_DISPLAY_REGS 45fc537bfSLinus Walleij 55fc537bfSLinus Walleij /* PP (pixel processor) interrupts */ 65fc537bfSLinus Walleij #define MCDE_IMSCPP 0x00000104 75fc537bfSLinus Walleij #define MCDE_RISPP 0x00000114 85fc537bfSLinus Walleij #define MCDE_MISPP 0x00000124 95fc537bfSLinus Walleij #define MCDE_SISPP 0x00000134 105fc537bfSLinus Walleij 115fc537bfSLinus Walleij #define MCDE_PP_VCMPA BIT(0) 125fc537bfSLinus Walleij #define MCDE_PP_VCMPB BIT(1) 135fc537bfSLinus Walleij #define MCDE_PP_VSCC0 BIT(2) 145fc537bfSLinus Walleij #define MCDE_PP_VSCC1 BIT(3) 155fc537bfSLinus Walleij #define MCDE_PP_VCMPC0 BIT(4) 165fc537bfSLinus Walleij #define MCDE_PP_VCMPC1 BIT(5) 175fc537bfSLinus Walleij #define MCDE_PP_ROTFD_A BIT(6) 185fc537bfSLinus Walleij #define MCDE_PP_ROTFD_B BIT(7) 195fc537bfSLinus Walleij 205fc537bfSLinus Walleij /* Overlay interrupts */ 215fc537bfSLinus Walleij #define MCDE_IMSCOVL 0x00000108 225fc537bfSLinus Walleij #define MCDE_RISOVL 0x00000118 235fc537bfSLinus Walleij #define MCDE_MISOVL 0x00000128 245fc537bfSLinus Walleij #define MCDE_SISOVL 0x00000138 255fc537bfSLinus Walleij 265fc537bfSLinus Walleij /* Channel interrupts */ 275fc537bfSLinus Walleij #define MCDE_IMSCCHNL 0x0000010C 285fc537bfSLinus Walleij #define MCDE_RISCHNL 0x0000011C 295fc537bfSLinus Walleij #define MCDE_MISCHNL 0x0000012C 305fc537bfSLinus Walleij #define MCDE_SISCHNL 0x0000013C 315fc537bfSLinus Walleij 325fc537bfSLinus Walleij /* X = 0..9 */ 335fc537bfSLinus Walleij #define MCDE_EXTSRCXA0 0x00000200 345fc537bfSLinus Walleij #define MCDE_EXTSRCXA0_GROUPOFFSET 0x20 355fc537bfSLinus Walleij #define MCDE_EXTSRCXA0_BASEADDRESS0_SHIFT 3 365fc537bfSLinus Walleij #define MCDE_EXTSRCXA0_BASEADDRESS0_MASK 0xFFFFFFF8 375fc537bfSLinus Walleij 385fc537bfSLinus Walleij #define MCDE_EXTSRCXA1 0x00000204 395fc537bfSLinus Walleij #define MCDE_EXTSRCXA1_GROUPOFFSET 0x20 405fc537bfSLinus Walleij #define MCDE_EXTSRCXA1_BASEADDRESS1_SHIFT 3 415fc537bfSLinus Walleij #define MCDE_EXTSRCXA1_BASEADDRESS1_MASK 0xFFFFFFF8 425fc537bfSLinus Walleij 435fc537bfSLinus Walleij /* External sources 0..9 */ 445fc537bfSLinus Walleij #define MCDE_EXTSRC0CONF 0x0000020C 455fc537bfSLinus Walleij #define MCDE_EXTSRC1CONF 0x0000022C 465fc537bfSLinus Walleij #define MCDE_EXTSRC2CONF 0x0000024C 475fc537bfSLinus Walleij #define MCDE_EXTSRC3CONF 0x0000026C 485fc537bfSLinus Walleij #define MCDE_EXTSRC4CONF 0x0000028C 495fc537bfSLinus Walleij #define MCDE_EXTSRC5CONF 0x000002AC 505fc537bfSLinus Walleij #define MCDE_EXTSRC6CONF 0x000002CC 515fc537bfSLinus Walleij #define MCDE_EXTSRC7CONF 0x000002EC 525fc537bfSLinus Walleij #define MCDE_EXTSRC8CONF 0x0000030C 535fc537bfSLinus Walleij #define MCDE_EXTSRC9CONF 0x0000032C 545fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_GROUPOFFSET 0x20 555fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BUF_ID_SHIFT 0 565fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BUF_ID_MASK 0x00000003 575fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BUF_NB_SHIFT 2 585fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BUF_NB_MASK 0x0000000C 595fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT 4 605fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_PRI_OVLID_MASK 0x000000F0 615fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_SHIFT 8 625fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_MASK 0x00000F00 635fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_1BPP_PAL 0 645fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_2BPP_PAL 1 655fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_4BPP_PAL 2 665fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_8BPP_PAL 3 675fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_RGB444 4 685fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_ARGB4444 5 695fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_IRGB1555 6 705fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_RGB565 7 715fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_RGB888 8 725fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_XRGB8888 9 735fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_ARGB8888 10 745fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11 755fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BGR BIT(12) 765fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BEBO BIT(13) 775fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_BEPO BIT(14) 785fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_TUNNELING_BUFFER_HEIGHT_SHIFT 16 795fc537bfSLinus Walleij #define MCDE_EXTSRCXCONF_TUNNELING_BUFFER_HEIGHT_MASK 0x0FFF0000 805fc537bfSLinus Walleij 815fc537bfSLinus Walleij /* External sources 0..9 */ 825fc537bfSLinus Walleij #define MCDE_EXTSRC0CR 0x00000210 835fc537bfSLinus Walleij #define MCDE_EXTSRC1CR 0x00000230 845fc537bfSLinus Walleij #define MCDE_EXTSRC2CR 0x00000250 855fc537bfSLinus Walleij #define MCDE_EXTSRC3CR 0x00000270 865fc537bfSLinus Walleij #define MCDE_EXTSRC4CR 0x00000290 875fc537bfSLinus Walleij #define MCDE_EXTSRC5CR 0x000002B0 885fc537bfSLinus Walleij #define MCDE_EXTSRC6CR 0x000002D0 895fc537bfSLinus Walleij #define MCDE_EXTSRC7CR 0x000002F0 905fc537bfSLinus Walleij #define MCDE_EXTSRC8CR 0x00000310 915fc537bfSLinus Walleij #define MCDE_EXTSRC9CR 0x00000330 925fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_SEL_MOD_SHIFT 0 935fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_SEL_MOD_MASK 0x00000003 945fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_SEL_MOD_EXTERNAL_SEL 0 955fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_SEL_MOD_AUTO_TOGGLE 1 965fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL 2 975fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY BIT(2) /* 0 = all */ 985fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_FS_DIV_DISABLE BIT(3) 995fc537bfSLinus Walleij #define MCDE_EXTSRCXCR_FORCE_FS_DIV BIT(4) 1005fc537bfSLinus Walleij 1015fc537bfSLinus Walleij /* Only external source 6 has a second address register */ 1025fc537bfSLinus Walleij #define MCDE_EXTSRC6A2 0x000002C8 1035fc537bfSLinus Walleij 1045fc537bfSLinus Walleij /* 6 overlays */ 1055fc537bfSLinus Walleij #define MCDE_OVL0CR 0x00000400 1065fc537bfSLinus Walleij #define MCDE_OVL1CR 0x00000420 1075fc537bfSLinus Walleij #define MCDE_OVL2CR 0x00000440 1085fc537bfSLinus Walleij #define MCDE_OVL3CR 0x00000460 1095fc537bfSLinus Walleij #define MCDE_OVL4CR 0x00000480 1105fc537bfSLinus Walleij #define MCDE_OVL5CR 0x000004A0 1115fc537bfSLinus Walleij #define MCDE_OVLXCR_OVLEN BIT(0) 1125fc537bfSLinus Walleij #define MCDE_OVLXCR_COLCCTRL_DISABLED 0 1135fc537bfSLinus Walleij #define MCDE_OVLXCR_COLCCTRL_ENABLED_NO_SAT (1 << 1) 1145fc537bfSLinus Walleij #define MCDE_OVLXCR_COLCCTRL_ENABLED_SAT (2 << 1) 1155fc537bfSLinus Walleij #define MCDE_OVLXCR_CKEYGEN BIT(3) 1165fc537bfSLinus Walleij #define MCDE_OVLXCR_ALPHAPMEN BIT(4) 1175fc537bfSLinus Walleij #define MCDE_OVLXCR_OVLF BIT(5) 1185fc537bfSLinus Walleij #define MCDE_OVLXCR_OVLR BIT(6) 1195fc537bfSLinus Walleij #define MCDE_OVLXCR_OVLB BIT(7) 1205fc537bfSLinus Walleij #define MCDE_OVLXCR_FETCH_ROPC_SHIFT 8 1215fc537bfSLinus Walleij #define MCDE_OVLXCR_FETCH_ROPC_MASK 0x0000FF00 1225fc537bfSLinus Walleij #define MCDE_OVLXCR_STBPRIO_SHIFT 16 1235fc537bfSLinus Walleij #define MCDE_OVLXCR_STBPRIO_MASK 0x000F0000 1245fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_SHIFT 20 1255fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_MASK 0x00F00000 1265fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_1W 0 1275fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_2W 1 1285fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_4W 2 1295fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_8W 3 1305fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_16W 4 1315fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_HW_1W 8 1325fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_HW_2W 9 1335fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_HW_4W 10 1345fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_HW_8W 11 1355fc537bfSLinus Walleij #define MCDE_OVLXCR_BURSTSIZE_HW_16W 12 1365fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_SHIFT 24 1375fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_MASK 0x0F000000 1385fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_1_REQ 0 1395fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_2_REQ 1 1405fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_4_REQ 2 1415fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_8_REQ 3 1425fc537bfSLinus Walleij #define MCDE_OVLXCR_MAXOUTSTANDING_16_REQ 4 1435fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_SHIFT 28 1445fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_MASK 0xF0000000 1455fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_1W 0 1465fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_2W 1 1475fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_4W 2 1485fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_8W 3 1495fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_16W 4 1505fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_HW_1W 8 1515fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_HW_2W 9 1525fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_HW_4W 10 1535fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_HW_8W 11 1545fc537bfSLinus Walleij #define MCDE_OVLXCR_ROTBURSTSIZE_HW_16W 12 1555fc537bfSLinus Walleij 1565fc537bfSLinus Walleij #define MCDE_OVL0CONF 0x00000404 1575fc537bfSLinus Walleij #define MCDE_OVL1CONF 0x00000424 1585fc537bfSLinus Walleij #define MCDE_OVL2CONF 0x00000444 1595fc537bfSLinus Walleij #define MCDE_OVL3CONF 0x00000464 1605fc537bfSLinus Walleij #define MCDE_OVL4CONF 0x00000484 1615fc537bfSLinus Walleij #define MCDE_OVL5CONF 0x000004A4 1625fc537bfSLinus Walleij #define MCDE_OVLXCONF_PPL_SHIFT 0 1635fc537bfSLinus Walleij #define MCDE_OVLXCONF_PPL_MASK 0x000007FF 1645fc537bfSLinus Walleij #define MCDE_OVLXCONF_EXTSRC_ID_SHIFT 11 1655fc537bfSLinus Walleij #define MCDE_OVLXCONF_EXTSRC_ID_MASK 0x00007800 1665fc537bfSLinus Walleij #define MCDE_OVLXCONF_LPF_SHIFT 16 1675fc537bfSLinus Walleij #define MCDE_OVLXCONF_LPF_MASK 0x07FF0000 1685fc537bfSLinus Walleij 1695fc537bfSLinus Walleij #define MCDE_OVL0CONF2 0x00000408 1705fc537bfSLinus Walleij #define MCDE_OVL1CONF2 0x00000428 1715fc537bfSLinus Walleij #define MCDE_OVL2CONF2 0x00000448 1725fc537bfSLinus Walleij #define MCDE_OVL3CONF2 0x00000468 1735fc537bfSLinus Walleij #define MCDE_OVL4CONF2 0x00000488 1745fc537bfSLinus Walleij #define MCDE_OVL5CONF2 0x000004A8 1755fc537bfSLinus Walleij #define MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA 0 1765fc537bfSLinus Walleij #define MCDE_OVLXCONF2_BP_CONSTANT_ALPHA BIT(0) 1775fc537bfSLinus Walleij #define MCDE_OVLXCONF2_ALPHAVALUE_SHIFT 1 1785fc537bfSLinus Walleij #define MCDE_OVLXCONF2_ALPHAVALUE_MASK 0x000001FE 1795fc537bfSLinus Walleij #define MCDE_OVLXCONF2_OPQ BIT(9) 1805fc537bfSLinus Walleij #define MCDE_OVLXCONF2_PIXOFF_SHIFT 10 1815fc537bfSLinus Walleij #define MCDE_OVLXCONF2_PIXOFF_MASK 0x0000FC00 1825fc537bfSLinus Walleij #define MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 1835fc537bfSLinus Walleij #define MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 1845fc537bfSLinus Walleij 1855fc537bfSLinus Walleij #define MCDE_OVL0LJINC 0x0000040C 1865fc537bfSLinus Walleij #define MCDE_OVL1LJINC 0x0000042C 1875fc537bfSLinus Walleij #define MCDE_OVL2LJINC 0x0000044C 1885fc537bfSLinus Walleij #define MCDE_OVL3LJINC 0x0000046C 1895fc537bfSLinus Walleij #define MCDE_OVL4LJINC 0x0000048C 1905fc537bfSLinus Walleij #define MCDE_OVL5LJINC 0x000004AC 1915fc537bfSLinus Walleij 1925fc537bfSLinus Walleij #define MCDE_OVL0CROP 0x00000410 1935fc537bfSLinus Walleij #define MCDE_OVL1CROP 0x00000430 1945fc537bfSLinus Walleij #define MCDE_OVL2CROP 0x00000450 1955fc537bfSLinus Walleij #define MCDE_OVL3CROP 0x00000470 1965fc537bfSLinus Walleij #define MCDE_OVL4CROP 0x00000490 1975fc537bfSLinus Walleij #define MCDE_OVL5CROP 0x000004B0 1985fc537bfSLinus Walleij #define MCDE_OVLXCROP_TMRGN_SHIFT 0 1995fc537bfSLinus Walleij #define MCDE_OVLXCROP_TMRGN_MASK 0x003FFFFF 2005fc537bfSLinus Walleij #define MCDE_OVLXCROP_LMRGN_SHIFT 22 2015fc537bfSLinus Walleij #define MCDE_OVLXCROP_LMRGN_MASK 0xFFC00000 2025fc537bfSLinus Walleij 2035fc537bfSLinus Walleij #define MCDE_OVL0COMP 0x00000414 2045fc537bfSLinus Walleij #define MCDE_OVL1COMP 0x00000434 2055fc537bfSLinus Walleij #define MCDE_OVL2COMP 0x00000454 2065fc537bfSLinus Walleij #define MCDE_OVL3COMP 0x00000474 2075fc537bfSLinus Walleij #define MCDE_OVL4COMP 0x00000494 2085fc537bfSLinus Walleij #define MCDE_OVL5COMP 0x000004B4 2095fc537bfSLinus Walleij #define MCDE_OVLXCOMP_XPOS_SHIFT 0 2105fc537bfSLinus Walleij #define MCDE_OVLXCOMP_XPOS_MASK 0x000007FF 2115fc537bfSLinus Walleij #define MCDE_OVLXCOMP_CH_ID_SHIFT 11 2125fc537bfSLinus Walleij #define MCDE_OVLXCOMP_CH_ID_MASK 0x00007800 2135fc537bfSLinus Walleij #define MCDE_OVLXCOMP_YPOS_SHIFT 16 2145fc537bfSLinus Walleij #define MCDE_OVLXCOMP_YPOS_MASK 0x07FF0000 2155fc537bfSLinus Walleij #define MCDE_OVLXCOMP_Z_SHIFT 27 2165fc537bfSLinus Walleij #define MCDE_OVLXCOMP_Z_MASK 0x78000000 2175fc537bfSLinus Walleij 2185fc537bfSLinus Walleij #define MCDE_CRC 0x00000C00 2195fc537bfSLinus Walleij #define MCDE_CRC_C1EN BIT(2) 2205fc537bfSLinus Walleij #define MCDE_CRC_C2EN BIT(3) 2215fc537bfSLinus Walleij #define MCDE_CRC_SYCEN0 BIT(7) 2225fc537bfSLinus Walleij #define MCDE_CRC_SYCEN1 BIT(8) 2235fc537bfSLinus Walleij #define MCDE_CRC_SIZE1 BIT(9) 2245fc537bfSLinus Walleij #define MCDE_CRC_SIZE2 BIT(10) 2255fc537bfSLinus Walleij #define MCDE_CRC_YUVCONVC1EN BIT(15) 2265fc537bfSLinus Walleij #define MCDE_CRC_CS1EN BIT(16) 2275fc537bfSLinus Walleij #define MCDE_CRC_CS2EN BIT(17) 2285fc537bfSLinus Walleij #define MCDE_CRC_CS1POL BIT(19) 2295fc537bfSLinus Walleij #define MCDE_CRC_CS2POL BIT(20) 2305fc537bfSLinus Walleij #define MCDE_CRC_CD1POL BIT(21) 2315fc537bfSLinus Walleij #define MCDE_CRC_CD2POL BIT(22) 2325fc537bfSLinus Walleij #define MCDE_CRC_WR1POL BIT(23) 2335fc537bfSLinus Walleij #define MCDE_CRC_WR2POL BIT(24) 2345fc537bfSLinus Walleij #define MCDE_CRC_RD1POL BIT(25) 2355fc537bfSLinus Walleij #define MCDE_CRC_RD2POL BIT(26) 2365fc537bfSLinus Walleij #define MCDE_CRC_SYNCCTRL_SHIFT 29 2375fc537bfSLinus Walleij #define MCDE_CRC_SYNCCTRL_MASK 0x60000000 2385fc537bfSLinus Walleij #define MCDE_CRC_SYNCCTRL_NO_SYNC 0 2395fc537bfSLinus Walleij #define MCDE_CRC_SYNCCTRL_DBI0 1 2405fc537bfSLinus Walleij #define MCDE_CRC_SYNCCTRL_DBI1 2 2415fc537bfSLinus Walleij #define MCDE_CRC_SYNCCTRL_PING_PONG 3 2425fc537bfSLinus Walleij #define MCDE_CRC_CLAMPC1EN BIT(31) 2435fc537bfSLinus Walleij 2445fc537bfSLinus Walleij #define MCDE_VSCRC0 0x00000C5C 2455fc537bfSLinus Walleij #define MCDE_VSCRC1 0x00000C60 2465fc537bfSLinus Walleij #define MCDE_VSCRC_VSPMIN_MASK 0x00000FFF 2475fc537bfSLinus Walleij #define MCDE_VSCRC_VSPMAX_SHIFT 12 2485fc537bfSLinus Walleij #define MCDE_VSCRC_VSPMAX_MASK 0x00FFF000 2495fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_SHIFT 24 2505fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MASK 0x07000000 2515fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_1 0 2525fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_2 1 2535fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_4 2 2545fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_8 3 2555fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_16 4 2565fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_32 5 2575fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_64 6 2585fc537bfSLinus Walleij #define MCDE_VSCRC_VSPDIV_MCDECLK_DIV_128 7 2595fc537bfSLinus Walleij #define MCDE_VSCRC_VSPOL BIT(27) /* 0 active high, 1 active low */ 2605fc537bfSLinus Walleij #define MCDE_VSCRC_VSSEL BIT(28) /* 0 VSYNC0, 1 VSYNC1 */ 2615fc537bfSLinus Walleij #define MCDE_VSCRC_VSDBL BIT(29) 2625fc537bfSLinus Walleij 2635fc537bfSLinus Walleij /* Channel config 0..3 */ 2645fc537bfSLinus Walleij #define MCDE_CHNL0CONF 0x00000600 2655fc537bfSLinus Walleij #define MCDE_CHNL1CONF 0x00000620 2665fc537bfSLinus Walleij #define MCDE_CHNL2CONF 0x00000640 2675fc537bfSLinus Walleij #define MCDE_CHNL3CONF 0x00000660 2685fc537bfSLinus Walleij #define MCDE_CHNLXCONF_PPL_SHIFT 0 2695fc537bfSLinus Walleij #define MCDE_CHNLXCONF_PPL_MASK 0x000007FF 2705fc537bfSLinus Walleij #define MCDE_CHNLXCONF_LPF_SHIFT 16 2715fc537bfSLinus Walleij #define MCDE_CHNLXCONF_LPF_MASK 0x07FF0000 2725fc537bfSLinus Walleij #define MCDE_MAX_WIDTH 2048 2735fc537bfSLinus Walleij 2745fc537bfSLinus Walleij /* Channel status 0..3 */ 2755fc537bfSLinus Walleij #define MCDE_CHNL0STAT 0x00000604 2765fc537bfSLinus Walleij #define MCDE_CHNL1STAT 0x00000624 2775fc537bfSLinus Walleij #define MCDE_CHNL2STAT 0x00000644 2785fc537bfSLinus Walleij #define MCDE_CHNL3STAT 0x00000664 2795fc537bfSLinus Walleij #define MCDE_CHNLXSTAT_CHNLRD BIT(0) 2805fc537bfSLinus Walleij #define MCDE_CHNLXSTAT_CHNLA BIT(1) 2815fc537bfSLinus Walleij #define MCDE_CHNLXSTAT_CHNLBLBCKGND_EN BIT(16) 2825fc537bfSLinus Walleij #define MCDE_CHNLXSTAT_PPLX2_V422 BIT(17) 2835fc537bfSLinus Walleij #define MCDE_CHNLXSTAT_LPFX2_V422 BIT(18) 2845fc537bfSLinus Walleij 2855fc537bfSLinus Walleij /* Sync settings for channel 0..3 */ 2865fc537bfSLinus Walleij #define MCDE_CHNL0SYNCHMOD 0x00000608 2875fc537bfSLinus Walleij #define MCDE_CHNL1SYNCHMOD 0x00000628 2885fc537bfSLinus Walleij #define MCDE_CHNL2SYNCHMOD 0x00000648 2895fc537bfSLinus Walleij #define MCDE_CHNL3SYNCHMOD 0x00000668 2905fc537bfSLinus Walleij 2915fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT 0 2925fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_MASK 0x00000003 2935fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 0 2945fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_NO_SYNCH 1 2955fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE 2 2965fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 2975fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C 2985fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 2995fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 1 3005fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE1 2 3015fc537bfSLinus Walleij 3025fc537bfSLinus Walleij /* Software sync triggers for channel 0..3 */ 3035fc537bfSLinus Walleij #define MCDE_CHNL0SYNCHSW 0x0000060C 3045fc537bfSLinus Walleij #define MCDE_CHNL1SYNCHSW 0x0000062C 3055fc537bfSLinus Walleij #define MCDE_CHNL2SYNCHSW 0x0000064C 3065fc537bfSLinus Walleij #define MCDE_CHNL3SYNCHSW 0x0000066C 3075fc537bfSLinus Walleij #define MCDE_CHNLXSYNCHSW_SW_TRIG BIT(0) 3085fc537bfSLinus Walleij 3095fc537bfSLinus Walleij #define MCDE_CHNL0BCKGNDCOL 0x00000610 3105fc537bfSLinus Walleij #define MCDE_CHNL1BCKGNDCOL 0x00000630 3115fc537bfSLinus Walleij #define MCDE_CHNL2BCKGNDCOL 0x00000650 3125fc537bfSLinus Walleij #define MCDE_CHNL3BCKGNDCOL 0x00000670 3135fc537bfSLinus Walleij #define MCDE_CHNLXBCKGNDCOL_B_SHIFT 0 3145fc537bfSLinus Walleij #define MCDE_CHNLXBCKGNDCOL_B_MASK 0x000000FF 3155fc537bfSLinus Walleij #define MCDE_CHNLXBCKGNDCOL_G_SHIFT 8 3165fc537bfSLinus Walleij #define MCDE_CHNLXBCKGNDCOL_G_MASK 0x0000FF00 3175fc537bfSLinus Walleij #define MCDE_CHNLXBCKGNDCOL_R_SHIFT 16 3185fc537bfSLinus Walleij #define MCDE_CHNLXBCKGNDCOL_R_MASK 0x00FF0000 3195fc537bfSLinus Walleij 3205fc537bfSLinus Walleij #define MCDE_CHNL0MUXING 0x00000614 3215fc537bfSLinus Walleij #define MCDE_CHNL1MUXING 0x00000634 3225fc537bfSLinus Walleij #define MCDE_CHNL2MUXING 0x00000654 3235fc537bfSLinus Walleij #define MCDE_CHNL3MUXING 0x00000674 3245fc537bfSLinus Walleij #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_A 0 3255fc537bfSLinus Walleij #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_B 1 3265fc537bfSLinus Walleij #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_C0 2 3275fc537bfSLinus Walleij #define MCDE_CHNLXMUXING_FIFO_ID_FIFO_C1 3 3285fc537bfSLinus Walleij 3295fc537bfSLinus Walleij /* Pixel processing control registers for channel A B, */ 3305fc537bfSLinus Walleij #define MCDE_CRA0 0x00000800 3315fc537bfSLinus Walleij #define MCDE_CRB0 0x00000A00 3325fc537bfSLinus Walleij #define MCDE_CRX0_FLOEN BIT(0) 3335fc537bfSLinus Walleij #define MCDE_CRX0_POWEREN BIT(1) 3345fc537bfSLinus Walleij #define MCDE_CRX0_BLENDEN BIT(2) 3355fc537bfSLinus Walleij #define MCDE_CRX0_AFLICKEN BIT(3) 3365fc537bfSLinus Walleij #define MCDE_CRX0_PALEN BIT(4) 3375fc537bfSLinus Walleij #define MCDE_CRX0_DITHEN BIT(5) 3385fc537bfSLinus Walleij #define MCDE_CRX0_GAMEN BIT(6) 3395fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_SHIFT 7 3405fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_MASK 0x00000380 3415fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_OFF 0 3425fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_ALPHA_RGB 1 3435fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_RGB 2 3445fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_FALPHA_FRGB 4 3455fc537bfSLinus Walleij #define MCDE_CRX0_KEYCTRL_FRGB 5 3465fc537bfSLinus Walleij #define MCDE_CRX0_BLENDCTRL BIT(10) 3475fc537bfSLinus Walleij #define MCDE_CRX0_FLICKMODE_SHIFT 11 3485fc537bfSLinus Walleij #define MCDE_CRX0_FLICKMODE_MASK 0x00001800 3495fc537bfSLinus Walleij #define MCDE_CRX0_FLICKMODE_FORCE_FILTER_0 0 3505fc537bfSLinus Walleij #define MCDE_CRX0_FLICKMODE_ADAPTIVE 1 3515fc537bfSLinus Walleij #define MCDE_CRX0_FLICKMODE_TEST_MODE 2 3525fc537bfSLinus Walleij #define MCDE_CRX0_FLOCKFORMAT_RGB BIT(13) /* 0 = YCVCR */ 3535fc537bfSLinus Walleij #define MCDE_CRX0_PALMODE_GAMMA BIT(14) /* 0 = palette */ 3545fc537bfSLinus Walleij #define MCDE_CRX0_OLEDEN BIT(15) 3555fc537bfSLinus Walleij #define MCDE_CRX0_ALPHABLEND_SHIFT 16 3565fc537bfSLinus Walleij #define MCDE_CRX0_ALPHABLEND_MASK 0x00FF0000 3575fc537bfSLinus Walleij #define MCDE_CRX0_ROTEN BIT(24) 3585fc537bfSLinus Walleij 3595fc537bfSLinus Walleij #define MCDE_CRA1 0x00000804 3605fc537bfSLinus Walleij #define MCDE_CRB1 0x00000A04 3615fc537bfSLinus Walleij #define MCDE_CRX1_PCD_SHIFT 0 3625fc537bfSLinus Walleij #define MCDE_CRX1_PCD_MASK 0x000003FF 3635fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_SHIFT 10 3645fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_MASK 0x00001C00 3655fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_CLKPLL72 0 3665fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_CLKPLL27 2 3675fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_TV1CLK 3 3685fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_TV2CLK 4 3695fc537bfSLinus Walleij #define MCDE_CRX1_CLKSEL_MCDECLK 5 3705fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_SHIFT 13 3715fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_MASK 0x0001E000 3725fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_8BPP_C1 0 3735fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_12BPP_C1 1 3745fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_12BPP_C2 2 3755fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_16BPP_C1 3 3765fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_16BPP_C2 4 3775fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_16BPP_C3 5 3785fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_18BPP_C1 6 3795fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_18BPP_C2 7 3805fc537bfSLinus Walleij #define MCDE_CRX1_CDWIN_24BPP 8 3815fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_SHIFT 25 3825fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_MASK 0x1E000000 3835fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_MONO1 0 3845fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_MONO2 1 3855fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_MONO4 2 3865fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_MONO8 3 3875fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_8BPP 4 3885fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_12BPP 5 3895fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_15BPP 6 3905fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_16BPP 7 3915fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_18BPP 8 3925fc537bfSLinus Walleij #define MCDE_CRX1_OUTBPP_24BPP 9 3935fc537bfSLinus Walleij #define MCDE_CRX1_BCD BIT(29) 3945fc537bfSLinus Walleij #define MCDE_CRA1_CLKTYPE_TVXCLKSEL1 BIT(30) /* 0 = TVXCLKSEL1 */ 3955fc537bfSLinus Walleij 3965fc537bfSLinus Walleij #define MCDE_COLKEYA 0x00000808 3975fc537bfSLinus Walleij #define MCDE_COLKEYB 0x00000A08 3985fc537bfSLinus Walleij 3995fc537bfSLinus Walleij #define MCDE_FCOLKEYA 0x0000080C 4005fc537bfSLinus Walleij #define MCDE_FCOLKEYB 0x00000A0C 4015fc537bfSLinus Walleij 4025fc537bfSLinus Walleij #define MCDE_RGBCONV1A 0x00000810 4035fc537bfSLinus Walleij #define MCDE_RGBCONV1B 0x00000A10 4045fc537bfSLinus Walleij 4055fc537bfSLinus Walleij #define MCDE_RGBCONV2A 0x00000814 4065fc537bfSLinus Walleij #define MCDE_RGBCONV2B 0x00000A14 4075fc537bfSLinus Walleij 4085fc537bfSLinus Walleij #define MCDE_RGBCONV3A 0x00000818 4095fc537bfSLinus Walleij #define MCDE_RGBCONV3B 0x00000A18 4105fc537bfSLinus Walleij 4115fc537bfSLinus Walleij #define MCDE_RGBCONV4A 0x0000081C 4125fc537bfSLinus Walleij #define MCDE_RGBCONV4B 0x00000A1C 4135fc537bfSLinus Walleij 4145fc537bfSLinus Walleij #define MCDE_RGBCONV5A 0x00000820 4155fc537bfSLinus Walleij #define MCDE_RGBCONV5B 0x00000A20 4165fc537bfSLinus Walleij 4175fc537bfSLinus Walleij #define MCDE_RGBCONV6A 0x00000824 4185fc537bfSLinus Walleij #define MCDE_RGBCONV6B 0x00000A24 4195fc537bfSLinus Walleij 4205fc537bfSLinus Walleij /* Rotation */ 4215fc537bfSLinus Walleij #define MCDE_ROTACONF 0x0000087C 4225fc537bfSLinus Walleij #define MCDE_ROTBCONF 0x00000A7C 4235fc537bfSLinus Walleij 4245fc537bfSLinus Walleij #define MCDE_SYNCHCONFA 0x00000880 4255fc537bfSLinus Walleij #define MCDE_SYNCHCONFB 0x00000A80 4265fc537bfSLinus Walleij 4275fc537bfSLinus Walleij /* Channel A+B control registers */ 4285fc537bfSLinus Walleij #define MCDE_CTRLA 0x00000884 4295fc537bfSLinus Walleij #define MCDE_CTRLB 0x00000A84 4305fc537bfSLinus Walleij #define MCDE_CTRLX_FIFOWTRMRK_SHIFT 0 4315fc537bfSLinus Walleij #define MCDE_CTRLX_FIFOWTRMRK_MASK 0x000003FF 4325fc537bfSLinus Walleij #define MCDE_CTRLX_FIFOEMPTY BIT(12) 4335fc537bfSLinus Walleij #define MCDE_CTRLX_FIFOFULL BIT(13) 4345fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_SHIFT 16 4355fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_MASK 0x00070000 4365fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DSI0VID 0 4375fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DSI0CMD 1 4385fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DSI1VID 2 4395fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DSI1CMD 3 4405fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DSI2VID 4 4415fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DSI2CMD 5 4425fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DPIA 0 4435fc537bfSLinus Walleij #define MCDE_CTRLX_FORMID_DPIB 1 4445fc537bfSLinus Walleij #define MCDE_CTRLX_FORMTYPE_SHIFT 20 4455fc537bfSLinus Walleij #define MCDE_CTRLX_FORMTYPE_MASK 0x00700000 4465fc537bfSLinus Walleij #define MCDE_CTRLX_FORMTYPE_DPITV 0 4475fc537bfSLinus Walleij #define MCDE_CTRLX_FORMTYPE_DBI 1 4485fc537bfSLinus Walleij #define MCDE_CTRLX_FORMTYPE_DSI 2 4495fc537bfSLinus Walleij 4505fc537bfSLinus Walleij #define MCDE_DSIVID0CONF0 0x00000E00 4515fc537bfSLinus Walleij #define MCDE_DSICMD0CONF0 0x00000E20 4525fc537bfSLinus Walleij #define MCDE_DSIVID1CONF0 0x00000E40 4535fc537bfSLinus Walleij #define MCDE_DSICMD1CONF0 0x00000E60 4545fc537bfSLinus Walleij #define MCDE_DSIVID2CONF0 0x00000E80 4555fc537bfSLinus Walleij #define MCDE_DSICMD2CONF0 0x00000EA0 4565fc537bfSLinus Walleij #define MCDE_DSICONF0_BLANKING_SHIFT 0 4575fc537bfSLinus Walleij #define MCDE_DSICONF0_BLANKING_MASK 0x000000FF 4585fc537bfSLinus Walleij #define MCDE_DSICONF0_VID_MODE_CMD 0 4595fc537bfSLinus Walleij #define MCDE_DSICONF0_VID_MODE_VID BIT(12) 4605fc537bfSLinus Walleij #define MCDE_DSICONF0_CMD8 BIT(13) 4615fc537bfSLinus Walleij #define MCDE_DSICONF0_BIT_SWAP BIT(16) 4625fc537bfSLinus Walleij #define MCDE_DSICONF0_BYTE_SWAP BIT(17) 4635fc537bfSLinus Walleij #define MCDE_DSICONF0_DCSVID_NOTGEN BIT(18) 4645fc537bfSLinus Walleij #define MCDE_DSICONF0_PACKING_SHIFT 20 4655fc537bfSLinus Walleij #define MCDE_DSICONF0_PACKING_MASK 0x00700000 4665fc537bfSLinus Walleij #define MCDE_DSICONF0_PACKING_RGB565 0 4675fc537bfSLinus Walleij #define MCDE_DSICONF0_PACKING_RGB666 1 468*77f512bdSLinus Walleij #define MCDE_DSICONF0_PACKING_RGB888 2 469*77f512bdSLinus Walleij #define MCDE_DSICONF0_PACKING_BGR888 3 4705fc537bfSLinus Walleij #define MCDE_DSICONF0_PACKING_HDTV 4 4715fc537bfSLinus Walleij 4725fc537bfSLinus Walleij #define MCDE_DSIVID0FRAME 0x00000E04 4735fc537bfSLinus Walleij #define MCDE_DSICMD0FRAME 0x00000E24 4745fc537bfSLinus Walleij #define MCDE_DSIVID1FRAME 0x00000E44 4755fc537bfSLinus Walleij #define MCDE_DSICMD1FRAME 0x00000E64 4765fc537bfSLinus Walleij #define MCDE_DSIVID2FRAME 0x00000E84 4775fc537bfSLinus Walleij #define MCDE_DSICMD2FRAME 0x00000EA4 4785fc537bfSLinus Walleij 4795fc537bfSLinus Walleij #define MCDE_DSIVID0PKT 0x00000E08 4805fc537bfSLinus Walleij #define MCDE_DSICMD0PKT 0x00000E28 4815fc537bfSLinus Walleij #define MCDE_DSIVID1PKT 0x00000E48 4825fc537bfSLinus Walleij #define MCDE_DSICMD1PKT 0x00000E68 4835fc537bfSLinus Walleij #define MCDE_DSIVID2PKT 0x00000E88 4845fc537bfSLinus Walleij #define MCDE_DSICMD2PKT 0x00000EA8 4855fc537bfSLinus Walleij 4865fc537bfSLinus Walleij #define MCDE_DSIVID0SYNC 0x00000E0C 4875fc537bfSLinus Walleij #define MCDE_DSICMD0SYNC 0x00000E2C 4885fc537bfSLinus Walleij #define MCDE_DSIVID1SYNC 0x00000E4C 4895fc537bfSLinus Walleij #define MCDE_DSICMD1SYNC 0x00000E6C 4905fc537bfSLinus Walleij #define MCDE_DSIVID2SYNC 0x00000E8C 4915fc537bfSLinus Walleij #define MCDE_DSICMD2SYNC 0x00000EAC 4925fc537bfSLinus Walleij 4935fc537bfSLinus Walleij #define MCDE_DSIVID0CMDW 0x00000E10 4945fc537bfSLinus Walleij #define MCDE_DSICMD0CMDW 0x00000E30 4955fc537bfSLinus Walleij #define MCDE_DSIVID1CMDW 0x00000E50 4965fc537bfSLinus Walleij #define MCDE_DSICMD1CMDW 0x00000E70 4975fc537bfSLinus Walleij #define MCDE_DSIVID2CMDW 0x00000E90 4985fc537bfSLinus Walleij #define MCDE_DSICMD2CMDW 0x00000EB0 4995fc537bfSLinus Walleij #define MCDE_DSIVIDXCMDW_CMDW_CONTINUE_SHIFT 0 5005fc537bfSLinus Walleij #define MCDE_DSIVIDXCMDW_CMDW_CONTINUE_MASK 0x0000FFFF 5015fc537bfSLinus Walleij #define MCDE_DSIVIDXCMDW_CMDW_START_SHIFT 16 5025fc537bfSLinus Walleij #define MCDE_DSIVIDXCMDW_CMDW_START_MASK 0xFFFF0000 5035fc537bfSLinus Walleij 5045fc537bfSLinus Walleij #define MCDE_DSIVID0DELAY0 0x00000E14 5055fc537bfSLinus Walleij #define MCDE_DSICMD0DELAY0 0x00000E34 5065fc537bfSLinus Walleij #define MCDE_DSIVID1DELAY0 0x00000E54 5075fc537bfSLinus Walleij #define MCDE_DSICMD1DELAY0 0x00000E74 5085fc537bfSLinus Walleij #define MCDE_DSIVID2DELAY0 0x00000E94 5095fc537bfSLinus Walleij #define MCDE_DSICMD2DELAY0 0x00000EB4 5105fc537bfSLinus Walleij 5115fc537bfSLinus Walleij #define MCDE_DSIVID0DELAY1 0x00000E18 5125fc537bfSLinus Walleij #define MCDE_DSICMD0DELAY1 0x00000E38 5135fc537bfSLinus Walleij #define MCDE_DSIVID1DELAY1 0x00000E58 5145fc537bfSLinus Walleij #define MCDE_DSICMD1DELAY1 0x00000E78 5155fc537bfSLinus Walleij #define MCDE_DSIVID2DELAY1 0x00000E98 5165fc537bfSLinus Walleij #define MCDE_DSICMD2DELAY1 0x00000EB8 5175fc537bfSLinus Walleij 5185fc537bfSLinus Walleij #endif /* __DRM_MCDE_DISPLAY_REGS */ 519