xref: /linux/drivers/gpu/drm/loongson/lsdc_gfxpll.h (revision a940daa52167e9db8ecce82213813b735a9d9f23)
1*f39db26cSSui Jingfeng /* SPDX-License-Identifier: GPL-2.0+ */
2*f39db26cSSui Jingfeng /*
3*f39db26cSSui Jingfeng  * Copyright (C) 2023 Loongson Technology Corporation Limited
4*f39db26cSSui Jingfeng  */
5*f39db26cSSui Jingfeng 
6*f39db26cSSui Jingfeng #ifndef __LSDC_GFXPLL_H__
7*f39db26cSSui Jingfeng #define __LSDC_GFXPLL_H__
8*f39db26cSSui Jingfeng 
9*f39db26cSSui Jingfeng #include <drm/drm_device.h>
10*f39db26cSSui Jingfeng 
11*f39db26cSSui Jingfeng struct loongson_gfxpll;
12*f39db26cSSui Jingfeng 
13*f39db26cSSui Jingfeng struct loongson_gfxpll_parms {
14*f39db26cSSui Jingfeng 	unsigned int ref_clock;
15*f39db26cSSui Jingfeng 	unsigned int div_ref;
16*f39db26cSSui Jingfeng 	unsigned int loopc;
17*f39db26cSSui Jingfeng 	unsigned int div_out_dc;
18*f39db26cSSui Jingfeng 	unsigned int div_out_gmc;
19*f39db26cSSui Jingfeng 	unsigned int div_out_gpu;
20*f39db26cSSui Jingfeng };
21*f39db26cSSui Jingfeng 
22*f39db26cSSui Jingfeng struct loongson_gfxpll_funcs {
23*f39db26cSSui Jingfeng 	int (*init)(struct loongson_gfxpll * const this);
24*f39db26cSSui Jingfeng 
25*f39db26cSSui Jingfeng 	int (*update)(struct loongson_gfxpll * const this,
26*f39db26cSSui Jingfeng 		      struct loongson_gfxpll_parms const *pin);
27*f39db26cSSui Jingfeng 
28*f39db26cSSui Jingfeng 	void (*get_rates)(struct loongson_gfxpll * const this,
29*f39db26cSSui Jingfeng 			  unsigned int *dc, unsigned int *gmc, unsigned int *gpu);
30*f39db26cSSui Jingfeng 
31*f39db26cSSui Jingfeng 	void (*print)(struct loongson_gfxpll * const this,
32*f39db26cSSui Jingfeng 		      struct drm_printer *printer, bool verbose);
33*f39db26cSSui Jingfeng };
34*f39db26cSSui Jingfeng 
35*f39db26cSSui Jingfeng struct loongson_gfxpll {
36*f39db26cSSui Jingfeng 	struct drm_device *ddev;
37*f39db26cSSui Jingfeng 	void __iomem *mmio;
38*f39db26cSSui Jingfeng 
39*f39db26cSSui Jingfeng 	/* PLL register offset */
40*f39db26cSSui Jingfeng 	u32 reg_base;
41*f39db26cSSui Jingfeng 	/* PLL register size in bytes */
42*f39db26cSSui Jingfeng 	u32 reg_size;
43*f39db26cSSui Jingfeng 
44*f39db26cSSui Jingfeng 	const struct loongson_gfxpll_funcs *funcs;
45*f39db26cSSui Jingfeng 
46*f39db26cSSui Jingfeng 	struct loongson_gfxpll_parms parms;
47*f39db26cSSui Jingfeng };
48*f39db26cSSui Jingfeng 
49*f39db26cSSui Jingfeng int loongson_gfxpll_create(struct drm_device *ddev,
50*f39db26cSSui Jingfeng 			   struct loongson_gfxpll **ppout);
51*f39db26cSSui Jingfeng 
52*f39db26cSSui Jingfeng #endif
53